1.

Decoders
2. Encoders, Priority Encoders
1.Decoders:
Definition:

A decoder is the combinational circuit that converts binary information from ‘n’
input lines to a maximum of output lines.

Decoders are usually referred to as n line to line decoders; e.g. a 3 line to 8

line decoder.

Fig 4.1 : 3 to 8 line decoder (without enable input)

The three inputs are decoded into the eight outputs, each output represents one
of minterms of three input variables. Generally an Enable input is also provided
to control the circuit. We will talk enable input in the later section.

Combinational logic implementation:

• A decoder provides minterms of n input variable. Since any boolean

function is sum of minterms (canonical form). We can use additional OR
gate to sum the minterms.

• Therefore any combinational circuit with n inputs and m outputs can be

implemented n to line decoder and OR gates.

Problem: 1, Implement a full adder with decoder circuit and two OR gates

Solution:

First write down the truth table for the Full adder whose inputs are x,y,z
and output are S (sum) and C(carry) {do it yourself or refer Full adder}.

S(x,yz)= ∑(1,2,4,7)

C(x,y,z)= ∑(3,5,6,7)

Since there are three inputs, there are total 8 minterms available. Therefore we
need to use 3 line to 8 line decoder. This decoder generates 8 outputs for three
inputs.

To Implement sum S of full adder we have to add the minterms 1,2,4,7 using an
OR gate. Similarly, to implement carry C minterms 3,5,6,7 can be added using
a OR gate.
Z

Fig 1.1 : Implementation of decoder using 3 x8 decoder

Note: A function with a long list of minterms requires an OR gate with a large
number of inputs. A function F having a list of k minterms can be expressed in
its complemented form F' with 2n – k minterms. If the number of minterms in a
function is greater than 2n/2, then F' can be expressed with fewer minterms than
required for F. In such a Case it is advantageous to use a NOR gate to sum the
ninterms of F'. The output of the NOR gate will generate the normal output F.

1.1 Decoders with the enable input:

Let us consider 2 to 4 line decoder

Case 1: Decoder with active high Enable

A
B

A D0
D0
D1
B
2 X 4 line decoder D2
D1

D3
D2

D3
E (Enable)
E (Enable)

Fig 1.2 : 2 to 4 line decoder with active high Enable

E A B D0 D1 D2 D3
0 X X 0 0 0 0
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1

Fig 1.3 Truth table for the 2 to 4 line decoder with active high enable

When the enable is active high, all the output gates are equal to zero when E=0,

When E=1, it will be enabled as a decoder as we can see from the truth table in
the Fig 1.3.

Case 2: Decoders with active low enable: (Implementation with NAND

gates)
A

D0

D1

D2

D3

E (Enable)

Fig 1.4 : 2 to 4 line decoder with active low Enable

Here we can observe that for the active low enable, we have active low
output.The circle in the enable and outputs signify the enable low input, and low
outputs respectively.
The decoder works when the enable input =0 in active low condition otherwise
the all the output will be one irrespective of the input. When enable is in active
low, one of the output will be zero corresponding to particular input. The details
can be analysed from the truth table below.

E A B D0 D1 D2 D3
1 X X 1 1 1 1
0 0 0 0 1 1 1
0 0 1 1 0 1 1
0 1 0 1 1 0 1
0 1 1 1 1 1 0

Fig 1.5 : Truth table for the 2 to 4 line decoder with active low enable

1.2 Demultiplexer:

A decoder with an enable input can function as a demultiplexer. A

demultiplexer is a circuit that receivės information on a single line and transmits
this information on one of 2n possible output lines. The selection of a specific
output line is controlled by the bit values of n sclection lines. The decoder can
function as a demultiplexer if the E line is taken as a data input line and lines A
and B are taken as the selection lines. This is shown in Fig. 1.6 (b). The single
input variable E has a path to all four outputs,but the input information is
directed to only one of the output lines, as specified by the binary value ộf the
two selection lines, A and B. This can be verified from the truth table of the
circuit, shown in Fig. 1.5 For example, if the selection lines. AB = 10, output
D3 will be the same as the input value E, while all other outputs are maintained
at 1. Because decoder and demultiplexer operations are obtained from the same
circuit a decoder with an enable input is referred to as a decoder/demultiplexer.
It is the euable input that makes the circuit a demultiplexer; the decoder itself
can use AND, NAND, or NOR gates.
Fig 1.6 : (a) Decoder with enable (b) Demultiplexer

Decoder/demultiplexer circuits can be connected together to form a larger

decoder circuit. Figure 1.7 shows two 3 x 8 decoders with enable inputs
connected to form a 4 x 16 decoder. When w= 0, the top decoder is enabled and
the other is disabled. The bottom decoder outputs are all 0's, and the top eight
outputs generate minterms 0000 to 0111. When w = 1, the enable conditions are
reversed; the bottom decoder output. Generate minterms 1000 to 1111, while
the outputs of the top decoder are all 0’s.

Fig 1.7 : 4 X 16 decoder constructed using two 3 x 8 decoders

2. Encoders and Parity encoders:

• An encoder is the combinational circuit that performs the inverse

operation of decoder. Encoder has input lines and n output lines.

• The output line generate binary code corresponding to input value.

• An example of encoder is octal to binary (8 x 3 encoder).

• Process the data to small number of bits.

An example of an encoder is an octal to binary encoder. An octal to binary

encoder accept eight inputs and produces a 3-bit output code corresponding to
the activated input. The truth table for the octal to binary encoder is shown
below in table

Fig 2.1 Truth table for 8 x 3 encoder (octal to binary)

It has eight inputs, one for each octal digit and three outputs that generate the
corresponding binary number. The truth table shows that Y0 must be 1
whenever the input O1 or O3 or O5 or O7 is high.

Thus, Y0 = O1 + O3 + O5 + O7

Similarly Y1 = O2 + O3 + O6 + O7 and

Y2 = O4 + O5 + O6 + O7.

Using these three expressions, the circuit can be implemented using three 4-
input OR gates as shown in Fig 2.2. thus encoders are implemented using OR
gates.
Fig 2.2 8 x3 encoder (octal to binary encoder)

The encoder has two limitations:

1. Only one input can be active at any given time. If two or more inputs are
equal to 1 at the same time, the O/P is undefined. For example if O2 and O5 are
active simultaneously, the o/p of encoder will be 111 that is equal to binary 7.
This does not represent binary 2 or 5.

2. The output with all 0’s is generated when all inputs are ‘0’, and is also true
when O0 = ‘1’.

The first problem is taken care by a circuit, called as ‘priority encoder’. It

establishes a priority to ensure that only one input is active (High) at a given
time.

The second problem is taken care by an extra line in the encoder output, called
‘valid output indicator’ that specifies the condition that none of the inputs are
active

Priority encoder:
A priority encoder is an encoder that includes priority function. If two or more
inputs are equal to 1 at the same time, the input having the highest priority will
take precedence. To understand priority encoder, consider a 4 to 2 line encoder
which gives priority to higher subscript number input than lower subscript
number.
The truth table is given below. Truth Table of 4 to 2 line priority encoder:

The X’s are don’t care conditions. Input D3 has the highest priority, so
regardless of values of other inputs, when this input is 1, the output Y1 Y2 = 11.
D2 has next priority level. The o/p is 10 if D2 is 1, provided D3 = 0, irrespective
of the values of the other two lowerpriority inputs. The o/p is 01 if D1 is 1,
provided both D2 and D3 are 0, irrespective of the value of lower-priority input
D0. The o/p is 00 if D0 = 1, provided all other inputs are 0. A valid output
indicator, V is set to 1, only when one or more of the inputs are equal to 1. If all
the inputs are 0, V is equal to 0 and the other two outputs of the circuit are not
used. Now, simplifying using k-map the outputs can be written as :

The logic diagram for a 4 to 2 line priority encoder with ‘valid output indicator’
is shown below in Fig. below

Fig 4 to 2 line parity encoder with valid output indicator