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Chapter 4

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78 views

Chapter 4

Uploaded by

Lemma Deme Researcher
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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CHAPTER 4

COMBINATIONAL LOGIC FUNCTIONS

INTRODUCTION
oCombinational logic circuits are circuits in which the output at any time
depends upon the combination of input signals present at that instant only, and does
not depend on any past conditions.
oIn particular, the output of particular circuit does not depend upon any past
inputs or outputs i.e. the output signals of combinational circuits are not feedback to
the input of the circuit.
oMoreover, in a combinational circuit, for a change in the input, the output
appears immediately, except for the propagation delay through circuit gates.
ADDERS
oThe most common arithmetic operation in digital systems is the addition of
two binary digits.
oThe combinational circuit that performs this operation is classified as half-
adder and full adder

Half Adder

oIt has two inputs A and B. that are two 1-bit members, and two output sum (S)
and carry (C) produced by addition of two bits.
2. Truth Table

oThe sum output is 1 when any of inputs (A and B) is 1 and the carry output is 1
when both the inputs are 1.
3. Using a two variable k-map, separately for both outputs S and C.
4. Logical Implementation.
(i) Using Basic gates

(ii) Using XOR gate.


Full Adder
oFull adder is a combinational circuit that performs the addition of three binary
digits.
1.Fig. shows a full adder (FA).
oIt has three inputs A, B and C and two outputs S and Co produced by addition of
three input bits.
oCarry output is designated Co just to avoid confusion between with i/p variable
C.

2. Truth Table:
oThe eight possible combinations of three input variables with the irrespective
outputs are shown.
oWe observe that when all the three inputs are 1, the sum and carry both
outputs, are 1.
3. Using a three variable map for both outputs.
4. Logical Implementation.
(i) Using basic gates.
ii) A ‘Full Adder’ can also be implemented using two half adders
and an ‘OR’ Gate
Block Diagram representation of a full adder using two half address:
S1 and C1 are outputs of first half adder (HA1)

S2 and C2 are outputs of second half adder (HA2)

A, B and C are inputs of Full adder.


Sum and Cout are outputs of full adder.

MAGNITUDE COMPARATOR
oA magnitude comparator is a combinational circuit designed primarily to
compare the relative magnitude of the two binary numbers A and B.
o Naturally, the result of this comparisons specified by three binary variables that
indicate, whether A > B, A = B or A < B.
The block diagram of a single bit magnitude comparator is shown in Fig. 1.

Fig. 1 Block diagram of single bit magnitude comparator.


oTo implement the magnitude comparator the properties of Ex-NOR gate and AND gate is used.

Fig. 2(a) shows an EX-NOR gate with two inputs A and B. If A = B then the output of
Ex-NOR gate is equal to 1 otherwise 0.

Fig. 2(a)
oFig. 2(b) and (c) shows AND gates, one with A and B' as inputs and another
with A'and B as their inputs.

Fig. 2(b) Fig. 2(c)


oThe AND gate output of 2(b) is 1 if A > B (i.e. A = 1 and B = 0) and 0 if A < B
(i.e. A = 0 and B = 1). Similarly the AND gate output of 2(c) is 1 if A < B (i.e. A = 0
and B =1) and 0 if A > B (i.e. A = 1 and B = 0).
oIf the EX-NOR gate and two AND gates are combined as shown in Fig. 3, the
circuitwith function as single bit magnitude comparator.
oFor EX-NOR implementation.

Fig. 3 Single bit magnitude comparator.


We have used EX-OR followed by an inverter.
Truth table of a single bit magnitude comparator.

It clearly shows Y1 is high when A > B.


Y2 is high when A = B.
Y3 is high when A < B.
MULTIPLEXER

Multiplexers provide a way of selecting one out of many digital signals.


A multiplexer will in general have n inputs, and obviously one output, with m
control lines which are used to select one of the n inputs.
Which of n-input channels is routed through to the output is determined by the
bit pattern on the m control lines.
Hence, the number of input lines that can be multiplexed is 2 m. The basic
structure of an n-input multiplexer is n (m+ 1) input AND gates (that is one AND
gate to decode each of the n=2m possible combinations of the m control inputs), all
feeding into a single OR gate.
The extra (to the m control lines) input to each gate is connected to one of the
n inputs.
Fig. 1 Block diagram of an n-to-1 multiplexer

oMultiplexers are usually referred to as n-to-1 or 1-of-n multiplexers or data selectors.


oThe operation is based upon the fact that only one of the 2 m possible input
combinations can ever be applied to the control inputs at any one time, and therefore
only the corresponding AND gate will be capable of giving an output other than 0.
oThis is the gate whose input will be routed through to the output.
2-to-1 multiplexer
o Fig. 2 is the circuit diagram of a 2-to-1 multiplexer. It has two inputs (n=2),
with a single control line (m=1).
oIf A=0 then the output from the AND gate with D1 as an input must be 0 (since any

thing AND’d with 0 is 0) whilst the output from the other AND gate will be
A`.D0 = 1.D0 =D0.

So, the output from the multiplexer is Y = D0 + 0 = D0. By similar reasoning if A =1

then Y = D1. In Boolean algebraic terms:

Fig. 2 A2-to-1 multiplexer


Demultiplexers

 Demultiplexers provide the reverse operation of multiplexers since they allow a single
input to be routed to one of n outputs, selected via m control lines (n=2 m).
 This circuit element is usually referred to as a 1-of-n demultiplexer.
 The circuit basically consists of n AND gates, one for each of the 2 m possible combinations
of the m control inputs, with the single line input fed to all of these gates. Since only one
AND gate will ever be active this determines which output the input is fed to.
 The block, and circuit, diagram of a 1-of-4 demultiplexer is shown in fig.
Fig. The block and circuit diagrams of a 1-of-4 demultiplexer
Encoders
 An encoder is a multiplexer without its single output line.
 It is a combinational logic function that has2n(or fewer) input lines and n output lines,
which correspond to n selection lines in a multiplexer.
 Then output lines generate the binary code for the possible 2 ninput lines.
 Let us take the case of an octal-to-binary encoder. Such an encoder would have eight
input lines, each representing an octal digit, and three output lines representing the
three-bit binary equivalent.
 The truth table of such an encoder is given in Table. In the truth table, D 0 to D7 represent
octal digits 0 to 7. A, B and C represent the binary digits.
Table: Truth table of an encoder

 The eight input lines would have 28= 256 possible combinations. However, in the case of
anoctal-to-binary encoder, only eight of these 256 combinations would have any
meaning.
 The remainingc ombinations of input variables are ‘don’t care’ input combinations. Also,
only one of the input lines at a time is in logic ‘1’ state. Figure shows the hardware
implementation of the
octal-to-binaryencoder described by the truth table in Table. This circuit has the shortcoming
that it produces anall 0s output sequence when all input lines are in logic ‘0’ state. This can be
overcome by having aadditional line to indicate an all 0s input sequence.

Fig. Octal-to-binary encoder.


Decoders
A decoder is a combinational circuit that decodes the information on n input lines to a
maximum of 2nunique output lines.
Figure 1 shows the circuit representation of 2-to-4, 3-to-8 and 4-to-16 line decoders. If there
are some unused or ‘don’t care’ combinations in the n-bit code, then there will be fewer than
2noutput lines.
if there are three input lines, it can have a maximum of eight unique output lines.
If, in the three-bit input code, the only used three-bit combinations are 000, 001, 010, 100,
110 and 111 (011 and 101 being either unused or don’t care combinations), then this decoder
will have only six output lines.
In general, if n and m are respectively the numbers of input and output lines, then m ≤ 2 n.
Figure 1 Circuit representation of 2-to-4, 3-to-8 and 4-to-16 line decoders.

 A decoder can generate a maximum of 2npossible minterms with an n-bit binary


code.
 In order to illustrate further the operation of a decoder, consider the logic circuit
diagram in Fig. 2. This logic circuit implements a 3-to-8 line decoder function.
 This decoder has three inputs designated as A, B and C and eight outputs designated
as D0, D1, D2, D3, D4, D5, D6 and D7. From the truth table given along with the logic
diagram it is clear that, for any given input combination, only one of the eight
outputs is in logic ‘1’ state.
 Thus, each output produces a certain minterm that corresponds to the binary
number currently present at the input.
 In the present case, D0, D1, D2, D3,D4, D5, D6 and D7 respectively represent the
following minterms:
D4 A. B'.C'
Figure 2 Logic diagram of a 3-to-8 line decoder

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