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Recitation 2

The document contains a series of questions and solutions related to computer organization, specifically focusing on microprogramming and register operations. It includes implementations of memory subtraction, machine code conversions, register contents during instruction execution, and symbolic microprograms for stack operations. Additionally, it provides a program for Mano’s Basic Computer that mimics a given C code functionality.

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10 views

Recitation 2

The document contains a series of questions and solutions related to computer organization, specifically focusing on microprogramming and register operations. It includes implementations of memory subtraction, machine code conversions, register contents during instruction execution, and symbolic microprograms for stack operations. Additionally, it provides a program for Mano’s Basic Computer that mimics a given C code functionality.

Uploaded by

Ali Huseynov
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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BLG222E

Computer Organization
Recitation 2
Spring 2024
23.05.2024
QUESTION 1-a
(a) In accord with the given CPU organization, implement
memory subtract (MES) that subtracts the value of AC
register from the given address at the memory, and
write the result to the next address:

M[EA + 1] ß M[EA] - AC

Assume that the opcode for MES is 0100.

Ignore fetch and decode cycles and assume that the


effective address is already in AR register (i.e. ignore
indirect addressing mode).

Write a micro-program that will implement MES


instruction. Use the microinstruction format that is given
in Figure 1, and mapping algorithm given in Figure 2.
SOLUTION 1-a
𝑀[𝐸𝐴 + 1] ← 𝑀[𝐸𝐴] − 𝐴𝐶

𝐷𝑅 ← 𝑀 𝐴𝑅 , 𝐴𝐶 ← 𝐴𝐶′
2’s complement of AC
𝐴𝐶 ← 𝐴𝐶 + 1, 𝐴𝑅 ← 𝐴𝑅 + 1
𝐴𝐶 ← 𝐴𝐶 + 𝐷𝑅
𝐷𝑅 ← 𝐴𝐶
𝑀[𝐴𝑅] ← 𝐷𝑅
𝐷𝑅 ← 𝑀 𝐴𝑅 , 𝐴𝐶 ← 𝐴𝐶′
SOLUTION 1-a 𝐴𝐶 ← 𝐴𝐶 + 1, 𝐴𝑅 ← 𝐴𝑅 + 1
𝐴𝐶 ← 𝐴𝐶 + 𝐷𝑅
0010000 = 16 (decimal)
𝐷𝑅 ← 𝐴𝐶
𝑀[𝐴𝑅] ← 𝐷𝑅

ORG 16
MES: READ, COM U JMP NEXT
INCAC, INCAR U JMP NEXT
ADD U JMP NEXT
ACTDR U JMP NEXT
WRITE U JMP FETCH
QUESTION 1-b
(b) Convert your micro-program from part (a) into
machine codes using codes that are given in
Figures 1 and 3.
SOLUTION 1-b

Index Address (7) F1 (3) F2 (3) F3 (3) CD (2) BR (2) AD (7)

1 0010000 000 100 010 00 00 0010001

2 0010001 011 000 111 00 00 0010010

3 0010010 001 000 000 00 00 0010011

4 0010011 000 101 000 00 00 0010100

5 0010100 111 000 000 00 00 1000000


𝐷𝑅 ← 𝑀 𝐴𝑅 , 𝐴𝐶 ← 𝐴𝐶′
𝐴𝐶 ← 𝐴𝐶 + 1, 𝐴𝑅 ← 𝐴𝑅 + 1
𝐴𝐶 ← 𝐴𝐶 + 𝐷𝑅
𝐷𝑅 ← 𝐴𝐶
𝑀[𝐴𝑅] ← 𝐷𝑅
QUESTION 2
Show the content of registers PC, AR, IR, and SC of the basic computer in
hexadecimal when the
following instruction is fetched from memory and executed.

• The initial content of PC is 1B1.


• The content of memory at address 1B1 is 52FF.
• The content of memory at address 2FF is 0B43.
• The content of memory at address B43 is 0DFF.

Show the contents of the registers along with the corresponding RTL
statements after the positive
transition of each clock pulse using a chart.
MEMORY
Address Content
1B1 52FF
SOLUTION 2 … …

2FF 0B43
Time Microoperation PC AR IR I SC
… …
T0 AR ß PC 1B1 1B1 - - 1
B43 0DFF
T1 IR ß M[AR], 1B2 1B1 52FF - 2
PCßPC+1 PC 1B1
T2 Decode ß IR[12-14] 1B2 2FF 52FF 0 3
AR ß IR[0-11]
I ß IR[15]
T3 Nothing 1B2 2FF 52FF 0 4
T4 M[AR] ß PC 1B2 300 52FF 0 5
AR ß AR +1
T4 PC ß AR, SC ß 0 300 300 52FF 0 0

BSA = Branch
and Save
Address
QUESTION 3-a

Consider the instruction 0x1D00. Describe


very shortly, what this instruction performs.
SOLUTION 3-a
0x1D00 = 0001 1101 0000 0000

Opcode: 0x03 = PSH (no address mode)

Destreg: 101

Srcreg1: 000 à R0

Srcreg2: 000

Not used: 00

M[SP] ß R0, SP ß SP - 1
Push content of R0 to Stack.
QUESTION 3-b

Write the sequence of microoperations using RTL


that are required to exececute the instruction given
on part a. Specify the values of relevant control
signals.
SOLUTION 3-b

T3D3: M[SP] ß R0, SP ß SP – 1, SC ß 0

M[SP] ß R0:
• OutASel = 00
• FunSelALU = Transfer A
• OutCSel = 11
• MuxBSel = 00
• MemLoad = 1

SP ß SP – 1
• FunSel = 10
• RegSel = 111
QUESTION 4

Write a symbolic microprogram for PSH (Opcode:101) and PULL (Opcode:110)


using the information given. Beware of the changed mapping algorithm:
CAR[3 - 5] ß IR(12 - 14),CAR[0,1,2,6] ß 0

There is no need to implement fetch&decode cycles. Just assume that there is


subroutine for fetch
(FETCH) available for your convenience that you can branch.
SOLUTION 4

CAR[3 - 5] ß IR(12 - 14),CAR[0,1,2,6] ß 0


PUSH: 0101000 = hex(28)

RTL: Symbolic:
ORG 0x28

T2K5: SP ß SP – 1 PSH: NOP, DECSP, NOP U J NEXT


T3K5: AR ß SP NOP, NOP, SPTAR U J NEXT
T4K5: M[AR] ß DR WRITE, NOP, NOP U J FETCH
SOLUTION 4

CAR[3 - 5] ß IR(12 - 14),CAR[0,1,2,6] ß 0

PULL: 0110000 = hex(30)


RTL: Symbolic:
ORG 0x30

T2K6: AR ß SP PULL: NOP,NOP, SPTAR U J NEXT


T3K6: DR ß M[AR], SP ß SP + 1, NOP, READ,NOP U J NEXT
NOP, INCSP, NOP U J FETCH
QUESTION 5
Write a program for Mano’s Basic Computer to perform the
same operations as done by the following C code. Specify
all the hex codes of instructions. You must write both if and
else blocks even if they do not execute. Assume that the
program starts at 0x100. Note that uint8_t refers to eight-
bit unsigned value.
SOLUTION 5
ORG 100 ; Starting address of the program

; Load number1 (0x300) into AC


LDA 300 ; AC = M[300]
CMA ; Complement AC (to perform subtraction)
INC ; Increment AC (to perform 2's complement)
ADD 350 ; AC = AC + M[350]
SZA ; Skip next instruction if AC is zero
BUN ELSE ; Branch to ELSE if not equal

; IF BLOCK: *number3 = *number2


LDA 350 ; Load value at 0x350 into AC
STA 400 ; Store AC at 0x400
BUN ENDIF ; Skip else block

; ELSE BLOCK
ELSE, LDA 300 ; Load value at 0x300 into AC
STA 400 ; Store AC at 0x400

; Set *number1 = 0
ENDIF, CLA ; Clear AC
STA 300 ; Store 0 at 0x300

; Set *number2 = 0
STA 350 ; Store 0 at 0x350

HLT ; Halt the program

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