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SystemVerilog Concepts

The document outlines key SystemVerilog concepts, including data types like 'byte', 'bit', 'logic', and their differences, as well as arrays, structures, and loops. It explains the importance of randomization, module versus program blocks, and various coverage types for verification. Additionally, it highlights the use of interfaces, modports, and the distinction between code and functional coverage.

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10 views

SystemVerilog Concepts

The document outlines key SystemVerilog concepts, including data types like 'byte', 'bit', 'logic', and their differences, as well as arrays, structures, and loops. It explains the importance of randomization, module versus program blocks, and various coverage types for verification. Additionally, it highlights the use of interfaces, modports, and the distinction between code and functional coverage.

Uploaded by

suresh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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SystemVerilog Concepts

1. Difference between byte a and bit [7:0]?


In SystemVerilog, 'byte' is an 8-bit data type that can hold signed or unsigned values, while
'bit [7:0]' is an array of 8 bits that hold only unsigned values.

Bit has only two states 0,1

Byte has four states 0,1,x,z

2. Why logic is introduced in SV? Or Why reg and wires are not sufficient?
'logic' was introduced in SystemVerilog to overcome the limitations of 'reg' and 'wire'.
Unlike 'reg', which can have multiple drivers, 'logic' can hold 4 states (0, 1, x, z) and is easier
to use for modeling digital circuits without ambiguity.

Wire: To connect the output of a module to the input of another module, To connect a signal
from a test-bench to a module under test.

Reg: To store the value of a counter, To store the state of a finite state machine.

Logic: To represent the output of a multiplexer, To represent the value of a signal that is
driven by multiple sources, such as the output of a shared bus.

3. Difference between reg and logic?


'reg' can represent a variable that holds a value in procedural blocks, but can be driven by
multiple sources. 'logic', on the other hand, can also hold values in procedural blocks but
can only be driven by a single source, making it more suitable for RTL design.

4. What are 2 state and 4 state variables? Provide some examples.


2-state variables can be either 0 or 1 (e.g., 'bit'). 4-state variables can represent 0, 1, x
(unknown), and z (high impedance) (e.g., 'logic', 'reg').

5. Difference between integer and int?


The difference between int and integer data type is that, int is a 2-state (0,1) data type and
integer is a 4-state ( 0,1,x,z) data type. The default initialization value of int data type is '0′
and integer data type is 'x'.

6. Difference between packed and unpacked arrays.


Packed arrays are contiguous in memory and can be indexed directly (e.g., 'logic [7:0]
my_array'). Unpacked arrays can be used as arrays of variables and are not contiguous (e.g.,
'logic my_array [7:0]').
7. Difference between dynamic and associative arrays.
Dynamic arrays are resizable arrays that can be allocated and deallocated during runtime
(e.g., 'logic my_array[];'). Associative arrays are indexed by keys and do not have a fixed size
(e.g., 'logic my_array[string];').

In Dynamic arrays memory has to be allocated before use.

In Associative memory memory is created when ever in use.

8. Difference between dynamic array and queue.


Dynamic arrays are resizable and can have any number of elements, while queues are
ordered collections of elements that can be added or removed from either end (e.g., 'logic
my_queue[];').

9. Difference between structure and union.


Structure: Allows all members to store values simultaneously, and each has its own
dedicated memory.

Union: All members share the same memory, and only one member can hold a value at a
time, as writing to one will overwrite the others.

Both structure and union holds different data types (not like array which hold only same
data type)

10. Difference between while and do while questions.


In a 'while' loop, the condition is checked before executing the loop body. In a 'do while'
loop, the body is executed at least once before the condition is checked.

11. Difference between function and task.


Functions return a value and cannot have time delays. Tasks can have time delays and do
not return values directly, but can modify variables passed by reference.

12. What are pass-by-value and pass-by-reference methods?


Pass-by-value means passing a copy of the variable's value to the function, while pass-by-
reference passes the variable itself, allowing the function to modify the original variable.

13. Why do we need randomization in SystemVerilog?


Randomization is essential for verification to generate different test scenarios, ensuring that
the design is tested under a wide range of conditions.
14. Difference between module and program block?
Modules define hardware structures, while program blocks are used for testbenches,
providing a separate scope to avoid race conditions and allowing for non-blocking
assignments.

15. How do program block avoid the race condition?


Program blocks avoid race conditions by providing a separate simulation context where
signals can be assigned without interference from other processes.

16. Difference between === and == operators?


The '===' operator is a strict equality operator that checks for exact matches, including
unknown states (x, z), while '==' ignores the unknown states.

17. What are SystemVerilog interfaces and why are they introduced?
Interfaces group related signals together, simplifying module connections and improving
readability and maintainability of code.

18. What is modport and clocking block?


Modports define the direction of signals in an interface (input, output), while clocking
blocks synchronize signal sampling and driving to a specific clock edge.

19. What is the final block? Difference between initial and final block.
The final block is executed at the end of the simulation, while the initial block is executed at
the start. Final blocks are used for cleanup tasks.

20. What is cross-coverage?


Cross-coverage is a technique to measure how many combinations of different variables
have been covered in tests, ensuring a more thorough verification process.

21. Difference between code and functional coverage?


Code coverage measures which lines of code were executed during simulation, while
functional coverage assesses whether specific functionalities have been exercised.

22. Different types of code coverage.


Common types of code coverage include line coverage, branch coverage, toggle coverage,
and expression coverage, each providing insights into different aspects of code execution.

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