Z80

Z80 Microprocessor
Dept. of Information & Communication Myung-Eui Lee

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Z80 Microprocessor

Z80

Z80 CPU
Long life cycle over 30 year
Microchip PIC, Motorola 6805, Intel MCS51

Bus master/arbitration
Multiprocessor, DMA support

10 addressing modes Various Interrupts

Maskable, Non-Maskable, Daisy chain

DRAM refresh circuit Z8 Single chip instruction compatible

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Z80 Microprocessor

Z80
Language

Programming

Machine Language : binary Assembly Language : Assembler 3 fields : Label, Operation/operand, comments
Label : op code operand pseudo instruction ; comments

Pseudo Instruction : ORG, EQU, DB, DW, DS, END High Level Language : Compiler

Assembly Language
1. Register 2. Memory, I/O Address Map 3. Addressing Modes

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Z80 Microprocessor

Z80
Symbol

Assembler

A, B, C, D, E, H, L, AF, BC, DE, HL, IX, IY, SP Z, NZ, C, NC, PO, PE, P, M

Constant/Literal
LD A, 0 LD A, FFh LD A, 11110000b LD A, A LD A, 5 LD A, 5h LD A, (5) savreg MACRO PUSH AF PUSH BC PUSH DE PUSH HL ENDM

Directives
ORG, EQU, DB, DW, DS, END Macro : savreg Macro : Assembly time facility (Preprocessor) Subroutine : Execution time facility

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Z80 Microprocessor

Z80

Registers
Main/Alternate Register General/Special Purpose Register

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Z80 Microprocessor

Z80

Register
Main Register : A, F, B, C, D, E, H, L
A (ACC) : holds the results of arithmetic or logical operations Input/Output with peripheral devices. F (Flag) : indicates specific conditions for operations S (Sign) : 1(-)/0(+) Z (Zero) : 1(0)/0(others) H (Half carry) : 1(carry or borrow at bit 3), BCD operation P/V (Parity/Overflow) P (Logical operation) : 1(1's Even parity)/0(Odd) V (Arithmetic operation) : 1(overflow)/0(normal) N (Negation) - 1(sub)/0(add) C (Carry) - 1(carry or borrow at bit 7)

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Z80 Microprocessor

Z80

Register
ADD A, B ( A A + B )
A : Destination (Result), B : Source Flag
S Z H P/V N C

affected according to the result of the operation not affected

Alternate Register : A', F', B', C', D', E', H', L'
EX AF, AF' A A', F F' EXX B B', C C', D D', E E',H H', L L'

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Z80 Microprocessor

Z80

Register
General purpose Register
8 bit : B, C, D, E, H, L, B', C', D', E', H', L' 16 bit : BC, DE, HL, BC', DE', HL'

Special function Register : PC, SP, IX/IY, I, R

PC (Program Counter) holds the 16-bit address of the current instruction being fetched from memory. automatically incremented after its contents have been transferred. the new value is automatically placed in the PC when a program jump occurs. SP (Stack Pointer) holds the 16-bit address of the current top of a stack (TOS). the Stack is located anywhere in external system RAM memory. The external stack memory is organized as a last-in first-out (LIFO) file. pushed onto the stack from specific CPU registers (PUSH). popped off of the stack to specific CPU registers (POP).
-8Z80 Microprocessor

Decrement
CALL, PUSH, Interrupt

Increment
RET, POP

Z80

Register
Special Function Register
Index Registers (IX/IY) hold a 16-bit base address used in indexed addressing modes. index register is used as a base to point to a region in memory. additional byte is to specify a displacement from this base. greatly simplifies the tables of data. Interrupt Register (I) allows interrupt routines to be dynamically located anywhere in memory. stores the high order eight bits of the indirect address. the interrupting device provides the lower eight bits of the address. Refresh Register (R) Used as the memory refresh counter when the DRAM is used for memory. The low order 7 bits of R is automatically incremented for each instruction fetch.
-9Z80 Microprocessor

Z80

Register Notations
n : 8 bits immediate data nn' : 16 bits immediate data d : displacement (8 bit : -128 ~ +127 ) e : effective address (8 bit : -128 ~ +127 ) r, r' : A, B, C, D, E, H, L ss : BC, DE, HL, SP pp : BC, DE, IX, SP rr : BC, DE, IY, SP qq : AF, BC, DE, HL b : 0, 1, 2, 3, 4, 5, 6, 7 (bits) cc : Z, NZ, C, NC, PO, PE, P, M (conditions)
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Z80 Microprocessor

Z80

Instruction Types
8/16 bit Data Transfer (memory and register read/write) Exchange, Block Transfer and Search 8 bit Arithmetic and Logical (16 bit Arithmetic) General purpose Arithmetic (DAA, CPL, NEG) CPU Control (CCF, SCF, NOP, HALT, EI, DI, IM) Rotate and Shift Bit Manipulation (SET, RESET, TEST) Jump, Call, and Return Input/Output

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Z80 Microprocessor

Z80

Instructions
8 bit Memory Read/Write
LD A, (nn) LD (nn), A LD HL, (nn') LD (nn'), HL
A (nn) (nn) A

16 bit Memory Read/Write

L (nn), H (nn+1) (nn) L, (nn+1) H

PUSH qq
PUSH HL
(SP - 1) H, (SP - 2) L, SP SP - 2

POP qq
POP HL
L (SP), H (SP + 1), SP SP + 2

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Z80 Microprocessor

Z80
Subroutine CALL
CALL nn

Instructions
(SP - 1) PCH, (SP - 2) PCL, SP SP 2, PC nn

Subroutine RETURN
RET PCL (SP),
PCH (SP + 1), SP SP + 2

Stack Operation

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Z80 Microprocessor

Z80
LDI

Instructions
HL : source, DE : destination, BC : count Operation (DE) (HL), HL HL + 1, DE DE + 1, BC BC - 1 P/V (Parity) PE (=1) : branch if BC has not been decremented to 0 (BC 0) PO (=1) : branch if BC has been decremented to 0 (BC= 0) Block Transfer 10 bytes from 4000h to 40A0h
LD LD LD LDI JP HL, 4000h DE, 40A0h BC, 0Ah PE , LOOP

LOOP:

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Z80 Microprocessor

Z80
CPI

Instructions
A : search pattern, HL : memory address, BC : count Operation A (HL), HL HL + 1, BC BC - 1 P/V (Parity) PE (=1) : branch if BC has not been decremented to 0 (BC 0) PO (=1) : branch if BC has been decremented to 0 (BC= 0) Pattern Search Pattern 23h from 40B0h to 40B9h (10 bytes)
LD LD LD CPI JR JP JP ; DEC ; A, 23h HL, 40B0h BC, 10 Z, FOUND PO, NOFND LOOP

LOOP:

FOUND: NOFND:

HL

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Z80 Microprocessor

Z80
DAA

Decimal Adjustment
Hexadecimal : CY=0, A=9Bh
LD A, 34h LD B, 67h ADD B
0011 0100 ( 34h ) + 0110 0111 ( 67h ) 1001 1011 ( 9Bh ) C =0 H=0

Decimal : CY=1, A=01

LD A, 34h LD B, 67h ADD B DAA

1001 1011 ( 9Bh ) + 0110 0110 ( 66h ) 0000 0001 ( 01 ) C =1 H=1 ; adjust 66h

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Z80 Microprocessor

Z80

Rotate/Shift
Rotate Left/Right Circular : RLC/RRC

Rotate Left/Right : RL/RR

Shift Left/Right Arithmetic : SLA/SRA

CY

b7

b0

CY

b7

b0

Shift Left/Right Logical : SRL (no SLL = SLA)

Sign unchanged

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Z80 Microprocessor

Z80

Jump / Hand Assemble

Jump types
Absolute Jump : JP nn Conditional Jump : JP NZ, nn Relative Jump : JR e

JR e : PC PC + e ( = e 2)
Address Op. Code 0C71 2004 0C73 CBF9 0C75 3E12 0C77 E63F PLAY: Instruction JR NZ, PLAY SET 7, C LD A, 12h AND 3Fh

-128 ~ +127

-126 ~ +129

DJNZ e : B B -1, if B 0 then PC PC + e

LD A, 0 LD B, 3 LOOP: INC A ; ; DJNZ LOOP LD A, 0 LD B, 3 LOOP: INC A ; DEC B JR NZ, LOOP

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Z80 Microprocessor

Z80
RST p

I/O Read and Write

PCL p, PCH 0

I/O Read
IN A, (n) A7~ A0 n, A15~ A8 0, A (n) INI A7~ A0 C, A15~ A8 B, (HL) (C), B B -1, HL HL + 1 C : port #, HL: memory buffer address, B: counter INIR

I/O Write
OUT (n) , A A7~ A0 n, A15~ A8 A, (n) A OUTI A7~ A0 C, A15~ A8 B, (C) (HL), B B -1, HL HL + 1 OTIR

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Z80 Microprocessor

Z80

Addressing Mode
1. Implied/Implicit CPL XOR 30h 2. Immediate ADD A, 20h XOR 30h
8 bit constant

3. Extended Immediate LD HL, 1234h

16 bit constant

4. Register AND B LD A, B 5. Indirect (register indirect) LD A, (BC) LD A, (1234h) 6. Absolute/Direct JP 1234h LD HL, (1234h)
16 bit memory address (nn)

7. Modified Page Zero Addressing RST 8. Relative JR Addressing Mode Combination 9. Indexed LD A, (IX + 3) 10. Bit SET 0, A RES 3, (IX + 2)
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Z80
1 byte
Op. Code

Instruction Byte Length

CPL
2F

DAA
27

LD A, B
78

2 byte
Op. Code 1 Op. Code 2

CPDR
EB D9

INIR
ED B2

CP 50h
Op. Code 1 Operand 1

LD B, 5
06 05

FE

50

3 byte
Op. Code 1 Op. Code 2 Operand 1

AND (IX + 3)
DD A6 03

LD HL, 1234h
Op. Code 1 Operand 1 Operand 2 21 34 12

4 byte
Op. Code 1 Op. Code 2 Operand 1 Operand 2

LD IX, (1234h)
DD 21 34 12

BIT 1, ( IX + 2 )
Op. Code 1 Op. Code 2 disp. Operand 1 DD CB 02 4E

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Z80 Microprocessor

Z80

Z80 Overview
Z80 CPU
158 Instruction Sets 10 Addressing Modes 2 Interrupt Inputs NMI : Non-Maskable Interrupt INT : Maskable Interrupt Mode 0, 1, 2 Alternate Registers 2 Index Registers DRAM Refresh 8080 Instruction Compatible

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Z80 Microprocessor

Z80

I/O Pin Configuration

Address/Data/Control Bus : 40 pins

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Z80 Microprocessor

Z80

Block Diagram

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Z80 Microprocessor

Z80
Instruction Cycle

CPU Timing
1 Instruction Cycle = 1 ~ 6 Machine Cycle 1 Machine Cycle = 3 ~ 6 T Cycle

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Z80 Microprocessor

Z80

Instruction Cycle
1. Op. Code Fetch = M1 2. Memory Read 3. Memory Write 4. I/O Read 5. I/O Write 6. Bus Request / Acknowledge 7. INT Request / Acknowledge 8. NMI Request / Acknowledge 9. HALT Exit

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Z80 Microprocessor

Z80

Op. Code Fetch = M1

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Z80 Microprocessor

Z80

Memory Read / Write

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Z80 Microprocessor

Z80

Input and Output Device Read / Write

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Z80 Microprocessor

Z80

Bus Request / Acknowledge

* Sampled on the rising edge of the last T clock * Sampled on the rising edge of each Tx

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Z80 Microprocessor

Z80

INT Request / Acknowledge

* Sampled on the rising edge of the last T clock

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Z80 Microprocessor

Z80

NMI Request / Acknowledge

* NMI signal is detected in any timing of each instruction. * NMI F/F is sampled on the rising edge of the last T clock.

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Z80 Microprocessor

Z80

HALT Exit
Exit Conditions : INT, NMI, Reset

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Z80 Microprocessor

Z80

Reset Timing

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Z80 Microprocessor

Z80

CPU Reset
Cold Reset : Power On Reset (POR) Warm Reset : Reset Switch Soft Reset : Jump to 0000h (PC = 0000h)

Cold Reset Power-On

Warm Reset Reset S/W

VIH = 2.0V
Min. 3 Clocks

Time Period = e-(1/RC)t

Min. 3 Clocks

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Z80 Microprocessor

Z80

Bus / Interrupt Request Timing

Bust Request
The rising edge of the last T clock of any machine cycle.

INT Request
The rising edge of the last T clock of each instruction.

NMI Request
Detected in any timing of each instruction Sampled on the rising edge of the last T clock of each instruction

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Z80 Microprocessor

Z80

Instruction Cycle Example

LD A, (nn) : LD A, (8123h)
1. M1 : Op. Code Fetch M1, RD, MREQ Address : 4000h Data : 3Ah 2. M2 : Memory Read RD, MREQ Address : 4001h Data : 23h 3. M3 : Memory Read RD, MREQ Address : 4002h Data : 81h 4. M4 : Memory Read RD, MREQ Address : 8123h Data : AAh
Memory ACC

Address 4000h 4001h 4002h

AA 3A 23 81

8123h

AA

Memory Write = M4 LD (8123h), A

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Z80 Microprocessor

Z80

Instruction Cycle Example

OUT (n), A : OUT (80h), A
1. M1 : Op. Code Fetch M1, RD, MREQ Address : 4000h Data : D3h 2. M2 : Memory Read RD, MREQ Address : 4001h Data : 80h 3. M3 : I/O Write WR, IORQ Address : 80h Data : 55h
I/O Read = M3 IN A, (80h)
Memory ACC

Address 4000h 4001h

55 D3 80

I/O Address 80h

I/O

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Z80 Microprocessor

Z80

Pin Functions
Pin Function Summary : p. 8 Tab. 1-2 & p. 28 Tab. 1-2
Address A0 A15 : output, active high 16 bit address for memory ( 64KB ) 8 bit address for I/O ( 256 ) Refresh address during M1 ( A0 A6 : 7 bit ) Data D0 D7: input/output, active high 8 bit exchange with memory & I/O. Interrupt vector RD / WR: output, active low Indicates that the CPU wants to read / write data from / to memory or I/O. M1: output, active low together with MREQ, indicates that the current machine cycle is the opcode fetch cycle together with IORQ, indicates an interrupt acknowledge cycle.

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Z80 Microprocessor

Z80

Pin Functions
MREQ : output, active low LD indicates that the address bus holds a valid address for a memory read / write operation. Also active low during memory refresh ( RFSH ). IORQ : output, active low IN, OUT indicates that the lower half of the address bus (A0 A7) holds a valid I/O address for an I/O read / write operation. also generated concurrently with M1 during an interrupt acknowledge cycle. RFSH : output, active low together with MREQ during M1, indicates that the lower seven bits of the systems address bus (A0 A7) can be used as a refresh address to the systems dynamic memories.
I/O Mapped I/O : Intel Memory Mapped I/O : Motorola

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Z80 Microprocessor

Z80

Pin Functions
HALT : output, active low indicates that the CPU has executed a HALT instruction.. During HALT, the CPU executes NOPs to maintain memory refresh. HALT exit : INT, NMI, RESET WAIT : input, active low This signal indicates to the CPU that the addressed memory or I/O device is not ready for data transfer. Always sampled at T2. NMI : input, active low higher priority than INT. always recognized at the end of the current instruction, independent of the status of the interrupt enable flip-flop (IFF). automatically forces the CPU to restart at location 0066H.

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Z80 Microprocessor

Z80

Pin Functions
INT : input, active low Acknowledged a INT request at the end of the current instruction if the internal software-controlled interrupt enable flip-flop (IFF) is enabled. EI / DI Instruction Mode 0, 1, 2 BUSREQ : input, active low higher priority than NMI and is always recognized at the end of the current machine cycle. BUSREQ forces the CPU address bus, data bus, and control signals MREQ, IORQ, RD, and WR to go to a high-impedance state so that other devices can control these lines. BUSACK : output, active low indicates to the requesting device that the CPU address bus, data bus, and control signals MREQ, IORQ RD, and WR have entered their high-impedance states. The external circuitry can now control these lines.
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Z80

Pin Functions
RESET : input, active low initializes the CPU as follows Reset the interrupt enable flip-flop ( IFF = 0 ) Clear the PC ( PC = 0000h ) Clear registers I and R sets the interrupt status to Mode 0. the address and data bus go to a high-impedance state all control output signals go to the inactive state. RESET must be active for a minimum of three full clock cycles before the reset operation is complete. CLK : input Normally 5 20 Mhz according to data sheet VCC / GND : input

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Z80 Microprocessor

Z80

Timer Delay
LD r, n : M = 2, T = 7 1 T cycle = 1 / clock
10 MHz : 100 ns 500 KHz : 2 us
# of T cycle 7 7 4 4 10 4 4 10 10 loop count 7x1 7 x 64 18 x 16 x 64 4 x 64 4 x 64 10 x 64 10 x 1 20,049

TIMER: TT2: TT1:

LD LD DEC NOP JP DEC NOP JP RET

D, 40H E, 10H E NZ, TT1 D NZ, TT2

20,049 x 100 ns = 2 ms

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Z80 Microprocessor

Z80
1. Programmed I/O 2. Interrupt driven I/O 3. DMA 4. I/O Processor

Interrupt
I/O Transfer Modes

DMA (Direct Memory Access)

A
I/O

B
Memory

DMA

I/O

A. B. C. D. E.

Transfer between memory and I/O Transfer between memories Transfer between I/O and I/O Memory search I/O search

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Z80 Microprocessor

Z80

Interrupt
IFF : Interrupt Flip Flop
IFF 1 : Enable/Disable Interrupt Request IFF 2 : Temporary storage location for IFF1
Action CPU Reset DI INT acknowledge EI RETI RETN NMI acknowledge IFF1 0 1 N.C IFF2 0 IFF2 0 1 N.C 1 IFF1 INT Disable INT Enable No change IFF2 IFF1 restore IFF1 IFF2 save, INT disable Comments

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Z80 Microprocessor

Z80
NMI

Interrupt

NMI cannot be disabled by program. When a NMI has been accepted, the CPU performs the following processing: NMI F/F (latch) is set to 1 : refer to NMI cycle IFF1 is reset to 0 : disable INT IFF1 is copied into IFF2 : save EI/DI status PC is saved into the stack : return address Jump to 66h RETN instruction performs the followings: IFF2 is copied into IFF1 : restore PC is restored from the stack

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Z80 Microprocessor

Z80
INT

Interrupt
INT can be enabled or disabled by program. When a INT has been accepted, the CPU performs the following processing: Both IFF1 and IFF2 are reset to 0 : disable nested INT PC is saved into the stack : return address Serviced in one of the three modes : 0, 1 and 2 A mode is selected by executing the instruction IM0, IM1, IM2

Mode 0
The interrupting peripheral device puts a restart instruction (RST) on the data bus. t p RST p 000 00h
7 6 5 4 3 2 1 0 1 1

1 1 1

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001 010 011 100 101 110 111

08h 10h 18h 20h 28h 30h 38h Z80 Microprocessor

Z80

Interrupt
Mode 0 using priority encoder

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Z80 Microprocessor

Z80
Mode 1

Interrupt
Restart from address 0038h

Mode 2
Requires a 16-bit interrupt service address High order 8 bits = I register LD I, ABh Low order 8 bits = Z80 family I/O peripheral device IV reg.
Memory ISR 1234h
ABC0h I register DATA bus ABC1h
34h 12h
: : POP A RETI

16 bit address
msb lsb

high 8

low 8

EI PUSH A : :

ABh

C0h

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Z80 Microprocessor

Z80

Daisy Chain
Daisy Chain using Mode 2

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Z80 Microprocessor

Z80

Interrupt
Interrupt Summary
Interrupt Priority NMI
1

Mode
none

Vector Address
0066h Instruction from peripheral devices * RST instruction 0038h

Return Instruction
RETN

Mode 0

Mode 1

INT

2 Indirect 16 bit address specified by * I register : high order * Peripheral device : low order

RETI

Mode 2

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Z80 Microprocessor

Z80

Minimum Z80 Computer System

CPU, Memory (ROM), I/O (Digital Data)

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Z80 Microprocessor

Z80

Hardware Interface
Peripheral Interface
PIO, SIO, DMAC, CTC, FDC, HDC, CRTC, ADC/DAC, USB, Ethernet, Bluetooth etc

Address

Data

Data
RD

CPU
WR IORQ M1

Interface Chip

Control

Peripheral Devices

INT

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Z80 Microprocessor

Z80

Hardware Interface
Interface Chips

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Z80 Microprocessor

Z80

Microcomputer Design
Memory Interface
Address Map
Address 0000h
32 K x 8 bit ROM

Address Decode
ROM
A0 - A14 A0 - A14

A 15 CE

7FFFh 8000h
32 K x 8 bit SRAM
SRAM
A0 - A14

FFFFh
CE

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Z80 Microprocessor

Z80

Microcomputer Design
ROM / RAM
256 K bit = 32 K Byte x 8 bit 27256 ROM 62256 RAM

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Z80 Microprocessor

Z80

Microcomputer Design
ROM / RAM Read

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Z80 Microprocessor

Z80
RAM Write

Microcomputer Design

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Z80 Microprocessor

Z80

Microcomputer Design
Memory Control Signal

RD MRD MREQ
RD L H

Input WR H L H L

Output MREQ MRD L L H H L H H H MWR H L H H

WR

MWR

L H

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Z80 Microprocessor

Z80

Microcomputer Design
Memory Interface Circuit

D0 - D7 A0 - A14 A15

A0 - A14 CE

D0 - D7

(32K)
OE

A0 - A14 RD CE MREQ OE WR WE

D0 - D7

(32K)

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Z80 Microprocessor

Z80

Microcomputer Design
I/O Address Map

80h

Port A Port B Port C Control Port

8255 PPI

81h 82h 83h

8251 SIO

84h 85h

Data Port Control Port

88h

Counter #0 Counter #1 Counter #2 Control Port

8253 PIT

89h 8Ah 8Bh

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Z80 Microprocessor

Z80

Microcomputer Design
I/O Address Decode
b7 1 1 1 b6 0 0 0 b5 0 0 0
A7 G1 A6 G2A A5 G2B Y5 Y4 Y3 A0 Y6 A1 Y7 CS

8253 PIT

b4 0 0 0 b3 0 0 1 b2 0 1 0 b1 x x x b0 x x x
80h 84h 88h

A4 C A3 B A2 A A1 Y0 Y1 Y2

8251 C/D SIO

CS

CS A1

A0 A0

8255 PPI

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Z80 Microprocessor

Z80

Microcomputer Design
I/O Control Signal

RD IORD IORQ
RD L H

Input WR H L H L IORQ L L H H

Output IORD IOWR L H H H H L H H

WR

IOWR

L H

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Z80 Microprocessor

Z80

Microcomputer Design
I/O Interface Circuit
8

CS A1 A0 D0 - D7 A2 - A7 RD WR

D0 - D7

138 DECODER

A1 A0

CS C/D

D0 - D7

RD WR RD IORQ CS WR A1 A0 RD WR D0 - D7

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Z80 Microprocessor

Z80

8255 PIO/PPI
Parallel Input Output / Programmable Peripheral Interface

Group A

Group A

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Z80 Microprocessor

Z80

8255 PIO
Pin Configuration

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Z80 Microprocessor

Z80
8255 Port Address

8255 PIO

80h 81h 82h 80h 81h 82h 83h

8255 I/O Modes

Mode 0 : Input or Output Only (Unidirectional), No Handshake Mode 1 : Input or Output Only (Unidirectional), Handshake Mode 2 : Input and Output (Bidirectional), Handshake

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Z80 Microprocessor

Z80
1

8255 PIO
Control Register (83h)

D7 : 1 = Mode & I/O setting / 0 = Port C bit set & reset D6 D5 : Group A Mode Definition 0 0 = Mode 0 / 0 1 = Mode 1 / 1 x = Mode 2 D4 : Port A I/O Definition 0 = Output / 1 = Input D3 : Port C High Order I/O Definition 0 = Output / 1 = Input D2 : Group B Mode Definition 0 = Mode 0 / 1 = Mode 1 D1 : Port B I/O Definition 0 = Output / 1 = Input D0 : Port C Low Order I/O Definition 0 = Output / 1 = Input - 69 -

Z80 Microprocessor

Z80
0

8255 PIO
Control Register (83h)

D7 : 0 = Port C bit set & reset D6 D5 D4 : Dont Care D3 D2 D1 : Port C bit selection 0 0 0 = PC0 0 0 1 = PC1 0 1 0 = PC2 0 1 1 = PC3 1 0 0 = PC4 1 0 1 = PC5 1 1 0 = PC6 1 1 1 = PC7 D0 : Bit Set / Reset 0 = Reset / 1 = Set

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Z80 Microprocessor

Z80

8255 PIO
Mode 0 : Basic Input/Output
80h

9Bh

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Z80 Microprocessor

Z80

8255 PIO
Mode 1 : Strobe Input / Output (Unidirectional)
Internal Interrupt Enable Flip/Flop INTEA : 1 when the rising edge of ACKA. INTEB : 1 when the rising edge of STBB.

Port A Output

Port B Input

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Z80 Microprocessor

Z80
STB IBF INTR RD Port B D0~D7

8255 PIO
Mode 1 : Port B Input
Interrupt condition STB = IBF = 1

Mode 1 : Port A Output

WR OBF ACK INTR D0~D7 Port A - 73 Z80 Microprocessor

Interrupt condition

OBF = ACK = 1

Z80
Mode 1 Combination

8255 PIO
Example

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Z80 Microprocessor

Z80

8255 PIO
Port A = Output, Port B = Input

D7 : 1 = Mode & I/O setting D6 D5 : Group A Mode 1 = 0 1 D4 : Port A Output = 0 D3 : Port C High Order I/O Definition ( PC4, PC5 ) 0 = Output / 1 = Input D2 : Group B Mode 1 = 1 D1 : Port B Input = 1 D0 : Port C Low Order I/O Definition ( not used x) - 75 Z80 Microprocessor

Z80

8255 PIO
Mode 2 : Strobe Bidirectional Input/Output

WR
Output

OBF ACK INTR Port A STB

Input

IBF RD

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Z80 Microprocessor

Z80

8255 PIO
Mode 2 : Strobe Bidirectional Input/Output
Port A only : Port A = Mode 2, Port B = Mode 1 Input

D7 : 1 = Mode & I/O setting D6 D5 : Group A Mode 2 = 1 x D4 : Port A Output = x D3 : Port C High Order I/O Definition = x D2 : Group B Mode 1 = 1 D1 : Port B Input = 1 D0 : Port C Low Order I/O Definition = x - 77 Z80 Microprocessor

Z80

8251 SIO
Serial Communication System
DTE DCE DCE DTE

Network

Terminal

Modem

Modem

Terminal

Null Modem

CPU

CPU

SIO

SIO

Network

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Z80 Microprocessor

Z80
SIO

8251 SIO

8250 UART : Universal Asynchronous Receiver / Transmitter 8251 USART : Universal Synchronous-Asynchronous Receiver / Transmitter

Asynchronous Serial Communication

Synchronous (Clock/Data) Serial Communication

Character Oriented Bit Oriented : HDLC (High-level Data Link Control)

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Z80 Microprocessor

Z80
Block Diagram

8251 SIO

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Z80 Microprocessor

Z80
Pin Group

8251 SIO

1. CPU Interface Pin 2. Modem Control Pin 3. Transmit & Transmit Control Pin 4. Receive & Receive Control Pin

CPU Interface Pin

D0 ~ D7, RD, WR, CS, C/D, CLK, RESET

CLK : internal timing clock must be greater that Baud rate clock (RxC/TxC) Asynch x1 & Synch mode : 30 Asynch x16 & Asych x64 mode : 5 C/D : Control = 1, Data = 0 A0

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Z80 Microprocessor

Z80
SIO Port Address

8251 SIO

DTR

Terminal

Modem

DSR RTS CTS

85h 85h 84h 84h

Modem Control Pin

DTR (Data Terminal Ready) / DSR (Data Set Ready) 1. DTR : terminal tells modem ready to send 2. DSR : modem tells terminal ready to transmit RTS (Request To Send) / CTS (Clear To Send) 3. RTS : terminal sets this when ready to send 4. CTS : modem ready to transmit
Carrier modem , CTS=0 - 82 Z80 Microprocessor

Z80

8251 SIO
Transmit/Receive & Transmit/Receive Control Pin
TxD / RxD : Transmit / Receive Data Line TxC / RxC : Data Transfer Rate Clock (Ex.= 9600bps) x1 : 9600bps x 1= 9.6Khz x16 : 9600bps x 16 = 153.6Khz CPU x64 : 9600bps x 64 = 614.4Khz TxRDY / RxRDY : Ready for Transmit/Receive TxRDY INT Can be used as an interrupt to the CPU Can be read as a Status Bit (= Polling) TxRDY pin signal is different from the TxRDY Status Bit. TxRDY [Status Bit] = (Transmit Data Buffer Empty) TxRDY [Pin] = (Transmit Data Buffer Empty) (CTS = 0) (TxEN = 1)

- 83 -

Z80 Microprocessor

Z80

8251 SIO
TxEMPTY : No character to send Can be read as a Status Bit SYDET / BD Asynchronous Mode : BD (Break Detect) Output Output upon the detection of a break character Command Register : SBRK command Synchronous Mode : SYDET (Synch Detect) Input/Output Internal Synchronous : output sync characters are received and synchronized External Synchronous : synch input start receiving data characters. Vcc / GND

- 84 -

Z80 Microprocessor

Z80

8251 SIO
Asynch Transmit Timing

SIO Register : Data Register / Control Register Data Register : Data Input (84h) / Data Output (84h)
- 85 Z80 Microprocessor

Z80
Control Register

8251 SIO
1. Mode instruction (setting of function) 2. Command (setting of operation)

Mode Instruction (85h)

Asynch Synch

Synch

Inhibit

- 86 -

Z80 Microprocessor

Z80

8251 SIO
Command Register (85h)

1 ... Hunt Mode (Synch) 2 Normal Operation

- 87 -

Z80 Microprocessor

Z80
Status Register (85h)

8251 SIO

Different from TxRDY pin Refer to the slide # 83 Same as RxRDY pin Refer to the slide # 84

Asynch Mode Only. Stop bit can not be detected in Synch Mode.

- 88 -

Z80 Microprocessor

Z80

8251 SIO
SIO Program Example
- 2 stop bit - Odd parity - Parity Enable - 8 bit data - x1 baud rate

- Error reset - RxEn - TxEn

- 89 -

Z80 Microprocessor

Z80
Software Timer Hardware Timer

8253 PIT/CTC
Timer (Desired Delay)

Hardware Timer
PIT (Programmable Interval Timer) CTC (Counter Timer Controller)

8253 PIT
Three independent 16-bit counters Six Programmable Counter Modes Binary or BCD counting Max. Clock : 5~10Mhz
- 90 Z80 Microprocessor

Z80
Pin Configuration

8253 PIT
Clock, Gate, Out : Timer pin D0-D7, RD, WR, CS, A0, A1 : CPU Interface pin

- 91 -

Z80 Microprocessor

Z80
PIT Port Address
88h 89h 8Ah 8Bh 88h 89h 8Ah

8253 PIT

Counter 0 Data OUT Counter 1 Data OUT Counter 2 Data OUT Control Register Counter 0 Data IN Counter 1 Data IN Counter 2 Data IN

Control Register (8Bh)

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Z80 Microprocessor

Z80
Control Register

8253 PIT
SC1 SC0 : Counter Selection 0 0 = Counter # 0 0 1 = Counter # 1 1 0 = Counter # 2 1 1 = Invalid RL1 RL0 : Read/Load Format Setting 0 0 = Counter Latch 0 1 = Reading/Loading of Least Significant Byte 1 0 = Reading/Loading of Most Significant Byte 1 1 = Least Significant Byte first, then Most Significant Byte M2 M1 M0 : Mode Selection 0 0 0 = Mode 0 (Interrupt on Terminal Count) 0 0 1 = Mode 1 (Programmable One-Shot) x 1 0 = Mode 2 (Rate Generator) x 1 1 = Mode 3 (Square Wave Generator) 1 0 0 = Mode 4 (Software Triggered Strobe) 1 0 1 = Mode 5 (Hardware Triggered Strobe) BCD : Count Mode Setting 0 = Binary Count (16-bit Binary) 1 = BCD Count (4-decade Binary Coded Decimal)
- 93 Z80 Microprocessor

Z80

8253 PIT
Mode 0 : Interrupt on Terminal Count
OUT pin will be initially low after the mode set operation. OUT pin will remain low, after the count is loaded into the counter register OUT pin will go high and remain high until the counter register is reloaded, when terminal count is reached.

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Z80 Microprocessor

Z80

8253 PIT
Mode 1: Programmable One-Shot

Mode 2 : Rate Generator

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Z80 Microprocessor

Z80

8253 PIT
Mode 3 : Square Wave Generator
Even Number Counter decremented by 2 Odd Number The first clock pulse decrements the count by 1 Subsequent clock pulses decrement the counter by 2 After time out, the output goes low and the full count is reloaded (5) Subsequent clock pulses decrement the counter by 3. Subsequent clock pulses decrement the counter by 2.

- 96 -

Z80 Microprocessor

Z80

8253 PIT
Mode 4 : Software Triggered Strobe

Mode 5 : Hardware Triggered Strobe

- 97 -

Z80 Microprocessor

Z80

8253 PIT
8253 PIT Mode 0 Example
Interrupt on terminal count after 40us Input CLK = 200 Khz = 5 us Counter Register Value = 8
- Counter 0 - LSB first - Mode 0 - Binary

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Z80 Microprocessor