SYSTEM INTERCONNECTION

CHAPTER #
10
Computer Organization & Architecture
Connecting
S H E H E R YAR MALI K

 All the units must be connected

 Different type of connection for different type of unit
 Memory
 Input/Output
 CPU

Chapter # 10 Computer Organization & Architecture 2

Types of Transfers
S H E H E R YAR MALI K

 Interconnection structure must support the following

types of transfers
 Memory to processor
 Processor reads an instruction or a unit of data from memory
 Processor to memory
 Processor writes a unit of data to memory
 I/O to processor
 Processor reads data from an I/O device via an I/O module
 Processor to I/O
 Processor sends data to the I/O device
 I/O to or from memory
 An I/O module is allowed to exchange data directly with memory
without going through the processor using direct memory access
Chapter # 10 Computer Organization & Architecture 3
Computer Modules
S H E H E R YAR MALI K

Chapter # 10 Computer Organization & Architecture 4

Memory Connection
S H E H E R YAR MALI K

 Receives and sends data

 Receives addresses (of locations)
 Receives control signals
 Read
 Write
 Timing

Chapter # 10 Computer Organization & Architecture 5

Input/Output Connection
S H E H E R YAR MALI K

 Similar to memory from computer’s viewpoint

 Output
 Receive data from computer
 Send data to peripheral
 Input
 Receive data from peripheral
 Send data to computer

Chapter # 10 Computer Organization & Architecture 6

Input/Output Connection
S H E H E R YAR MALI K

 Receive control signals from computer

 Send control signals to peripherals
 e.g. spin disk
 Receive addresses from computer
 e.g. port number to identify peripheral
 Send interrupt signals (control)

Chapter # 10 Computer Organization & Architecture 7

CPU Connection
S H E H E R YAR MALI K

 Reads instruction and data

 Writes out data (after processing)
 Sends control signals to other units
 Receives (& acts on) interrupts

Chapter # 10 Computer Organization & Architecture 8

What is a Bus?
S H E H E R YAR MALI K

 A communication pathway connecting two or more

devices
 Usually broadcast
 Signals transmitted by any one device are available for
reception by all other devices attached to the bus
 Often grouped
 A number of channels in one bus
 e.g. 32 bit data bus is 32 separate single bit channels
 Power lines may not be shown

Chapter # 10 Computer Organization & Architecture 9

Buses
S H E H E R YAR MALI K

 There are a number of possible interconnection

systems
 Single and multiple BUS structures are most
common
 e.g. Control/Address/Data bus (PC)
 e.g. Unibus (DEC-PDP)

Chapter # 10 Computer Organization & Architecture 10

Data Bus
S H E H E R YAR MALI K

 Carries data
 Remember that there is no difference between “data” and
“instruction” at this level
 The number of lines determines how many bits can
be transferred at a time
 May consist of 8, 16, 32, 64, 128, or more separate lines
 Width is a key determinant of performance

Chapter # 10 Computer Organization & Architecture 11

Address bus
S H E H E R YAR MALI K

 Identify the source or destination of data

 e.g. CPU needs to read an instruction or data from a given
location in memory
 Bus width determines maximum memory capacity of
system
 e.g. 8080 has 16 bit address bus giving 64k address space
 Also used to address I/O ports
 The higher order bits are used to select a particular
module on the bus and the lower order bits select a
memory location or I/O port within the module

Chapter # 10 Computer Organization & Architecture 12

Control Bus
S H E H E R YAR MALI K

 Used to control the access and the use of the data

and address lines
 Carries control and timing information
 Timing signals indicate the validity of data and address
information
 Command signals specify operations to be performed
 Generally use for
 Memory read/write signal
 Interrupt request
 Clock signals

Chapter # 10 Computer Organization & Architecture 13

Bus Interconnection Scheme
S H E H E R YAR MALI K

Chapter # 10 Computer Organization & Architecture 14

What do Buses Look Like?
S H E H E R YAR MALI K

 Has many shapes

 Parallel lines on circuit boards
 Ribbon cables
 Strip connectors on mother boards
 e.g. PCI
 Sets of wires

Chapter # 10 Computer Organization & Architecture 15

Single Bus Problems
S H E H E R YAR MALI K

 Lots of devices on one bus leads to:

 Propagation delays
 Long data paths mean that co-ordination of bus use can adversely
affect performance
 If aggregate data transfer approaches bus capacity
 Most systems use multiple buses to overcome these
problems

Chapter # 10 Computer Organization & Architecture 16

Traditional Architecture
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Chapter # 10 Computer Organization & Architecture 17

High Performance Bus
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Elements of Bus Design
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 Bus Type  Bus Width

 Dedicated  Address
 Multiplexed  Data
 Method of Arbitration  Data Transfer Type
 Centralized  Read
 Distributed  Write
 Timing  Read-modify-write
 Synchronous  Read-after-write
 Asynchronous  Block

Chapter # 10 Computer Organization & Architecture 19

Bus Types
S H E H E R YAR MALI K

 Dedicated
 Separate data & address lines
 Multiplexed
 Shared lines
 Address valid or data valid control line
 Advantage
 fewer lines
 Disadvantages
 More complex control

Chapter # 10 Computer Organization & Architecture 20

Bus Arbitration
S H E H E R YAR MALI K

 More than one module controlling the bus

 e.g. CPU and DMA controller
 Only one module may control bus at one time
 Arbitration may be centralised or distributed

Chapter # 10 Computer Organization & Architecture 21

Centralised or Distributed Arbitration
S H E H E R YAR MALI K

 Centralised
 Single hardware device controlling bus access
 Bus Controller
 Arbiter
 May be part of CPU or separate
 Distributed
 Each module may claim the bus
 Control logic on all modules

Chapter # 10 Computer Organization & Architecture 22

Timing of Synchronous Bus Operations
S H E H E R YAR MALI K

Chapter # 10 Computer Organization & Architecture 23

Timing of Asynchronous Bus Operations
S H E H E R YAR MALI K

Chapter # 10 Computer Organization & Architecture 24

Point-to-Point Interconnect
S H E H E R YAR MALI K

 In conventional bus
 Over the period of time electrical constraints encountered
with increasing the frequency of wide synchronous buses
 At higher and higher data rates it becomes increasingly
difficult to perform the synchronization and arbitration
functions in a timely fashion
 Shared bus on the same chip magnified the difficulties of
increasing bus data rate and reducing bus latency to keep
up with the processors
 All this became reason for a change in bus
 Point-to-Point Interconnect was introduced
 It has lower latency, higher data rate, and better scalability
Chapter # 10 Computer Organization & Architecture 25
Quick Path Interconnect
S H E H E R YAR MALI K

 QPI is a point-to-point interconnect

 Introduced in 2008
 Multiple direct connections
 Direct pairwise connections to other components eliminating
the need for arbitration found in shared transmission systems
 Layered protocol architecture
 These processor level interconnects use a layered protocol
architecture rather than the simple use of control signals
found in shared bus arrangements
 Packetized data transfer
 Data are sent as a sequence of packets each of which includes
control headers and error control codes
Chapter # 10 Computer Organization & Architecture 26
Multicore Configuration using QPI
S H E H E R YAR MALI K

Chapter # 10 Computer Organization & Architecture 27

QPI Layers
S H E H E R YAR MALI K

 Physical
 Consists of the actual wires carrying the signals
 The unit of transfer at the is 20 bits, which is called a Phit (physical unit)
 Link
 Responsible for reliable transmission and flow control
 The Link layer’s unit of transfer is an 80-bit Flit (flow control unit)
 Routing
 Provides the framework for
directing packets through the fabric
 Protocol
 The high-level set of rules for
exchanging packets of data
between devices. A packet is
comprised of an integral number of
Flits

Chapter # 10 Computer Organization & Architecture 28

Physical Interface of the Intel QPI Interconnect
S H E H E R YAR MALI K

Chapter # 10 Computer Organization & Architecture 29

Physical Interface of the Intel QPI Interconnect
S H E H E R YAR MALI K

 The QPI port consists of 84 individual links

 Each data path consists of a pair of wires referred to as a lane
 It transmits data one bit at a time
 There are 20 data lanes in each
 The 20-bit unit is referred to as a phit
 QPI can transmit in parallel in each direction
 Typical signaling speeds 6.4 GT/s
 At 20 bits per transfer, that adds up
to 16 GB/s
 Being bidirectional, the total
capacity is 32 GB/s
 The lanes are grouped into four
quadrants of 5 lanes each
 In some applications, the link can
also operate at half or quarter
widths

Chapter # 10 Computer Organization & Architecture 30

Peripheral Component Interconnect (PCI)
S H E H E R YAR MALI K

 A popular high bandwidth, processor independent bus that can

function as a mezzanine or peripheral bus
 Delivers better system performance for high speed I/O
subsystems
 PCI Special Interest Group (SIG)
 Created to develop further and maintain the compatibility of the PCI
specifications
 PCI Express (PCIe)
 Point-to-point interconnect scheme intended to replace bus-based
schemes such as PCI
 Key requirement is high capacity to support the needs of higher data
rate I/O devices, such as Gigabit Ethernet
 Another requirement deals with the need to support time dependent
data streams
Chapter # 10 Computer Organization & Architecture 31
PCIe Configuration
S H E H E R YAR MALI K

Chapter # 10 Computer Organization & Architecture 32

PCIe Protocol Layers
S H E H E R YAR MALI K

 Physical
 Consists of the actual wires carrying the signals
 Data link
 responsible for reliable transmission and flow control
 data packets generated/consumed are called Data Link Layer Packets (DLLPs)
 Transaction
 Generates and consumes data
packets used to implement
load/store data transfer
mechanisms
 Also manages the flow control of
those packets between the two
components on a link
 Data packets generated and
consumed by the TL are called
Transaction Layer Packets (TLPs)
Chapter # 10 Computer Organization & Architecture 33