Computer Organization & Architecture

(COA)
GTU # 3140707

UNIT-3
Central Processing Unit

Dr.K.Arun Kumar
 Outline
Looping
• General Register Organization
• Stack Organization
• Instruction format
• Addressing Modes
• Data transfer and manipulation
• Program Control
• Reduced Instruction Set Computer (RISC)
• Complex Instruction Set Computer (CISC)
General Register Organization
Clock Input

R1
R2
R3
R4
R5
R6
R7

Load
(7 lines) SEL MUX - A MUX - B SEL
A B
3x8 A - bus B - bus
decoder

Arithmetic Logic Unit

OPR
SEL (ALU)
D

Output
General Register Organization
 Example: R1 R2 + R3
 To perform the above operation, the control must provide binary selection variables to the
following selector inputs:
1. MUX A selector (SELA): to place the content of R2 into bus A.
2. MUX B selector (SELB): to place the content of R3 into bus B.
3. ALU operation selector (OPR): to provide the arithmetic addition A + B.
4. Decoder destination selector (SELD): to transfer the content of the output bus into R1.

 Control Word:

SELA SELB SELD OPR

General Register Organization
OPR Select Operation Symbol
00000 Transfer A TSFA
Binary
SELA SELB SELD
Code 00001 Increment A INCA
000 Input Input None 00010 A+B ADD
001 R1 R1 R1 00101 A–B SUB
010 R2 R2 R2 00110 Decrement A DECA
011 R3 R3 R3 01000 A and B AND
100 R4 R4 R4 01010 A or B OR
101 R5 R5 R5 01100 A xor B XOR
110 R6 R6 R6 01110 Complement A COMA
111 R7 R7 R7 10000 Shift right A SHRA
11000 Shift left A SHLA
Encoding of Register Selection Fields
Encoding of ALU Operations
Stack Organization
Stack Organization
 A stack is a storage device that stores information in such a manner that the item stored last is
the first item retrieved (LIFO).
 The register that holds the address for the stack is called a stack pointer (SP) because its
value always points at the top item in the stack.
 The physical registers of a stack are always available for reading or writing. It is the content
of the word that is inserted or deleted.
 There are two types of stack organization
1. Register stack – built using registers
2. Memory stack – logical part of memory allocated as stack
Register Stack
 PUSH Operation Address

63
SP ← SP + 1
FULL EMTY
M[SP] ←
DR
IF (SP= 0) then (FULL ←
1)
EMTY ← 0

 POP Operation 4
SP C 3
DR ← M[SP] B 2
SP ← SP - 1 A 1
0
IF (SP= 0) then (EMTY ←
1)
FULL ← 0 DR
Register Stack
 A stack can be placed in a portion of a large memory or it can be organized as a collection of
a finite number of memory words or registers. Figure shows the organization of a 64-word
register stack.
 The stack pointer register SP contains a binary number whose value is equal to the address of
the word that is currently on top of the stack.
 In a 64-word stack, the stack pointer contains 6 bits because 26 = 64.
 Since SP has only six bits, it cannot exceed a number greater than 63 (111111 in binary).
 The one-bit register FULL is set to 1 when the stack is full, and the one-bit register EMTY is
set to 1 when the stack is empty of items.
 DR is the data register that holds the binary data to be written into or read out of the stack.
Memory Stack
 PUSH Operation Address

PC Program 1000
SP ← SP - 1 (instructions)
AR Data 2000
M[SP] ← (operands)
DR 3000
 POP Operation Stack

3997
DR ←
SP 3998
M[SP]
SP ← SP + 1
3999
4000
4001

DR
Memory Stack
 The implementation of a stack in the CPU is done by assigning a portion of memory to a
stack operation and using a processor register as a stack pointer.
 Figure shows a portion of computer memory partitioned into three segments: program, data,
and stack.
 The program counter PC points at the address of the next instruction in the program which is
used during the fetch phase to read an instruction.
 The address registers AR points at an array of data which is used during the execute phase to
read an operand.
 The stack pointer SP points at the top of the stack which is used to push or pop items into or
from the stack.
 We assume that the items in the stack communicate with a data register DR.
Reverse Polish Notation
 The common mathematical method of writing arithmetic expressions imposes difficulties
when evaluated by a computer.
 The Polish mathematician Lukasiewicz showed that arithmetic expressions can be
represented in prefix notation as well as postfix notation.

Infix Prefix or Postfix or Reverse

Polish Polish
A+B + AB AB +

A*B+C* AB * CD * +
D Reverse
Polish
Evaluation of Arithmetic Expression

(3 * 4) + (5 * 6) 34*56*+ 42

4 5 5 30

3 3 12 12 12 12 42

3 4 * 5 6 * +
Instruction format
Instruction Formats
 Instructions are categorized into different formats with respect to the operand fields in the
instructions.
1. Three Address Instructions
2. Two Address Instruction
3. One Address Instruction
4. Zero Address Instruction
5. RISC Instructions
Three Address Instruction
 Computers with three-address instruction formats can use each address field to specify either
a processor register or a memory operand.
 The program in assembly language that evaluates X = (A + B) * (C + D) is shown below.

ADD R1, A, B R1← M[A]+ M[B]

ADD R2, C, D R2← M[C]+ M[D]
MUL X, R1, R2 M[X]← R1 * R2
 The advantage of three-address format is that it results in short programs when evaluating
arithmetic expressions.
 The disadvantage is that the binary-coded instructions require too many bits to specify three
addresses.
Two Address Instruction
 Two address instructions are the most common in commercial computers. Here again each
address field can specify either a processor register or a memory word.
 The program to evaluate X = (A + B) * (C + D) is as follows:

MOV R1, A R1← M[A]

ADD R1, B R1← R1+ M[B]
MOV R2, C R2← M[C]
ADD R2, D R2← R2+ M[D]
MUL R1, R2 R1← R1 * R2
MOV X, R1 M[X]← R1
One Address Instruction
 One address instructions use an implied accumulator (AC) register for all data manipulation.
 For multiplication and division these is a need for a second register.
 However, here we will neglect the second register and assume that the AC contains the result
of all operations.
 The program to evaluate X = (A + B) * (C + D) is

LOAD A AC← M[A]

ADD B AC← AC+M[B]
STORE T M[T]←AC
LOAD C AC← M[C]
ADD D AC← AC+M[D]
MUL T AC← AC*M[T]
STORE X M[X]←AC
Zero Address Instruction
 A stack-organized computer does not use an address field for the instructions ADD and MUL.
 The PUSH and POP instructions, however, need an address field to specify the operand that
communicates with the stack.
 The program to evaluate X = (A + B) * (C + D) will be written for a stack-organized
computer.
 To evaluate arithmetic expressions in a stack computer, it is necessary to convert the
expression into reverse polish notation.
PUSH A TOS← M[A]
PUSH B TOS← M[B]
ADD TOS←(A+B)
PUSH C TOS← M[C]
PUSH D TOS← M[D]
ADD TOS←(C+D)
MUL TOS←(C+D)*(A+B)
POP X M[X] ← TOS
RISC Instruction
 The instruction set of a typical RISC processor is restricted to the use of load and store
instructions when communicating between memory and CPU.
 All other instructions are executed within the registers of the CPU without referring to
memory.
 A program for a RISC type CPU consists of LOAD and STORE instructions that have one
memory and one register address, and computational-type instructions that have three
addresses with all three specifying processor registers.
 The following is a program to evaluate X = (A + B) * (C + D)
LOAD R1, A R1← M[A]
LOAD R2, B R2← M[B]
LOAD R3, C R3← M[C]
LOAD R4, D R4← M[D]
ADD R1, R1, R2 R1← R1+R2
ADD R3, R3, R4 R3← R3+R4
MUL R1, R1, R3 R1← R1*R3
STORE X, R1 M[X] ← R1
Addressing Modes
Addressing Modes
 The addressing mode specifies a rule for 1. Implied Mode
interpreting or modifying the address field of 2. Immediate Mode
the instruction before the operand is 3. Register Mode
referenced. 4. Register Indirect Mode
 Computers use addressing mode techniques 5. Autoincrement or Autodecrement Mode
for the purpose of accommodating one or 6. Direct Address Mode
both of the following provisions: 7. Indirect Address Mode
1. To give programming versatility to the user by
providing such facilities as pointers to memory, 8. Relative Address Mode
counters for loop control, indexing of data, and 9. Indexed Addressing Mode
program relocation. 10. Base Register Addressing Mode
2. To reduce the number of bits in the addressing
field of the instruction.
 There are basic 10 addressing modes
supported by the computer.
1. Implied Mode & 2. Immediate Mode
1. Implied Mode 2. Immediate Mode
 Operands are specified implicitly in the  Operand is specified in the instruction
definition of the instruction. itself.
 For example, the instruction “complement  In other words, an immediate-mode
accumulator (CMA)” is an implied-mode instruction has an operand field rather than
instruction because the operand in the an address field.
accumulator register is implied in the  The operand field contains the actual
definition of the instruction. operand to be used in conjunction with the
 In fact, all register reference instructions operation specified in the instruction.
that use an accumulator and zero address  Immediate mode of instructions is useful
instructions are implied mode instructions. for initializing register to constant value.
 E.g. MOV R1, 05H
instruction copies immediate number 05H
to R1 register.
3. Register Mode & 4. Register Indirect Mode
3. Register Mode 4. Register Indirect Mode
 Operands are in registers that reside within  In this mode the instruction specifies a register
the CPU. in the CPU whose contents give the address of
the operand in memory.
 The particular register is selected from a
 Before using a register indirect mode
register field in the instruction.
instruction, the programmer must ensure that
 E.g. MOV AX, BX the memory address of the operand is placed in
move value from BX to AX register the processor register with a previous
instruction.
 The advantage of this mode is that address field
of the instruction uses fewer bits to select a
register than would have been required to
specify a memory address directly.
 E.g. MOV [R1], R2
value of R2 is moved to the memory location
specified in R1.
5. Auto-increment or Auto-decrement Mode & 6. Direct Address Mode
5. Auto-increment or Auto-decrement 6. Direct Address Mode
Mode  In this mode the effective address is equal
 This is similar to the register indirect mode to the address part of the instruction.
expect that the register is incremented or  The operand resides in memory and its
decremented after (or before) its value is
used to access memory. address is given directly by the address
field of the instruction.
 When the address stored in the register
 E.g. ADD 457
refers to a table of data in memory, it is
necessary to increment or decrement the
register after every access to the table. This
can be achieved by using the increment or
decrement instruction.
7. Indirect Address Mode & 8. Relative Address Mode
7. Indirect Address Mode 8. Relative Address Mode
 In this mode the address field of the  In this mode the content of the program
instruction gives the address where the counter is added to the address part of the
effective address is stored in memory. instruction in order to obtain the effective
 Control fetches the instruction from address.
memory and uses its address part to access  The address part of the instruction is
memory again to read the effective address. usually a signed number which can be
 The effective address in this mode is either positive or negative.
obtained from the following computational:
Effective address = address part of instruction
Effective address = address part of instruction + content of PC
+ content of CPU register
9. Indexed Addressing Mode & 10. Base Register Addressing Mode
9. Indexed Addressing Mode 10. Base Register Addressing Mode
 In this mode the content of an index  In this mode the content of a base register
register is added to the address part of the is added to the address part of the
instruction to obtain the effective address. instruction to obtain the effective address.
 The indexed register is a special CPU  A base register is assumed to hold a base
register that contain an index value. address and the address field of the
 The address field of the instruction defines instruction gives a displacement relative to
the beginning address of a data array in this base address.
memory.  The base register addressing mode is used
 Each operand in the array is stored in in computers to facilitate the relocation of
memory relative to the begging address. programs in memory.
Effective address = address part of instruction Effective address = address part of instruction
+ content of index register + content of base register
Addressing Modes (Example)
Address Memory
200 Load to AC Mode
PC = 200
201 Address = 500
202 Next instruction
R1 = 400

XR = 100 399 450

400 700

AC 800
500

600 900

325
702

300
800
Data transfer and manipulation
Data transfer instructions
 Data transfer instructions move data from one place in the computer to another without
changing the data content.
 The most common transfers are between memory and processor registers, between processor
registers and input or output, and between the processor registers themselves.

Name Mnemonic The data manipulation instructions in a typical

Load LD computer are usually divided into three basic
Store ST types:
Move MOV 1. Arithmetic instructions
Exchange XCH 2. Logical and bit manipulation instructions
Input IN 3. Shift instructions
Output OUT
Push PUSH
Pop POP
Instructions
Arithmetic Instructions Logical & Bit
Manipulation Instructions Shift Instructions
Name Mnemonic Name Mnemonic Name Mnemonic
Increment INC Clear CLR Logical shift right SHR
Decrement DEC Complement COM Logical shift left SHL
Add ADD AND AND Arithmetic shift right SHRA
Subtract SUB OR OR Arithmetic shift left SHLA
Multiply MUL Exclusive-OR XOR Rotate right ROR
Divide DIV Clear carry CLRC Rotate left ROL
Add with carry ADDC Set carry SETC Rotate right through RORC
Subtract with borrow SUBB Complement COMC carry
Negate (2’s NEG carry Rotate left through ROLC
complement) Enable interrupt EI carry
Disable interrupt DI
Program Control
Program Control
 A program control type of instruction, when executed, may change the address value in the
program counter and cause the flow of control to be altered.
 The change in value of the program counter as a result of the execution of a program control
instruction causes a break in the sequence of instruction execution.

Name Mnemonic
Branch BUN
Jump JMP
Skip SKP
Call CALL
Return RET
Compare (by subtraction) CMP
Test (by ANDing) TST
Status Bit Conditions
A B  Bit C (carry) is set to 1 if the end
8 8
carry C8 is 1. It is cleared to 0 if the
𝐶7 carry is 0.
8-bit ALU
𝐶8  Bit S (sign) is set to 1 if the highest-
V Z S C order bit F7 is 1. It is set to 0 if the
𝐹 7 − 𝐹0 bit is 0.
 Bit Z (zero) is set to 1 if the output
𝐹7 is zero and Z = 0 if the output is not
zero.
 Bit V (overflow) is set to 1 if the
Check for zero output exclusive-OR of the last two carries
is equal to 1, and cleared to 0
8
otherwise. This is the condition for
an overflow when negative numbers
Output F are in 2’s complement.
Conditional Branch Instructions
Mnemoni Branch Condition Tested Mnemoni Branch Condition Tested
c Condition c Condition
BZ Branch if zero Z=1 BLO Branch if lower A<B
BNZ Branch if not zero Z=0 BLOE Branch if lower or equal A ≤ B
BC Branch if carry C=1 BE Branch if equal A=B
BNC Branch if no carry C=0 BNE Branch if not equal A≠B
BP Branch if plus S=0 Signed compare conditions (A – B)
BM Branch if minus S=1 BGT Branch if greater than A>B
BV Branch if overflow V=1 BGE Branch if greater or A≥B
BNV Branch if no overflow V=0 equal
Unsigned compare conditions (A – B) BLT Branch if less than A<B
BHI Branch if higher A>B BLE Branch if less or equal A≤B
BHE Branch if higher or A≥B BE Branch if equal A=B
equal BNE Branch if not equal A≠B
Program Interrupt
 The interrupt procedure is, in principle, quite similar to a subroutine call except for three
variations:
1. The interrupt is usually initiated by an internal or external signal rather than from the execution of an
instruction
2. The address of the interrupt service program is determined by the hardware rather than from the address
field of an instruction
3. An interrupt procedure usually stores all the information necessary to define the state of the CPU rather
than storing only the program counter.
 After a program has been interrupted and the service routine been executed, the CPU must return to exactly
the same state that it was when the interrupt occurred. Only if this happens will the interrupted program be
able to resume exactly as if nothing had happened.
 The state of the CPU at the end of the execute cycle (when the interrupt is recognized) is determined from:
1. The content of the program counter
2. The content of all processor registers
3. The content of certain status conditions
Types of interrupts
 There are three major types of interrupts that cause a break in the normal execution of a
program. They can be classified as:
1. External interrupts
2. Internal interrupts
3. Software interrupts
1. External Interrupt
 External interrupts come from
 Input-output (I/O) devices
 Timing device
 Circuit monitoring the power supply
 Any other external source
 Examples that cause external interrupts are
 I/O device requesting transfer of data
 I/O device finished transfer of data
 Elapsed time of an event
 Power failure
 External interrupts are asynchronous.
 External interrupts depend on external conditions that are independent of the program being
executed at the time.
2. Internal interrupts (Traps)
 Internal interrupts arise from
 Illegal or erroneous use of an instruction or data.
 Examples of interrupts caused by internal error conditions like
 Register overflow
 Attempt to divide by zero
 invalid operation code
 stack overflow
 protection violation.
 These error conditions usually occur as a result of a premature termination of the instruction
execution.
 Internal interrupts are synchronous with the program. If the program is rerun, the internal
interrupts will occur in the same place each time.
3. Software interrupts
 A software interrupt is a special call instruction that behaves like an interrupt rather than a
subroutine call.
 The most common use of software interrupt is associated with a supervisor call instruction.
This instruction provides means for switching from a CPU user mode to the supervisor mode.
 When an input or output transfer is required, the supervisor mode is requested by means of a
supervisor call instruction. This instruction causes a software interrupt that stores the old
CPU state and brings in a new PSW that belongs to the supervisor mode.
 The calling program must pass information to the operating system in order to specify the
particular task requested.
Reduced Instruction Set
Computer (RISC)
Overlapped Register Window
 Windows for adjacent procedures have overlapping registers that are shared to provide the
passing of parameters and results.
 Suppose that procedure A calls procedure B.
 Registers R26 through R31 are common to both procedures, and therefore procedure A stores
the parameters for procedure B in these registers.
 Procedure B uses local registers R32 through R41 for local variable storage.
 If procedure B calls procedure C, it will pass the parameters through registers R42 through
R47.
 When procedure B is ready to return at the end of its computation, the program stores results
of the computation in registers R26 through R31 and transfers back to the register window of
procedure A.
 Note that registers R10 through R15 are common to procedures A and D because the four
windows have a circular organization with A being adjacent to D.
Complex Instruction Set
Computer (CISC)
Complex Instruction Set Computer (CISC)
 Characteristics of CISC are as follows:
 A larger number of instructions – typically from 100 to 250 instructions
 Some instructions that perform specialized tasks and are used infrequently
 A large variety of addressing modes – typically from 5 to 20 different modes
 Variable-length instruction formats
 Instructions that manipulate operands in memory
END OF UNIT-III
FIRST HALF