CENTRAL PROCESSING UNIT

UNIT - IV
CONTENT

1. General register organization

2. Stack organization
3. Instruction format
4. Addressing modes
5. Data transfer and manipulation
instructions
6. Program control
7. RISC, and CISC
1. GENERAL REGISTER ORGANIZATION
INTRODUCTION
 The central processing unit is where
all the calculations and logic
operations take place. Register Set

 CPU performs data-processing

operations.
Control Unit
 Main parts of the CPU are:
 Arithmetic Logic Unit (ALU)
 Control Unit (CU) AL
 Registers U
INTRODUCTION

 The registers set stores

intermediate data used during the Register Set
execution of the instructions.
 The ALU performs the required
micro-operations for executing the Control Unit
instructions.
 The Control unit supervises the
transfer of information among the AL
registers and instructs the ALU as to U
which operation to perform.
GENERAL REGISTER ORGANIZATION

 Registers are more convenient and efficient to store pointers,

return addresses, counters, temporary results, etc.
 In Basic Computer, there is only one general-purpose register, the
Accumulator (A), but in modern CPUs, there are many general-
purpose registers.
 It is advantageous to have many registers:
 Transfer between registers within the processor is relatively fast.

 Going “off the processor” to access memory is much slower.

GENERAL REGISTER ORGANIZATION

 When a large number of registers are included in the CPU it is

efficient to connect them through a common system bus.
 Because registers communicate with each other not only for direct
data transfers but also while performing various microoperations.
A BUS ORGANIZATION FOR SEVEN CPU REGISTERS
 The control unit directs the
information flow through ALU by
 Selecting various components in the
system.
 Selecting the Function of ALU.
 Example: R1 ← R2 + R3

1. MUX A selector (SELA): BUS A ← R2.

2. MUX B selector (SELB): BUS B ← R3.
3. ALU operation selector (OPR): ALU to ADD.
4. Decoder destination selector (SELD):
R1←Out Bus
 The entire information is passed through the
Control Word.
CONTROL WORD FORMAT

 The control word is determined

by the sum of the binary
selection inputs.
 It is divided into four sections.
 SELA, SELB, and SELD each have Three bits Three bits
three bits, of SELA of SELB The three The four
choose a choose a bits of bits of OPR
 the OPR field has five bits. source source SELD pick a determine
register for register for target the ALU
the ALU’s A the ALU’s B register. operation
 For a total of 14 bits in the input. input.
control word.
CONTROL WORD FORMAT

ALU operations encoding

OPR Select Operation Symbol
00000 Transfer A TSFA
Register Selection Field 00001 Increment A INCA
Encoding
Bina 00010 Add A + B ADD
SELB
ry SELA SELD
Code Subtract A -
00101 SUB
B
000 Input Input None
Decrement
001 R1 R1 R1 00110 DECA
A
010 R2 R2 R2 01000 ADD A and B AND
011 R3 R3 R3 01010 OR A and B OR
100 R4 R4 R4 01100 XOR A and B XOR
101 R5 R5 R5 Complement
01110 COMA
110 R6 R6 R6 A
MICRO-OPERATIONS AT ALU

Micro- SEL SEL SEL OPR Control Word

operation A B D
R1 ← R2 – R3 R2 R3 R1 SUB 010 011 001 00101

R4 ← R4 ∨ R4 R5 R4 OR 100 101 100 01010

Control Word R5
Format
R6 ← R6 + 1 R6 - R6 INCA 110 000 110 00001

R7 ← R1 R1 - R7 TSFA 001 000 111 00000

Output ← R2 R2 - None TSFA 010 000 000 00000

Output ← Inpu - None TSFA 000 000 000 00000

Input t
R4 ← shl R4 R4 - R4 SHLA 100 000 100 11000

R5 ← 0 R5 R5 R5 XOR 101 101 101 01100

2. STACK ORGANIZATION
STACK ORGANIZATION
 A stack is an ordered linear list in which all
insertions and deletions are made at one end, called
the top.
 It uses the Last In First Out (LIFO)
access method
which is the most popular access method in most of
the CPUs.
 A register is used to store the address of the
topmost element of the stack which is known as a
Stack Pointer(SP) because its value always points
at the top of the stack.
 The main two operations that are performed on the
operands of the stack are:
 Push Operation: The operation of inserting an item
onto a stack is called push operation.
 Pop Operation: The operation of deleting an item onto
a stack is called pop operation.
STACK IN COMPUTER ARCHITECTURE

 There are two types of stack organization that are used in computer
architecture:
 Register stack: It is built using a register.

 Memory stack: It is the logical part of memory allocated as the stack. The
logically partitioned part of RAM is used to implement the stack.
REGISTER STACK ORGANIZATION
 A stack can be organized as a collection of a finite number of
memory words or registers.
 In the figure, there are 64 registers used to make a register
stack. The numbers 0,1,2,3,….. 63 denote the address of
different registers (Binary address representation is 000000 …
111111).
 SP is a pointer that points to the top of the stack i.e. it
currently points to the item at the top (in this figure SP
contains a 6-bit address).
 In a 64-word stack, the stack pointer contains 6 bits because
26=64.
 Since SP has only 6 bits, it cannot exceed a number greater
than 63(111111 in binary). When 63 is incremented by 1 the
result is 0 since 111111+1=1000000, but SP can
accommodate only the six least significant bits → SP points to
the 000000 address register which implies the stack is full.
REGISTER STACK ORGANIZATION

 The two more registers called FULL and EMPTY are

used. These are made up of flip-flops also known as
flags. It indicates whether the stack is full or not.
 If FULL = 1, then EMPTY = 0 → stack is full.

 If FULL= 0, then EMPTY =1 → stack is empty.

 DR is the data register through which data is

transferred to and from the stack.
 Zero address instructions are used in registers stack
organization i.e. the instruction that does not contain
the address of the operands.
REGISTER STACK ORGANIZATION

PUSH Operation POP Operation

For the PUSH operation initially,

SP ← 0
DR ← M[SP] Read from the top
Full ← 0
of the stack
EMTY ← 1
SP← SP-1 Decrement the
stack pointer
SP ← SP+1 Increment stack
pointer If (SP=0) then (EMTY←1) Check if the stack
M[SP] ← DR Write on top of the
is empty
stack
FULL ← 0 Stack is not
If (SP = 63) then (FULL ← 1) Check if the stack is full
full

EMTY← 0 Stack is not empty

MEMORY STACK ORGANIZATION

 A stack may be implemented in a computer's random

access memory (RAM).
 A stack is implemented in the CPU by allocating a portion
of memory to a stack operation and utilizing a processor
register as a stack pointer. The stack pointer is a CPU
register that specifies the stack's initial memory address.
 The RAM is divided into three logical parts:
 Program: The logical part of RAM where programs are stored.

 Data: It is the logical part of the RAM where data(operands) are

stored.
 Stack: It is the part of RAM used to implement stack.
MEMORY STACK ORGANIZATION

PUSH Operation POP Operation

SP ← SP -1 Decrement stack pointer DR ← M[SP] Read from the top

M[SP] ← DR Write on top of the stack
of the stack

SP← SP + 1 Increment the

stack pointer

 The upper limit register and lower limit register are used to check
the stack’s overflow (Full) and underflow (Empty).
 Most computers do not provide hardware to check stack overflow (full
stack) or underflow (empty stack). It must be done in the software
REVERSE POLISH NOTATION

Introduction
 The stack organization is very effective in evaluating the arithmetic expression.

 Computers found difficulties in evaluating common arithmetic mathematical

expressions because they are represented in “Infix notation” (Eg. A+B*C+D).
 The Polish mathematician Lukasiewicz demonstrated that arithmetic expressions
can be represented in prefix or postfix notations.

Types of Notations
 Infix notation (Eg. A+B)
Used by general
register
 Prefix notation or Polish notation (Eg. +AB)
organization
 Postfix notations or Reverse Polish Notation (Eg. Used
AB+) by stack
organization
REVERSE POLISH NOTATION
 Reverse Polish notation (RPN) is a method for conveying mathematical expressions without the
use of separators such as brackets and parentheses.
 In this notation, the operators follow their operands, hence removing the need for the brackets
to define evaluation priority.
 The operation is read from left to right but execution is done every time an operator is reached.

 This notation is suited for computers and calculators since there are fewer characters to
track and fewer operations to execute.
 Reverse Polish notation is also known as postfix notation

Example:
 (A+B)*(C*(D+E)+F)

 RPN is AB+CDE+*F+*
EVALUATION OF ARITHMETIC EXPRESSION

 Let us consider an arithmetic expression: (3*4) + (5*6).

 In Reverse Polish Notation: 34*56*+

Rules
 In RPN, the numbers and operators are listed one after another, and an operator
always acts on the most recent number in the list.
 The numbers can be thought of as forming a stack, and the most recent number
goes on the top of the stack.
 An operator takes the appropriate number of arguments from the top of the stack
and replaces them with the result of the operation.
EVALUATION OF ARITHMETIC EXPRESSION

 Let us consider an arithmetic expression: (3*4) + (5*6).

 In Reverse Polish Notation: 34*56*+

Stack representation
3 4 * 5 6 * +

4 5 5 30

3 3 12 12 12 12 42
PROCESSOR ORGANIZATION

 In general, most processors are organized in one of three ways:

 Single register (Accumulator) organization

 Basic Computer is a good example

 Accumulator is the only general-purpose register

 General register organization

 Used by most modern computer processors

 Any of the registers can be used as the source or destination for computer operations

 Stack organization

 All operations are done using the hardware stack

 For example, an OR instruction will pop the two top elements from the stack, do a logical OR
on them, and push the result on the stack
3. INSTRUCTION FORMAT
INSTRUCTION FORMAT
 In computer architecture, the instruction format is defined as a standard machine
instruction format that can be directly decoded and executed by the central processing
unit ( CPU ).
 The instruction format is simply a sequence of bits ( binary 0 or 1 ) contained in a
machine instruction that defines the layout of the instruction.
 The machine instruction contains the number of bits (patterns of 0 and 1 ). These bits are
grouped together and called fields.
 Each field of the machine instruction provides specific information to the CPU regarding
the operation to be performed and the location of the data.
 An instruction is of various lengths depending upon the number of addresses
it contains. Generally, CPU organizations are of three types on the basis of the number
of address fields:
1. Single Accumulator organization
2. General register organization`
3. Stack organization
CPU ORGANIZATION

1. Single Accumulator Organization

 All the operations on a system are performed with an implied accumulator register.

The instruction format in this type of computer uses one address field.

 For example, the instruction for arithmetic addition is defined by an assembly

language instruction ‘ADD.’ Where X is the operand’s address, the ADD instruction
results in the operation.

AC ← AC + M[X].

 AC is the accumulator register, and M[X] symbolizes the memory word located at

address X.
CPU ORGANIZATION

2. General Register Organization

 The general register type computers employ two or three address fields in their

instruction format. Each address field specifies a processor register or a memory.

 An instruction symbolized by ADD R1, X specifies the operation R1 ← R1 + M [X].

 This instruction has two address fields: register R1 and memory address X.
CPU ORGANIZATION

3. Stack Organization

 A computer with a stack organization has PUSH and POP instructions that require an

address field. Hence, the instruction PUSH X pushes the word at address X to the top
of the stack. The stack pointer updates automatically.

 In stack-organized computers, the operation type instructions don’t require an

address field as the operation is performed on the two items on the top of the
stack.
INSTRUCTION FORMAT REPRESENTATION

 Instruction format is a sequence of bits contained int the machine instruction that
defines the layout of an instruction.
INSTRUCTION FORMAT TYPE

 The set of instructions that manages the operation codes is called the format
of instruction. The design of bits in instruction is supported by the format of
instruction.
 The length of instruction is generally preserved in multiples of character, which is
8 bits. Depending upon the number of addresses, the format of instruction is of
variable length.
 Types of instruction format include:

1. Zero(0) Address Instruction format

2. One(1) Address Instruction format

3. Two(2) Address Instruction format

4. Three(3) Address Instruction format

1. ZERO (0) ADDRESS INSTRUCTION FORMAT
 This instruction does not have an operand field, and
the location of operands is implicitly represented.
 The MODE OPCODE
stack-organized computer system supports
these instructions.
 To evaluate the arithmetic expression, it is required
to convert it into reverse Polish notation. TOS: Top of the Stack
PUSH A TOS ← A
• Example: Consider the below operations, PUSH B TOS ← B
which show how X = (A + B) ∗ (C + D) ADD TOS ← (A + B)
expression will be written for a stack-
organized computer. PUSH C TOS ← C
PUSH D TOS ← D
ADD TOS ← (C + D)
MUL TOS ← (C + D) ∗
(A + B)
2. ONE (1) ADDRESS INSTRUCTION FORMAT
 The instruction format in which the instruction uses only one
address field is called the one address instruction format.
 In this type of instruction format, one operand is in the OPERAN
MODE OPCODE
accumulator and the other is in the memory location D
 It has only one operand

 It has two special instructions LOAD and STORE

 Example: The program to evaluate X = (A + B) ∗ (C LOAD A AC ← M [A]

+ D) is as follows: ADD B AC ← AC + M [B]
STORE T M [T] ← AC
• LOAD: This is used to transfer the data to the
accumulator. LOAD C AC ← M [C]
• STORE: This is used to move the data from the ADD D AC ← AC + M [D]
accumulator to the memory.
• M[ ] is any memory location. MUL T AC ← AC ∗ M [T]
• M[T] addresses a temporary memory location for STORE X M [X] ← AC
3. TWO (2) ADDRESS INSTRUCTION FORMAT
 The instruction format in which the instruction uses only two
address fields is called the two-address instruction format
OPERAN OPERAN
MODE OPCODE
 This type of instruction format is the most commonly used D1 D2
instruction format
 As in one address instruction format, the result is stored in the
accumulator only, but in the two addresses instruction format the
result can be stored in different locations
 This type of instruction format has two operands

 It requires shorter assembly language instructions MOV R1, A R1 ← M [A]

ADD R1, B R1 ← R1 + M [B]
• Example: The program to evaluate X = (A +
B) ∗ (C + D) is as follows: MOV R2, C R2 ← M [C]
ADD R2, D R2 ← R2 + M [D]
• The MOV instruction transfers the
MUL R1, R2 R1 ← R1 ∗ R2
operands to the memory from the
processor registers. R1, R2 registers. MOV X, R1 M [X] ← R1
4. THREE (3) ADDRESS INSTRUCTION FORMAT
 The instruction format in which the instruction uses the three address fields is called the
three-address instruction format.
 The format of a three-address instruction requires three operand fields. These three fields
can be either memory addresses or registers.
 It requires shorter assembly language instructions

OPERAN OPERAN OPERAN

MODE OPCODE
D1 D2 D3

• Example: The program to evaluate X = (A + B) ∗

(C + D) is as follows:
• Two processor registers, R1 and R2. ADD R1 ← M[A] + M
R1, A, B
[B]
• The symbol M [A] denotes the operand at
memory address symbolized by A. The ADD R2 ← M[C] + M
R2, C, D
operand1 and operand2 contain the data or [D]
address that the CPU will operate. Operand 3 MUL X, R1, M [X] ← R1 ∗ R2
contains the result’s address. R2
4. ADDRESSING MODES
ADDRESSING MODES

 The operation field of an instruction specifies the operation to be performed. This operation

will be executed on some data which is stored in computer registers or the main memory.

 Addressing modes define the rules and mechanisms by which the processor

calculates the effective memory address or operand location for data operations.

 The way any operand is selected during the program execution is dependent on the

addressing mode of the instruction. The purpose of using addressing modes is as follows:

1. To give the programming versatility to the user.

2. To reduce the number of bits in addressing the field of instruction.

1 Implied/Implicit
Addressing Modes
2 Immediate Addressing
Modes
3 Register Direct
Addressing Modes
4 Register Indirect
Addressing Modes
5 Auto-Increment
Addressing Modes
6 Auto-Decrement
Types of Addressing Addressing Modes
Modes 7 Direct Addressing Modes
8 Indirect Addressing
Modes
9 Displacement Addressing
Modes
10 Relative Addressing
Modes
11 Indexed Addressing
Modes
12 Base Register
Addressing Modes
13 Stack Addressing Modes
1 Implied/Implicit 1. Implied/Implicit Addressing Modes:
Addressing Modes
2 Immediate Addressing  Address of the operands is specified implicitly in the definition
Modes of the instruction.
3 Register Direct  All registers, reference the instructions that use an accumulator,
Addressing Modes
4 Register Indirect and Zero-address instructions in a stack-organized computer
Addressing Modes are implied addressing mode instructions.
5 Auto-Increment  EA = AC, or EA = Stack[SP]
Addressing Modes Instruction
6 Auto-Decrement
Addressing Modes  Example: CMA, CLA, PUSH, POP, etc. OPCODE
7 Direct Addressing Modes 2. Immediate Addressing Modes
8 Indirect Addressing  The operand is defined in the instruction itself which is used to
Modes
9 Displacement Addressing perform a specified operation.
Modes  Instruction has an operand field instead of an address field.
10 Relative Addressing  Help initialize registers to a constant value.
Modes
11 Indexed Addressing
Modes  Example: ADD 8 will increment the value stored in the
12 Base Register accumulator by 8.
Addressing Modes
Instruction
13 Stack Addressing Modes
OPCODE OPERAND
1 Implied/Implicit
3. Register Direct Addressing Modes:
Addressing Modes  Address specified in the instruction is the register address.
2 Immediate Addressing
 Designated operand need to be in a register.
Modes
3 Register Direct  Shorter address than the memory address. Faster to acquire an
Addressing Modes operand than the memory addressing.
4 Register Indirect  Saving address field in the instruction.
Addressing Modes
 EA = IR(R) (IR(R): Register field of IR)
5 Auto-Increment
Addressing Modes
6 Auto-Decrement  Example: MOV R1, 35H
Addressing Modes
7 Direct Addressing Modes 4. Register Indirect Addressing Modes
8 Indirect Addressing  The instruction defines a register in the CPU that stores the
Modes effective address of the operand in memory.
9 Displacement Addressing  Only one reference to the memory is required to fetch the operand.
Modes
10 Relative Addressing The specified register contains the address of the operand instead
Modes of the operand.
11 Indexed Addressing
Modes  Example: MOV R1, [R2]
12 Base Register
Addressing Modes
13 Stack Addressing Modes
1 Implied/Implicit 5. Auto-Increment Addressing Modes:
Addressing Modes
2 Immediate Addressing  When the address in the register is used to access memory, the
Modes value in the register is incremented by 1 automatically.
3 Register Direct  It follows a post-increment approach.
Addressing Modes  EA = content of the register
4 Register Indirect
Addressing Modes
5 Auto-Increment  Example: EA = 178
Addressing Modes
6 Auto-Decrement
Addressing Modes
7 Direct Addressing Modes

8 Indirect Addressing 6. Auto-Decrement Addressing Modes

Modes  When the address in the register is used to access memory, the
9 Displacement Addressing
Modes value in the register is decremented by 1 automatically
10 Relative Addressing  It follows a pre-decrement approach.
Modes  EA = content of the register
11 Indexed Addressing
Modes
12 Base Register  Example: EA = 399
Addressing Modes
13 Stack Addressing Modes
7. Direct Addressing Modes:
 The effective address of the operand resides in
1 Implied/Implicit
Addressing Modes the address field of the instruction.
2 Immediate Addressing  The operand resides in the memory, and the
Modes address field of the instruction gives its
3 Register Direct
Addressing Modes address.
4 Register Indirect  One references to the memory is required to
Addressing Modes fetch the operand.
5 Auto-Increment  Also known as absolute addressing mode.
Addressing Modes
6 Auto-Decrement
Addressing Modes  Example: ADD, [1000H]
7 Direct Addressing Modes
8. Indirect Addressing Modes
8 Indirect Addressing
Modes  The address field of the instruction gives the
9 Displacement Addressing address of the memory location that contains
Modes the effective address of the operand.
10 Relative Addressing  Two references to the memory are required to
Modes
11 Indexed Addressing fetch the operand
Modes  This addressing mode slows down the
12 Base Register execution as it requires multiple memory
Addressing Modes lookups to find the operand.
13 Stack Addressing Modes
 Example: ADD [[1000H]]
9. Displacement Addressing Modes:
1 Implied/Implicit  The displacement is added to the instruction’s address part to obtain the
Addressing Modes effective address of the operand.
2 Immediate Addressing
Modes
 EA = A + (R) Here, the address field holds two values, A: Base value R:
3 Register Direct displacement value.
Addressing Modes
4 Register Indirect
Addressing Modes
5 Auto-Increment
 Example:
Addressing Modes MOV R1, [Address Field+09H]
6 Auto-Decrement
Addressing Modes
7 Direct Addressing Modes
10. Relative Addressing Modes
8 Indirect Addressing
Modes
 This mode is another version of the displacement address mode. The
9 Displacement Addressing program counter’s content is added to the instruction’s address part to
Modes obtain the effective address.
10 Relative Addressing  EA = A + (PC) Here, EA: Effective address, PC: program counter.
Modes
11 Indexed Addressing
Modes
12 Base Register  Example: MOV R1, [PC + Address Field]
Addressing Modes
13 Stack Addressing Modes  The instruction’s address is usually a signed number.
11. Indexed Addressing Modes:
1 Implied/Implicit  The index register’s content is added to the instruction’s address to
Addressing Modes obtain the effective address.
2 Immediate Addressing
Modes
 EA = content of index register (XI) + Instruction address part
3 Register Direct
Addressing Modes
4 Register Indirect
Addressing Modes
5 Auto-Increment
 Example: MOV R1, [XI + Address Field].
Addressing Modes
6 Auto-Decrement
Addressing Modes
7 Direct Addressing Modes 12. Base Register Addressing Modes
8 Indirect Addressing  This mode is another version of the displacement address mode. To
Modes obtain the effective address, the base register’s content is added to the
9 Displacement Addressing
Modes
instruction’s address.
10 Relative Addressing
 EA = A + (R)
Modes  A: Instruction address,
11 Indexed Addressing  R: Pointer to the base address.
Modes
12 Base Register
Addressing Modes
 Example: MOV R1, [BX + Address Field]
13 Stack Addressing Modes
13. Stack Addressing Modes:
1 Implied/Implicit
Addressing Modes  In this mode, the operand is at the top of the stack.
2 Immediate Addressing
Modes  For example: ADD, this instruction will POP the top two items from the
3 Register Direct
Addressing Modes stack, add them, and will then PUSH the result to the top of the stack.
4 Register Indirect
Addressing Modes  It helps in reducing the number of bits in the instruction's addressing
5 Auto-Increment
Addressing Modes field.
6 Auto-Decrement
Addressing Modes  It facilitates pointers, indexing of data, and counters for loop controls.
7 Direct Addressing Modes

8 Indirect Addressing
Modes
9 Displacement Addressing
Modes
10 Relative Addressing
Modes
11 Indexed Addressing
Modes
12 Base Register
Addressing Modes
13 Stack Addressing Modes
APPLICATIONS OF ADDRESSING MODES

Addressing Mode Applications

Immediate Addressing Mode Initialize the register to a constant value.
Direct Addressing Modes
Helps access static data and implement
Register Direct Addressing
variables.
Mode
Indirect Addressing Modes
Helps implement pointers and pass arrays as
Register Indirect Addressing
parameters.
Mode
Helps in program relocation at runtime. And in
Relative Addressing Mode changing the sequence of instructions during
execution.
Index Addressing Mode Helps in the array and record implementation.
Base Register Addressing Helps in writing relocatable code and handling
Mode recursive procedures.
Auto-Increment Addressing
Mode
Helps implements loops and stacks.
Auto-Decrement Addressing
ADVANTAGES OF ADDRESSING MODES

 They improve performance by efficiently utilizing the CPU cache and

reducing the memory read latency.

 Addressing Modes are used for implementing complex data structures in

memory as they provide mechanisms such as indexing.

 Program sizes can be reduced drastically as the code can be compacted which

allows faster execution of instructions.

 Addressing modes give you the flexibility to use different ways of specifying

the address of operands in your instructions.

EXAMPLE: ADDRESSING MODES

 To show the differences between the various modes, we will

show the effect of the addressing modes on the instruction

defined in Fig.

 The two-word instruction at addresses 200 and 201 is a "load to

AC" instruction with an address field equal to 500.

 The first word of the instruction specifies the operation code

and mode, and the second word specifies the address part.

 PC has the value 200 for fetching this instruction. The content

of processor register R1 is 400, and the content of an index

register or base register XR is 100.

 AC receives the operand after the instruction is executed. The

figure lists a few pertinent addresses and shows the memory

content at each of these addresses.
EXAMPLE: ADDRESSING MODES
Effective Content
Addressing Mode Instruction
Address of AC
Immediate AM MOV A, 500
Register AM MOV A, R1
Register Indirect AM MOV A, [R1]
Auto-Increment AM INR A, [R1]
Auto-Decrement AM DCR A, [R1]
Direct AM MOV A, 500
MOV A,
Indirect AM
[[500]]
Relative AM (EA=PC + MOV A, [PC +
Address Field) Address Field]
Base Register AM
MOV A, [XR +
(EA=XR + Address
Address Field]
Field)
Indexed Register AM
MOV A, [XR +
EXAMPLE: ADDRESSING MODES
Effective Content of
Addressing Mode
Address AC
Immediate AM 201 500
Register AM -- 400
Register Indirect AM 400 700
Auto-Increment AM 400 700
Auto-Decrement AM 399 450
Direct AM 500 800
Indirect AM 800 300
Relative AM (EA=PC +
702 325
Address Field)
Base Register AM
(EA=XR + Address 600 900
Field/)
Indexed Register AM
(EA=XR + Address 600 900
EXAMPLE: ADDRESSING MODES

 Consider a 16-bit processor in which the following contents

appear in main memory, starting at location 200:

 The first part of the first instruction indicates that this

instruction loads a value into an accumulator. The mode field

specifies the addressing mode and, if appropriate a source
register; assume that when used, the source register is R1,
which has a value of 400. There is also a base register that
contains the value 100. The value 500 in location 201 may
be part of the address calculation. Assume that location 399
contains the value 999, location 400 contains a value 1000,
and so on. Determine the effective address and operand to
be loaded for the following address modes: Direct, Indirect,
Immediate, Register Direct, and Register Indirect
EXAMPLE: ADDRESSING MODES
5. DATA TRANSFER AND MANIPULATION
INTRODUCTION

 Opcode: Operation codes are known as

opcodes. The first component of an instruction,
known as an opcode, instructs the computer on
what task to carry out.

 Operand: The second component of an

instruction, known as an operand, instructs the
computer where to locate or store the data or
instructions.
TYPES OF INSTRUCTIONS

 There are certain basic operations included in every computer's

instructions set. The computer instructions are classified into three

categories:

 Data Transfer Instructions

 Data Manipulation Instructions

 Program Control Instructions

DATA TRANSFER INSTRUCTIONS

 Data transfer instructions move data from one

location to another, without changing the binary

information content. They are also called copy
instructions.

 Typically the transfers are between memory

and processor registers, between processor

registers and input and output registers,
and among the processor registers
themselves.
DATA TRANSFER INSTRUCTIONS

 With different Addressing Modes: Eight addressing modes for Load instruction
DATA MANIPULATION INSTRUCTIONS

 Data manipulation instructions are those instructions that manipulate or

change the content of the data/registers/memory.

 It performs operations on data and provides the computational capabilities of

the Computer.

 Data manipulation instructions can be categorized into three parts:

1. Arithmetic instruction

2. Logical and bit manipulation instructions

3. Shift instructions
1. ARITHMETIC INSTRUCTIONS

 Arithmetic instructions
Name Mnemonic
include increment,
Increment INC
decrement, add, subtract,
Decrement DEC
multiply, divide, add with
Add ADD
Carry, subtract with Borrow,
Subtract SUB
and negate that is (2’s) two's
Multiply MUL
complement. If there’s a
Divide DIV
negative number, it is
Add with carry ADDC
considered as negate (so
Subtract with
two's complement). SUBB
borrow
2. LOGICAL AND BIT MANIPULATION INSTRUCTIONS
Name Mnemonic

Clear CLR
 These logical instructions Complement COM
consider each operand bit AND AND
individually and treat it as a
OR OR
Boolean variable.
Exclusive-OR XOR
 Basically, logical instructions help Clear carry CLRC

perform binary operations on Set Carry SETC

strings of bits stored in registers. Complement

COMC
Carry

Enable Interrupt EI

Disable Interrupt DI
3. SHIFT INSTRUCTIONS
 Shift instructions allow the bits of a memory byte or

register to be shifted one-bit place to the right or the Name Mnemonic

left. Logical Shift Right SHR

 There are basically two types of shift instructions — Logical Shift Left SHL

arithmetic and logical. Arithmetic Shift Right SHRA

 Arithmetic shifts consider the contents of the memory Arithmetic Shift Left SHLA
byte or register to be a signed number. So, when the Rotate Right ROR
shift is made, the number is arithmetically divided by
Rotate Left ROL
two (right shift) or multiplied by two (left shift).
Rotate Right through
RORC
 Logical shifts consider the contents of the register or carry
memory byte to be just a bit pattern when the shift is Rotate Left through
ROLC
made. carry
6. PROGRAM CONTROL
PROGRAM CONTROL INSTRUCTIONS

 Program control instructions modify or change the flow of a program.

 It is the instruction that alters the sequence of the program's execution, which means it changes

the value of the program counter, due to which the execution of the program changes.

 Features:

 These instructions cause a change in the sequence of the execution of the instruction.

 This change can be through a condition or sometimes unconditional.

 Flags represent the conditions.

 Flag-Control Instructions.

 Control Flow and the Jump Instructions include jumps, calls, returns, interrupts, and machine control
instructions.

 Subroutine and Subroutine-Handling Instructions.

 Loop and Loop-Handling Instructions.

PROGRAM CONTROL INSTRUCTIONS
PROGRAM CONTROL INSTRUCTIONS
Program Description
Control
Instructions
Branch (BR) Branches are conditional and are used to provide logic to the program and make
it do different things. Branches require several bits in the machine code instruction
for the condition so they have less bits to use for the location of the branch. That's
why branches use a specified offset from the current program counter and can't go
as far as a jump.
Skip (SKP) Skip instructions is used to skip one(next) instruction. It can be conditional or
unconditional. It does not need an address field. In the case of conditional skip
instruction, the combination of conditional skip and an unconditional branch can be
used as a replacement for the conditional branch.
Jump (JMP) The jump instruction transfers the program sequence to the memory address given
in the operand based on the specified flag.
For a larger distance.
Compare The Compare instruction performs a comparison via a subtraction, with difference
(CMP) not retained. CMP compares register sized values, with one exception.
CALL and The CALL and RETURN instructions interrupt the flow of a program by passing
RETURN control to an internal or external subroutine. An external subroutine is another
STATUS BIT CONDITIONS/ FLAG, PROCESSOR STATUS WORD

 To check different conditions for branching instructions like CMP (compare) or TEST

can be used. Certain status bit conditions are set as a result of these operations.
V Z S C

 Status bits mean that the value will be either 0 or 1 as it is a bit. We have four status bits:

 "V" stands for Overflow: based on certain bits, i.e., if extra bits are generated into our operation.

 "Z" stands for Zero: If the output of the ALU(Arithmetic Logic Unit) is 0, then the Z flag is set to 1, otherwise, it is set to 0.

 "S" stands for the Sign bit: If the number is positive, the Sign(S) flag is 0, and if the number is negative, the Sign flag is 1.

 "C" stands for Carry: if the output of the ALU operation generates Carry, then C is set to 1, else C is set to 0.
STATUS BIT CONDITIONS/ FLAG, PROCESSOR STATUS WORD
1. CONDITIONAL BRANCH INSTRUCTIONS

 A conditional branch instruction is basically used

to examine the values that are stored in the

condition code register to examine whether the
specific condition exists and to branch if it does.

 Each conditional branch instruction tests for a

different combination of Status bits for a

condition.
2. SUBROUTINE CALL AND RETURN

 Subroutine is a self-contained sequence of instructions that performs a given computational task.

 It may be called many times at various points in the main program.

 When called, branches to 1st line of the subroutine and at the end, returned to the main program.

 Different names for the instruction that transfers program control to a subroutine

 Call subroutine

 Jump to subroutine

 Branch to a subroutine

 Branch and save the return address

2. SUBROUTINE CALL AND RETURN

 Two Most Important Operations are Implied:

 Branch to the beginning of the Subroutine - Same as the Branch or Conditional Branch.

 Save the Return Address to get the address of the location in the Calling Program upon

exit from the Subroutine

 Locations for storing Return Address

 Fixed Location in the subroutine (Memory)

 Fixed Location in memory

 In a processor Register

 In memory stack - most efficient way

2. SUBROUTINE CALL AND RETURN

 In Memory Stack
3. PROGRAM INTERRUPT

 An interrupt is a signal emitted by a device

attached to a computer or from a program

within the computer.

 An interrupt temporarily stops or terminates a

service or a current process.

 Types of Interrupts:

 External interrupts

 Internal interrupts

 Software interrupts
3. PROGRAM INTERRUPT
3. INTERRUPT PROCEDURE
 Step 1 − First device issues interrupt to CPU.

 Step 2 − Then, the CPU finishes the execution of the current instruction.

 Step 3 − CPU tests for pending interrupt requests. If there is one, it

sends an acknowledgment to the device which removes its interrupt
signal.

 Step 4 − CPU saves program status word onto the control stack.

 Step 5 − CPU loads the location of the interrupt handler into the PC
register.

 Step 6 − Save the contents of all registers from the control stack into
memory.

 Step 7 − Find out the cause of interrupt, or interrupt type, or invokes

the appropriate routine.

 Step 8 − Restore saved registers from the stack.

 Step 9 − Restore the PC to dispatch the original process

7. RISC, AND CISC
REDUCED INSTRUCTION SET COMPUTER PROCESSOR (RISC)

 RISC is a microprocessor architecture that uses a simple set

of instructions that can be substantially modified.

 It is designed to reduce the time it takes for instructions to

execute by optimizing and reducing the number of

instructions. It means that each instruction cycle has only
one clock per cycle, and each cycle consists of three
parameters: fetch, decode, and execute.

 The RISC processor can also combine multiple complex

instructions into a simple one. RISC chips require several

transistors, making them less expensive to develop and
reducing instruction execution time. RISC
Architecture
 Examples of RISC processors are PowerPC, Microchip PIC,

SUN's SPARC, RISC-V.

FEATURES OF RISC PROCESSOR

 RISC processors use one clock per cycle (CPI) to execute each instruction in a

computer. Each CPI also comprises the methods for fetching, decoding, and
executing computer instructions.

 Multiple registers in RISC processors allow them to hold instructions, reply fast to the

computer, and interact with computer memory as little as possible.

 The RISC processors use the pipelining technique to execute multiple parts or stages

of instructions to perform more efficiently.

 RISC has a simple addressing mode and fixed instruction length for the pipeline

execution.

 It uses LOAD and STORE instructions to access the memory location.

COMPLEX INSTRUCTION SET COMPUTER (CISC)

 Intel developed the CISC processor.

 It has an extensive collection of complex instructions that range

from simple to very complex and specializes in the assembly

language level, which takes a long time to execute the instructions.

 CISC approaches reducing the number of instructions on each

program and ignoring the number of cycles per instruction.

 It emphasizes building complex instructions directly in the hardware

because the hardware is always faster than the software.

 CISC chips are relatively slower than RISC chips but use little

instructions. CISC
Architecture
 Examples of CISC processors are AMD, Intel x86, and the
System/360.
FEATURES OF CISC PROCESSOR

 CISC may take longer than a single clock cycle to execute the code.

 The length of the code is short, so it requires minimal RAM.

 It provides more accessible programming in assembly language.

 It focuses on creating instructions on hardware rather than software because they

are faster to develop.

 It comprises fewer registers and more addressing nodes, typically 5 to 20.

DIFFERENCE BETWEEN RISC AND CISC