MOD 3 - Digital Logic Operations
MOD 3 - Digital Logic Operations
FUNDAMENTALS OF
INFORMATION
TECHNOLOGY
MOD 3 - Digital Logic
Operations
Learning Objectives
• Logic Gates
• Combinational Gates
• Boolean Algebra
• Logic Circuit Design
• Truth Tables
LOGIC GATES
- Imply that the computer deals with digital information, i.e., it deals
with the information that is represented by binary digits
- Why BINARY ? instead of Decimal or other number system ?
0 1 2 3 4 5 6 7 8 9
* Consider the calculation cost - Add 0 0 1 2 3 4 5 6 7 8 9
1 1 2 3 4 5 6 7 8 9 10
0 1 2
3
2 3 4 5 6 7 8 9 1011
3 4 5 6 7 8 9 101112
0 0 1 4 4 5 6 7 8 9 10111213
5 5 6 7 8 9 1011121314
1 1 10 6 6 7 8 9 101112131415
7 7 8 9 10111213141516
8 8 9 1011121314151617
9 9 101112131415161718
Logic Gates
BASIC LOGIC BLOCK - GATE -
Binary Binary
Digital Gate Digital
. Output
Input .
. Signal
Signal
- Truth Table
- Boolean Function
- Karnaugh Map
Combinational Gates
• Combinational Logic Circuits are memoryless digital logic circuits whose
output at any instant in time depends only on the combination of its inputs.
• Unlike Sequential Logic Circuits whose outputs are dependant on both their
present inputs and their previous output state giving them some form
of Memory.
• The outputs of Combinational Logic Circuits are only determined by the
logical function of their current input state, logic “0” or logic “1”, at any given
instant in time.
• The result is that combinational logic circuits have no feedback, and any
changes to the signals being applied to their inputs will immediately have an
effect at the output.
• In other words, in a Combinational Logic Circuit, the output is dependant at
all times on the combination of its inputs. Thus a combinational circuit
is memoryless. MOD 3 - Digital Logic Operations 6
• So if one of its inputs condition changes state, from 0-1 or 1-0, so too
will the resulting output as by default combinational logic circuits
have “no memory”, “timing” or “feedback loops” within their design.
BOOLEAN ALGEBRA
Boolean Algebra
Truth Table
- Table that describes the Output Values for all the combinations
of the Input Values, called MINTERMS
- n input variables → 2n minterms
Logic Circuit Design
• In digital electronics, a logic gate is the most elementary component of
a digital circuit or a digital system.
x y z F
0 0 0 0
Truth 0 0 1 1
Table 0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1
Boolean F = x + y’z
Function
x
F
Logic y
Diagram
z
BASIC IDENTITIES OF BOOLEAN ALGEBRA
[1] x + 0 = x [2] x • 0 = 0
[3] x + 1 = 1 [4] x • 1 = x
[5] x + x = x [6] x • x = x
[7] x + x’ = 1 [8] x • X’ = 0
[9] x + y = y + x [10] xy = yx
[11] x + (y + z) = (x + y) + z [12] x(yz) = (xy)z
[13] x(y + z) = xy +xz [14] x + yz = (x + y)(x + z)
[15] (x + y)’ = x’y’ [16] (xy)’ = x’ + y’
[17] (x’)’ = x
[15] and [16] : De Morgan’s Theorem
Usefulness of this Table
- Simplification of the Boolean function
- Derivation of equivalent Boolean functions
to obtain logic diagrams utilizing different logic gates
-- Ordinarily ANDs, ORs, and Inverters
-- But a certain different form of Boolean function may be convenient
to obtain circuits with NANDs or NORs
→ Applications of De Morgans Theorem
Truth Table
Boolean Inputs Output
Logic Function Logic Symbol
Expression A B Y
0 0 0
0 1 0
AND A•B=Y
1 0 0
1 1 1
0 0 0
0 1 1
OR A+B=Y
1 0 1
1 1 1
A=Ā 0 - 1
NOT
• Sample Problem
0 0 PWD
01 1 1 1 0
P W PW P W PW
0D 0 1 1 1
1D 0 1 1 0
_
WhyWhy can’t
can’t you you loop
switch PWthe three
and PW?
adjacent 1s in the top row together?
Karnaugh Maps (K-maps)
PW 11 1 1_
C= W
PW 1 1 1 1PWD
_1 _
_
+ PD
PW 1 0 _
1 PWD
PWD PWD
Simplified Boolean Equation
PW 0 0 Step
PWD
_ 2
PWD
=W
PWD PWD
1 1
1
PW 4
_ _
1
Step
PW 1 1 PWD
__ = PD
PW 1 0 PWD
C = W + PD
Combinational Logic Circuit
C=W
P _ PD
+ PD
D _ PD
D
• Integrated Circuits (ICs)
T T T
T F T
F T T
F F F
A B A⋀B
T T T
T F F
F T F
F F F
T T T
T F T
F T T
F F F
T F
F T
Truth tables really become useful when analyzing more complex Boolean statements.
T T T T
T T F T
T F T T
T F F F
F T T T
F T F T
F F T T
F F F F
T T T T F
T T F T F
T F T T F
T F F F T
F T T T F
F T F T F
F F T T F
F F F F T