Microprocessors and Microcontrollers

(21EC208)
IV Semester ECE
By,
Dr.S.Gandhimathi @ Usha,
Associate Professor/ECE
VCET
Course Objectives

• To study the architecture of 8086 Microprocessor and

assembly language programming fundamentals.

• To develop skills in interfacing of peripheral devices

with 8086 Microprocessor, 8051 Microcontroller and
MSP430 Microcontroller.

• To learn about 8086 Microprocessor and 8051

Microcontrollers.

• To study the architecture of MSP430 Microcontroller.

• To develop microcontroller based systems.

COURSE OUTCOMES

CO1: Explain the architecture of Microprocessors and Understand

Microcontrollers.
CO2: Analyse various types of Interfacing Techniques. Apply

CO3: Write assembly language program for 8086 Apply

Microprocessor, 8051 and MSP430 microcontrollers.
CO4: Learn the architecture of MSP430 Microcontroller. Understand

CO5: Develop ALP for microcontroller based system Apply

design.
CO-PO/PSO MAPPING

PO PO PO PO PO PO PO PO PO PO1 PO1 PO PSO PS

PO
1 2 3 4 5 6 7 8 9 0 1 12 1 O2
CO K-
lev K3 K4 K5 K5 K6 K3 K2 K3 K3 K2 K3 K3 K3 K4
el
CO1 K2 2 1 --- 2 --- --- --- --- 1 1 --- --- 2 ---
CO2 K3 3 2 1 --- --- --- --- --- --- --- --- --- 3 ---
CO3 K3 3 2 1 --- 2 --- --- --- 1 1 --- --- 3 ---
CO4 K2 2 1 --- --- --- --- --- --- --- --- --- --- 2 ---
CO5 K3 3 2 1 --- 2 --- --- --- 1 1 --- --- 3 2

Course
Contrib 2 1 1 --- 1 --- --- --- 1 1 --- --- 2 1
ution
21EC208/ Microprocessors and Microcontrollers
UNIT I ARCHITECTURE OF 8086 & ASSEMBLY LANGUAGE PROGRAMMING
Microprocessor Families – 8086 –Architecture – Instruction set – Addressing Modes –
Bus Cycles – Assembly Language Programming of 8086 – Assembler Directives – Interrupts
and its applications.

UNIT II PERIPHERAL INTERFACING

External Memory Interface – Programmable Peripheral Interface (8255) – Serial
Communication Interface (8251) –Keyboard and Display Interface (8279) – Programmable
Timer Controller (8253/8254) – Programmable interrupt controller (8259).

UNIT III 8051 MICROCONTROLLER

8051 Microcontroller – Instruction Set – Assembly Language Programming – I/ O
Interfacing – 8051 Timers –USART – Interrupts – 8051 Programming in C .

UNIT IV MSP430 MICROCONTROLLER

Architecture Introduction - Embedded C Programming in MSP430 - GPIO Pins &
Configuration - Timers, Capture & PWM – DAC – ADC Ports - I 2C.

UNIT V SYSTEM DESIGN USING MICROCONTROLLERS

ADC & DAC Interfacing – Sensor Interfacing – RTC Interfacing (DS1307) using I 2C
Standard – Relay, Motor Control – DC & Stepper Motor – System Design: Traffic Light
Controller & Digital Weighing Machine.
TEXT BOOK(S):
• Douglas V Hall, “Microprocessors and Interfacing”, 3rd Edition, McGraw
Hill Education, 2012.
• Muhammad Ali Mazidi, “The 8051 Microcontroller and Embedded Systems
using Assembly and C”, 2nd Edition, Pearson India, 2007.
• John H. Davies, "MSP430 Microcontroller Basics", 2nd Edition,
Newnes,2008.

REFERENCES:
• V. A.K. Ray and K.M. Burchandi, “Intel Microprocessors Architecture
Programming and Interfacing”, McGraw Hill, 2000.
• Sunil Mathur, "Microprocessor 8086: Architecture, Programming and
Interfacing", PHI Learning Pvt.Ltd., 2011.
• Kenneth Ayala, "The 8051 Microcontroller”, 3rd Edition, Delmar Cengage
Learning, 2004.
Block Diagram of a Microcomputer
Introduction

• A microprocessor consists of an ALU, control unit

and register array.

• ALU performs arithmetic and logical operations on

the data received from an input device or memory.

• Control unit controls the instructions and flow of

data within the computer.

• Register array consists of registers identified by

letters like B, C, D, E, H, L and accumulator.
Introduction
Computer's Central Processing Unit (CPU) built on
a single Integrated Circuit (IC) is called
a microprocessor.

It is a programmable, multipurpose, clock-driven,

register-based electronic device that reads binary
instructions from a storage device called memory,
accepts binary data as input and processes data
according to those instructions and provides results
as output.

It contains millions of tiny components like

transistors, registers, and diodes that work together.
Working of Microprocessor
• The microprocessor follows a sequence to execute the
instruction: Fetch, Decode, and then Execute.

• Initially, the instructions are stored in the storage memory

of the computer in sequential order.

• The microprocessor fetches those instructions from the

stored area (memory), then decodes it and executes those
instructions till STOP instruction is met.

• Then, it sends the result in binary form to the output port.

• Between these processes, the register stores the temporary

data and ALU (Arithmetic and Logic Unit) performs the
computing functions.
Microprocessor Applications

• Household Devices
• Industrial Applications
• Transportation Industry
• Computers and Electronics
• In Medicals
• Instrumentation
• Entertainment
• Communication
Case Study: Intel
Slide 2
Processors
Generation of Fifth Generation
Pentium

Microprocess Fourth Generation

ors During 1980s
Low power version of HMOS technology
(HCMOS)
Third Generation 32 bit processors
During 1978 Physical memory space 224 bytes = 16 Mb
HMOS technology  Faster speed, Higher Virtual memory space 240 bytes = 1 Tb
packing density Floating point hardware
16 bit processors  40/ 48/ 64 pins Supports increased number of addressing
Easier to program modes
Dynamically relatable programs
Processor has multiply/ divide arithmetic Intel 80386
hardware
More powerful interrupt handling
capabiliti Second Generation
es During 1973
Flexible NMOS technology  Faster speed, Higher
I/O port addressing density, Compatible with TTL
4 / 8/ 16 bit processors  40 pins
Intel Ability to address large memory spaces
8086 (16 bit processor) and I/O ports
Greater number of levels of subroutine
First nesting
Generation Better interrupt handling capabilities
Between 1971 – 1973
PMOS technology, non compatible with TTL Intel 8085 (8 bit processor)
8086 Microprocessor
Introduction:
• INTEL 8086 is a 16 bit Microprocessor
• Implemented in N-channel HMOS technology
• 40 pin dual in-line package

Features:
• 16 bit Microprocessor
• 16 bit data bus
• 20 address lines – 1MB memory
• It has 16 bit I/O address. Able to access 65,536 I/O ports.
• It has fourteen 16 bit registers
• It has multiplexed address & data bus
• It is designed to operate in 1. Min mode 2. Max mode
• It supports multiprogramming
• It has powerful instruction set
• It fetches up to 6 instruction bytes from memory- high speed
8086
Microprocessor Pins and Common signals
Signals
AD0-AD15 (Bidirectional)

Address/Data bus

Low order address bus; these are

multiplexed with data.

When AD lines are used to

transmit memory address the symbol
A is used instead of AD, for example A0-
A15.

When data are transmitted over AD

lines the symbol D is used in place of
AD, for example D0-D7, D8-D15 or D0-D15.

A16/S3, A17/S4, A18/S5, A19/S6

High order address bus. These

are multiplexed with status signals
8086 MICROPROCESSOR ARCHITECTURE
Bus Interface Unit (BIU)
• The BIU fetches instructions, reads data from memory and
ports, and writes data to memory and I/O ports.
• It has Segment registers , Instruction pointer and Instruction
queue.
•
Execution Unit (EU)
EU receives program instruction codes and data from the BIU,
executes these instructions and stores the results either in the
general registers or output them through the BIU.

It contains
ALU
• General purpose registers
• Index registers
• Pointers
• Flag register
Register organization of 8086:

All the registers of 8086 are 16-bit registers.

The general purpose registers, can be used either 8-bit registers or 16-bit registers
used for
• holding the data and variables
• intermediate results temporarily.

The special purpose registers are used as segment registers, pointers, index
registers or as offset storage registers for particular addressing modes.

AX Register (Accumulator):
• consists of two 8-bit registers AL and AH, which can be combined together and
used as a 16- bit register AX.
• AL - low-order byte of the word ,AH - high-order byte.
• can be used for I/O operations, rotate and string manipulation.
BX Register:
• This register is mainly used as a base register.
• It holds the starting base location of a memory
region within the data segment.

CX Register:
It is used as default counter - count register in case of
string and loop instructions.

DX Register:
• used as a port number in I/O operations.
• In integer 32-bit multiply and divide instruction the
DX register contains high-order word of the initial or
resulting number.
Memory segmentation
8086
Microprocessor Addressing Modes : Memory
Access
20 Address lines  8086 can address up to
220 = 1M bytes of memory

However, the largest register is only 16 bits

Physical Address will have to be calculated

Physical Address : Actual address of a byte in
memory. i.e. the value which goes out onto
the address bus.

Memory Address represented in the form –

Seg : Offset (Eg - 89AB:F012)

Each time the processor wants to access

memory, it takes the contents of a segment
register, shifts it one hexadecimal place to the
16 bytes of
left (same as multiplying by 1610), then add the contiguous memory
required offset to form the 20- bit address

89AB : F012  89AB  89AB0 (Paragraph to byte  89AB x 10 = 89AB0)

F012  0F012 (Offset is already in byte
unit)
+ -------
98AC2 (The absolute 44
address)
Generation of Physical Address

• Offset is the displacement of the memory location

from the starting location of the segment. The
8086 addresses a segmented memory.
• The complete physical address which is 20-bits
long is generated using segment and offset
registers each of the size 16-bit
Segment Registers:
• Code segment (CS) -The CS register is automatically updated
during FAR JUMP, FAR CALL and FAR RET instructions.

• Stack segment (SS) -SS register can be changed directly using POP
instruction.

• Data segment (DS) -DS register can be changed directly using POP
and LDS instructions.

• Extra segment (ES)-ES register can be changed directly using POP

and LES instructions.
INSTRUCTION POINTER (IP):
It is a 16-bit register. The operation is same as the program
counter.
The IP register is updated by the BIU to point to the address of the
next instruction.

INSTRUCTION QUEUE:
The instruction queue is a First-In-First-out (FIFO) group of
registers where 6 bytes of instruction code is pre-fetched from
memory ahead of time.
It is being done to speed-up program execution by overlapping
instruction fetch and execution- PIPELINING.

CONTROL UNIT:
The control unit in the EU directs the internal operations like RD ,
WR and M/IO operations
ALU:
It is a 16 bit register. It can add, subtract, increment, decrement,
complement, shift numbers and performs AND, OR, XOR operations.
POINTER REGISTERS
Stack Pointer (SP)-16-bit register pointing to program stack.

Base Pointer (BP) - 16-bit register pointing to data in the stack

segment.
- used for based, based indexed or register indirect addressing.

Index Registers
 Source Index (SI)
- 16-bit register.
- used for indexed, based indexed and register indirect
addressing, as well as a source data address in string manipulation
instructions.

 Destination Index (DI)

- 16-bit register.
- used for indexed, based indexed and register indirect
addressing, as well as a destination data address in string
manipulation instructions
FLAG REGISTER

Six status flags - OF, SF, ZF, AF, PF, CF

Three control flags - TF, DF, IF

Conditional Flags:

1.Carry Flag (CY):

- indicates an overflow condition for unsigned integer arithmetic.

2. Auxiliary Flag (AC):

-Sets when ALU generates a carry/barrow between operations from
lower nibble (i.e. D0 – D3) to upper nibble (i.e. D4 – D7).

3.Parity Flag (PF):

-used to indicate the parity of result.
-result contains even number of 1’s-flag is set
odd number of 1’s-flag is reset.

4.Zero Flag (ZF): set if the result of arithmetic or logical operation is

zero else it is reset.

5.Sign Flag (SF):

In sign magnitude format the sign of number is indicated by MSB
bit. If the result of operation is negative, sign flag is set.

6. Overflow flag(OF):
Set if the result is too large positive number or is too small
negative number to fit into destination operand.
II. Control Flags

Control flags are set or reset deliberately to control the operations of the
execution unit.
1. Trap Flag (TF):
• It is used for single step control. It allows user to execute one
instruction of a program at a time for debugging.
• When trap flag is set, program can be run in single step mode.

2. Interrupt Flag (IF):

• It is an interrupt enable/disable flag.
• If it is set, the maskable interrupt of 8086 is enabled and if it is reset,
the interrupt is disabled.
• It can be set by executing instruction SIT and can be cleared by
executing CLI instruction.

3. Direction Flag (DF):

• It is used in string operation.
• If it is set, string bytes are accessed from higher memory address to
lower memory address.
• When it is reset, the string bytes are accessed from lower memory
address to higher memory address.
8086
Microprocessor Introduction

Program
A set of instructions written to solve
a problem.

Instruction
Directions given by the user to a
microprocessorto execute a task

Computer language

High Level Low Level

Machine Assembly Language

Language
⯀ Binary bits ⯀ English
Alphabets
⯀ ‘Mnemonics’
⯀ Mnemonics
Assembler Machine
37
Language
ADDRESSING
MODES
8086
Microprocessor Addressing
Modes
Every instruction of a program has to operate on a data.
The different ways in which a source operand is denoted
in an instruction are known as addressing modes.

1. Register
Addressing
Group I : Addressing modes for
2. Immediate Addressing register and immediate data

3. Direct Addressing

4. Register Indirect Addressing

5. Based Addressing
Group II : Addressing modes for
6. Indexed Addressing memory data
7. Based Index Addressing

8. String Addressing

9. Direct I/O port Addressing

Group III : Addressing modes for
10. Indirect I/O port Addressing I/O ports

11. Relative Addressing Group IV : Relative Addressing mode

12. Implied Addressing Group V : Implied Addressing m4o0de

8086 Group I : Addressing modes for
Microprocessor Addressing register and immediate
Modes data

1. Register The instruction will specify the name of

Addressing the register which holds the data to be
2. Immediate Addressing operated by the instruction.
3. Direct Addressing Example:
4. Register Indirect Addressing
MOV CL,
5. Based Addressing DH
The content of 8-bit register DH is moved
6. Indexed Addressing to another 8-bit register CL

7. Based Index Addressing (CL)  (DH)

8. String Addressing

9. Direct I/O port Addressing

10. Indirect I/O port Addressing

11. Relative Addressing

12. Implied Addressing

8086 Group I : Addressing modes for
Microprocessor Addressing register and immediate
Modes data

1. Register
Addressing In immediate addressing mode, an 8-bit or 16-bit
2. Immediate Addressing data is specified as part of the instruction
3. Direct Addressing
Example:
4. Register Indirect Addressing
MOV DL, 08H
5. Based Addressing
The 8-bit data (08H) given in the instruction is
6. Indexed Addressing moved to DL

7. Based Index Addressing (DL)  08H

8. String
Addressing MOV AX, 0A9FH
9. Direct I/O port Addressing
The 16-bit data (0A9FH) given in the instruction is
10. Indirect I/O port Addressing
moved to AX register
11. Relative Addressing
(AX)  0A9FH
12. Implied Addressing

42
8086 Group II : Addressing modes
Microprocessor Addressing for memory data
Modes
1. Register Addressing

2. Immediate Addressing
Here, the effective address of the
3. Direct Addressing
memory location at which the data operand is
4. Register Indirect Addressing stored is given in the instruction.

5. Based Addressing The effective address is just a 16-bit number

written directly in the instruction.
6. Indexed Addressing
Example:
7. Based Index Addressing
MOV BX, [1354H]
8. String MOV BL, [0400H]
Addressing
9. Direct I/O port Addressing
The square brackets around the 1354H denotes
10. Indirect I/O port Addressing the contents of the memory location.
When executed, this instruction will copy the
11. Relative Addressing contents of the memory location into BX register.

12. Implied Addressing This addressing mode is called direct because

the displacement of the operand from the
segment base is specified directly in the
instruction.

46
Group II : Addressing modes
8086 Addressing Modes
Microprocessor for memory data

1. Register In Register indirect addressing, name of

Addressing the register which holds the effective address
2. Immediate Addressing (EA) will be specified in the instruction.

3. Direct Addressing Registers used to hold EA are any of the

following registers:
4. Register Indirect Addressing
BX, BP, DI and SI.
5. Based Addressing
Content of the DS register is used for
6. Indexed Addressing
address calculation. base
7. Based Index Addressing
Example:
Note : Register/ memory
8. String Addressing enclosed in brackets refer
MOV CX, [BX]
to content of register/
9. Direct I/O port Addressing memory
Operations:
10. Indirect I/O port Addressing
EA = (BX)
11. Relative Addressing BA = (DS) x 1610
MA = BA + EA
12. Implied Addressing
(CX)  (MA)
or,

(CL)  (MA)
(CH)  (MA +1) 47
8086 Group II : Addressing modes
Microprocessor Addressing for memory data
Modes
1. Register In Based Addressing, BX or BP is used to hold
Addressing base value for effective addressthe
and a signed 8-
2. Immediate Addressing bit
or unsigned 16-bit displacement will be specified
in the instruction.
3. Direct Addressing
In case of 8-bit displacement, it is sign extended
4. Register Indirect Addressing to 16-bit before adding to the base value.

5. Based Addressing When BX holds the base value of EA, 20-bit

physical address is calculated from BX and DS.
6. Indexed Addressing
When BP holds the base value of EA, BP and SS
7. Based Index Addressing
is
8. String Addressing used.
Example:
9. Direct I/O port Addressing
MOV AX, [BX + 08H]
10. Indirect I/O port Addressing
Operations:
11. Relative Addressing
0008H  08H (Sign extended)
12. Implied Addressing EA = (BX) + 0008H
BA = (DS) x 1610
MA = BA + EA

(AX)  (MA) or,

(AL)  (MA)
48
(AH)  (MA + 1)
8086 Group II : Addressing modes
Microprocessor Addressing for memory data
Modes
1. Register SI or DI register is used to hold an index value for
Addressing memory data and a signed 8-bit or unsigned 16-
2. Immediate Addressing bit displacement will be specified in
the instruction.
3. Direct Addressing
Displacement is added to the index value in SI or
4. Register Indirect Addressing DI register to obtain the EA.

5. Based Addressing In case of 8-bit displacement, it is sign extended

to 16-bit before adding to the base value.
6. Indexed Addressing

7. Based Index Addressing

Example:
8. String
Addressing MOV CX, [SI + 0A2H]
9. Direct I/O port Addressing
Operations:
10. Indirect I/O port Addressing

11. Relative Addressing

EA = (SI) + A2H BA
12. Implied Addressing = (DS) x 1610 MA =
BA + EA

(CX)  (MA) or,

(CL)  (MA)
(CH)  (MA + 1)
49
8086 Group II : Addressing modes
Microprocessor Addressing for memory data
Modes
1. Register In Based Index Addressing, the effective address
Addressing is computed from the sum of a base register
2. Immediate Addressing (BX or BP), an index register (SI or DI)
and a displacement.
3. Direct Addressing
Example:
4. Register Indirect Addressing
MOV DX, [BX + SI + 0AH]
5. Based Addressing
Operations:
6. Indexed Addressing
000AH  0AH (Sign extended)
7. Based Index Addressing

8. String EA = (BX) + (SI) + 000AH

Addressing BA = (DS) x 1610
9. Direct I/O port Addressing MA = BA + EA

10. Indirect I/O port Addressing (DX)  (MA) or,

11. Relative Addressing (DL)  (MA)

(DH)  (MA + 1)
12. Implied Addressing

50
8086 Group II : Addressing modes
Microprocessor Addressing for memory data
Modes
1. Register Employed in string operations to operate on
Addressing string data.
2. Immediate Addressing
The effective address (EA) of source data is
3. Direct Addressing stored in SI register and the EA of destination is
stored in DI register.
4. Register Indirect Addressing
Segment register for calculating base address of
5. Based Addressing source data is DS and that of the destination
data is ES
6. Indexed Addressing

7. Based Index Addressing

Example: MOVS BYTE
8. String Addressing
Operations:
9. Direct I/O port Addressing
Calculation of source memory location:
10. Indirect I/O port Addressing EA = (SI) BA = (DS) x 1610 MA = BA + EA

11. Relative Addressing Calculation of destination memory location:

EAE = (DI) BAE = (ES) x 1610 MAE = BAE + EAE
12. Implied Addressing

Note : Effective address of (MAE)  (MA)

the Extra segment register
If DF = 1, then (SI)  (SI) – 1 and (DI) = (DI) - 1 If
DF = 0, then (SI)  (SI) +1 and (DI) = (DI)51+ 1
8086 Group III : Addressing
Microprocessor Addressing modes for I/O ports
Modes
1. Register These addressing modes are used to access
Addressing data from standard I/O mapped devices or ports.
2. Immediate Addressing
In direct port addressing mode, an 8-bit port
3. Direct Addressing address is directly specified in the instruction.

4. Register Indirect Addressing Example: IN AL, [09H]

5. Based Addressing Operations: PORTaddr = 09H

(AL)  (PORT)
6. Indexed Addressing
Content of port with address 09H is
7. Based Index Addressing
moved to AL register
8. String Addressing
In indirect port addressing mode, the instruction
9. Direct I/O port Addressing will specify the name of the register which
holds the port address. In 8086, the 16-bit port
10. Indirect I/O port Addressing address is stored in the DX register.

11. Relative Addressing Example: OUT [DX], AX

12. Implied Addressing Operations: PORTaddr = (DX)

(PORT)  (AX)

Content of AX is moved to port

whose address is specified
by DX register. 52
8086 Group IV : Relative
Microprocessor Addressing Addressing
Modes mode

1. Register Addressing

2. Immediate Addressing

3. Direct Addressing In this addressing mode, the effective address

of a program instruction is specified relative
4. Register Indirect Addressing to Instruction Pointer (IP) by an 8-bit
signed displacement.
5. Based Addressing
Example: JZ 0AH
6. Indexed Addressing
Operations:
7. Based Index Addressing

8. String 000AH  0AH (sign extend)

Addressing
9. Direct I/O port Addressing If ZF = 1, then

10. Indirect I/O port Addressing EA = (IP) + 000AH

BA = (CS) x 1610
11. Relative Addressing MA = BA + EA
12. Implied Addressing If ZF = 1, then the program control jumps to
new address calculated above.

If ZF = 0, then next instruction of

the program is executed.
53
8086 Group IV : Implied
Microprocessor Addressing Addressing
Modes mode

1. Register Addressing

2. Immediate Addressing

3. Direct Addressing

4. Register Indirect Addressing

5. Based Addressing

6. Indexed Addressing
Instructions using this mode have no operands.
The instruction itself will specify the data to
7. Based Index Addressing
be operated by the instruction.
8. String
Addressing Example: CLC
9. Direct I/O port Addressing
This clears the carry flag to
10. Indirect I/O port Addressing zero.

11. Relative Addressing

12. Implied Addressing

54
INSTRUCTION
SET
8086
Microprocessor Instruction Set

8086 supports 6 types of instructions.

1. Data Transfer Instructions

2. Arithmetic Instructions

3. Logical Instructions

4. String manipulation Instructions

5. Process Control Instructions

6. Control Transfer Instructions

56
8086
Microprocessor Instruction Set

1. Data Transfer Instructions

Instructions that are used to transfer data/ address in to

registers, memory locations and I/O ports.

Generally involve two operands: Source operand and

Destination operand of the same size.

Source: Register or a memory location or an immediate

data Destination : Register or a memory location.

The size should be a either a byte or a word.

A 8-bit data can only be moved to 8-bit register/ memory

and a 16-bit data can be moved to 16-bit register/ memory.

57
8086
Microprocessor Instruction Set

1. Data Transfer Instructions

Mnemonics: MOV, XCHG, PUSH, POP, IN, OUT …

MOV reg2/ mem, reg1/ mem

MOV reg2, reg1 (reg2)  (reg1)

MOV mem, reg1 (mem)  (reg1)
MOV reg2, (reg2)  (mem)
mem
MOV reg/ mem, data

MOV reg, data (reg)  data

MOV mem, data (mem)  data

XCHG reg2/ mem, reg1

XCHG reg2, reg1 (reg2)  (reg1)

XCHG mem, reg1 (mem)  (reg1)

58
8086
Microprocessor Instruction Set

1. Data Transfer Instructions

Mnemonics: MOV, XCHG, PUSH, POP, IN, OUT …

PUSH reg16/ mem

PUSH reg16 (SP)  (SP) – 2

MA S = (SS) x 1610 + SP
(MA S ; MA S + 1)  (reg16)

PUSH mem (SP)  (SP) – 2

MA S = (SS) x 1610 + SP
(MA S ; MA S + 1)  (mem)

POP reg16/ mem

POP reg16 MA S = (SS) x 1610 + SP

(reg16)  (MA S ; MA S + 1)
(SP)  (SP) + 2

POP mem MA S = (SS) x 1610 + SP

(mem)  (MA S ; MA S + 1)
(SP)  (SP) + 2
59
8086
Microprocessor Instruction Set

1. Data Transfer Instructions

Mnemonics: MOV, XCHG, PUSH, POP, IN, OUT …

IN A, [DX] OUT [DX], A

IN AL, [DX] PORTaddr = (DX) OUT [DX], AL PORTaddr = (DX)

(AL)  (PORT) (PORT)  (AL)

IN AX, [DX] PORTaddr = (DX) OUT [DX], AX PORTaddr = (DX)

(AX)  (PORT) (PORT)  (AX)

IN A, addr8 OUT addr8, A

IN AL, addr8 (AL)  (addr8) OUT addr8, AL (addr8)  (AL)

IN AX, addr8 (AX)  (addr8) OUT addr8, (addr8)  (AX)

AX

60
8086
Microprocessor Instruction Set

2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

ADD reg2/ mem, reg1/mem

ADC reg2, reg1 (reg2)  (reg1) + (reg2)

ADC reg2, mem (reg2)  (reg2) + (mem)
ADC mem, reg1 (mem)  (mem)+(reg1)

ADD reg/mem, data

ADD reg, data (reg)  (reg)+ data

ADD mem, data (mem)  (mem)+data

ADD A, data

ADD AL, data8 (AL)  (AL) + data8

ADD AX, data16 (AX)  (AX) +data16

61
8086
Microprocessor Instruction Set

2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

ADC reg2/ mem, reg1/mem

ADC reg2, reg1 (reg2)  (reg1) + (reg2)+CF

ADC reg2, mem (reg2)  (reg2) + (mem)+CF
ADC mem, reg1 (mem)  (mem)+(reg1)+CF

ADC reg/mem, data

ADC reg, data (reg)  (reg)+ data+CF

ADC mem, data (mem)  (mem)+data+CF

ADDC A, data

ADD AL, data8 (AL)  (AL) + data8+CF

ADD AX, data16 (AX)  (AX) +data16+CF

62
8086
Microprocessor Instruction Set

2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

SUB reg2/ mem, reg1/mem

SUB reg2, reg1 (reg2)  (reg1) - (reg2)

SUB reg2, mem (reg2)  (reg2) - (mem)
SUB mem, reg1 (mem)  (mem) - (reg1)

SUB reg/mem, data

SUB reg, data (reg)  (reg) - data

SUB mem, data (mem)  (mem) - data

SUB A, data

SUB AL, data8 (AL)  (AL) - data8

SUB AX, data16 (AX)  (AX) - data16

63
8086
Microprocessor Instruction Set

2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

SBB reg2/ mem, reg1/mem

SBB reg2, reg1 (reg2)  (reg1) - (reg2) - CF

SBB reg2, mem (reg2)  (reg2) - (mem)- CF
SBB mem, reg1 (mem)  (mem) - (reg1) –CF

SBB reg/mem, data

SBB reg, data (reg)  (reg) – data - CF

SBB mem, data (mem)  (mem) - data - CF

SBB A, data

SBB AL, data8 (AL)  (AL) - data8 - CF

SBB AX, data16 (AX)  (AX) - data16 - CF

64
8086
Microprocessor Instruction Set

2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

INC reg/ mem

INC reg8 (reg8)  (reg8) + 1

INC reg16 (reg16)  (reg16) + 1

INC mem (mem)  (mem) + 1

DEC reg/ mem

DEC reg8 (reg8)  (reg8) - 1

DEC reg16 (reg16)  (reg16) - 1

DEC mem (mem)  (mem) - 1

65
8086
Microprocessor Instruction Set

2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

MUL reg/ mem

MUL reg For byte : (AX)  (AL) x (reg8)

For word : (DX)(AX)  (AX) x (reg16)

MUL mem For byte : (AX)  (AL) x (mem8)

For word : (DX)(AX)  (AX) x (mem16)

IMUL reg/ mem

IMUL reg For byte : (AX)  (AL) x (reg8)

For word : (DX)(AX)  (AX) x (reg16)

IMUL mem For byte : (AX)  (AX) x (mem8)

For word : (DX)(AX)  (AX) x (mem16)

66
8086
Microprocessor Instruction Set

2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

DIV reg/ mem

DIV reg For 16-bit :- 8-bit :

(AL)  (AX) :- (reg8) Quotient
(AH)  (AX) MOD(reg8) Remainder

For 32-bit :- 16-bit :

(AX)  (DX)(AX) :- (reg16)
Quotient
(DX)  (DX)(AX) MOD(reg16)
Remainder
DIV mem

For 16-bit :- 8-bit :

(AL)  (AX) :- (mem8) Quotient
(AH)  (AX) MOD(mem8)
Remainder

For 32-bit :- 16-bit :

(AX)  (DX)(AX) :- (mem16)
Quotient
(DX)  (DX)(AX) MOD(mem16)
Remainder 67
8086
Microprocessor Instruction Set

2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

IDIV reg/ mem

IDIV reg For 16-bit :- 8-bit :

(AL)  (AX) :- (reg8) Quotient
(AH)  (AX) MOD(reg8) Remainder

For 32-bit :- 16-bit :

(AX)  (DX)(AX) :- (reg16)
Quotient
(DX)  (DX)(AX) MOD(reg16)
Remainder
IDIV mem

For 16-bit :- 8-bit :

(AL)  (AX) :- (mem8) Quotient
(AH)  (AX) MOD(mem8)
Remainder

For 32-bit :- 16-bit :

(AX)  (DX)(AX) :- (mem16)
Quotient
(DX)  (DX)(AX) MOD(mem16)
Remainder 68
8086
Microprocessor Instruction Set

2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

CMP reg2/mem, reg1/ mem

CMP reg2, reg1 Modify flags  (reg2) – (reg1)

If (reg2) > (reg1) then CF=0, ZF=0, SF=0

If (reg2) < (reg1) then CF=1, ZF=0, SF=1
If (reg2) = (reg1) then CF=0, ZF=1, SF=0

CMP reg2, mem Modify flags  (reg2) – (mem)

If (reg2) > (mem) then CF=0, ZF=0, SF=0

If (reg2) < (mem) then CF=1, ZF=0, SF=1
If (reg2) = (mem) then CF=0, ZF=1, SF=0

CMP mem, reg1 Modify flags  (mem) – (reg1)

If (mem) > (reg1) then CF=0, ZF=0, SF=0

If (mem) < (reg1) then CF=1, ZF=0, SF=1
If (mem) = (reg1) then CF=0, ZF=1, SF=0

69
8086
Microprocessor Instruction Set

2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

CMP reg/mem, data

CMP reg, data Modify flags  (reg) – (data)

If (reg) > data then CF=0, ZF=0, SF=0

If (reg) < data then CF=1, ZF=0, SF=1
If (reg) = data then CF=0, ZF=1, SF=0

CMP mem, data Modify flags  (mem) – (mem)

If (mem) > data then CF=0, ZF=0, SF=0

If (mem) < data then CF=1, ZF=0, SF=1
If (mem) = data then CF=0, ZF=1, SF=0

70
8086
Microprocessor Instruction Set

2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

CMP A, data

CMP AL, data8 Modify flags  (AL) – data8

If (AL) > data8 then CF=0, ZF=0, SF=0

If (AL) < data8 then CF=1, ZF=0, SF=1
If (AL) = data8 then CF=0, ZF=1, SF=0

CMP AX, data16 Modify flags  (AX) – data16

If (AX) > data16 then CF=0, ZF=0,

SF=0
If (mem) < data16 then CF=1, ZF=0,
SF=1
If (mem) = data16 then CF=0, ZF=1,
SF=0

71
8086
Microprocessor Instruction Set

3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

72
8086
Microprocessor Instruction Set

3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

73
8086
Microprocessor Instruction Set

3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

74
8086
Microprocessor Instruction Set

3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

75
8086
Microprocessor Instruction Set

3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

76
8086
Microprocessor Instruction Set

3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

77
8086
Microprocessor Instruction Set

3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

78
8086
Microprocessor Instruction Set

3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

79
8086
Microprocessor Instruction Set

4. String Manipulation Instructions

 String Sequence of bytes or words

:
 8086 instruction set includes instruction string movement, comparison,
scan,
for load and store.

 REP instruction : used to repeat execution of string

prefix instructions
 String instructions end with S or SB or SW.
S represents string, SB string byte and SW string word.

 Offset or effective address of the source operand is stored in SI register

and
that of the destination operand is stored in DI register.

 Depending on the status of DF, SI and DI registers are automatically

updated.

 DF = 0  SI and DI are incremented by 1 for byte and 2 for word.

 DF = 1  SI and DI are decremented by 1 for byte and 2 for word.

80
8086
Microprocessor Instruction Set

4. String Manipulation Instructions

Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS

REP

REPZ/ REPE While CX  0 and ZF = 1, repeat execution

of string instruction and
(Repeat CMPS or SCAS (CX)  (CX) – 1
until ZF = 0)

REPNZ/ REPNE While CX  0 and ZF = 0, repeat execution

of
(Repeat CMPS or SCAS string instruction
until and (CX)  (CX) - 1
ZF = 1)

81
8086
Microprocessor Instruction Set

4. String Manipulation Instructions

Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS

MOVS

MOVSB MA = (DS) x 1610 + (SI)

MAE = (ES) x 1610 + (DI)

(MAE)  (MA)

If DF = 0, then (DI)  (DI) + 1; (SI)  (SI) + 1

If DF = 1, then (DI)  (DI) - 1; (SI)  (SI) - 1

MOVSW MA = (DS) x 1610 + (SI)

MAE = (ES) x 1610 + (DI)

(MAE ; MAE + 1)  (MA; MA + 1)

If DF = 0, then (DI)  (DI) + 2; (SI)  (SI) + 2 If

DF = 1, then (DI)  (DI) - 2; (SI)  (SI) - 2

82
8086
Microprocessor Instruction Set

4. String Manipulation Instructions

Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS

Compare two string byte or string word

CMPS

CMPSB MA = (DS) x 1610 + (SI)

MAE = (ES) x 1610 + (DI)

Modify flags  (MA) - (MAE)

If (MA) > (MAE), then CF = 0; ZF = 0; SF = 0

If (MA) < (MAE), then CF = 1; ZF = 0; SF = 1
CMPSW If (MA) = (MAE), then CF = 0; ZF = 1; SF = 0

For byte operation

If DF = 0, then (DI)  (DI) + 1; (SI)  (SI) + 1 If
DF = 1, then (DI)  (DI) - 1; (SI)  (SI) - 1

For word operation

If DF = 0, then (DI)  (DI) + 2; (SI)  (SI) + 2 If
DF = 1, then (DI)  (DI) - 2; (SI)  (SI) - 2

83
8086
Microprocessor Instruction Set

4. String Manipulation Instructions

Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS
Scan (compare) a string byte or word with accumulator
SCAS

SCASB MAE = (ES) x 1610 + (DI)

Modify flags  (AL) - (MAE)

If (AL) > (MAE), then CF = 0; ZF = 0; SF = 0

If (AL) < (MAE), then CF = 1; ZF = 0; SF = 1
If (AL) = (MAE), then CF = 0; ZF = 1; SF = 0

If DF = 0, then (DI)  (DI) + 1

If DF = 1, then (DI)  (DI) – 1

SCASW
MAE = (ES) x 1610 + (DI)
Modify flags  (AL) - (MAE)

If (AX) > (MAE ; MAE + 1), then CF = 0; ZF = 0; SF = 0

If (AX) < (MAE ; MAE + 1), then CF = 1; ZF = 0; SF = 1
If (AX) = (MAE ; MAE + 1), then CF = 0; ZF = 1; SF = 0

If DF = 0, then (DI)  (DI) + 2

84
If DF = 1, then (DI)  (DI) – 2
8086
Microprocessor Instruction Set

4. String Manipulation Instructions

Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS

Load string byte in to AL or string word in to AX

LODS

LODSB MA = (DS) x 1610 + (SI)

(AL)  (MA)

If DF = 0, then (SI)  (SI) + 1

If DF = 1, then (SI)  (SI) – 1

LODSW MA = (DS) x 1610 + (SI)

(AX)  (MA ; MA + 1)

If DF = 0, then (SI)  (SI) + 2

If DF = 1, then (SI)  (SI) – 2

85
8086
Microprocessor Instruction Set

4. String Manipulation Instructions

Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS

Store byte from AL or word from AX in to string

STOS

STOSB MAE = (ES) x 1610 + (DI)

(MAE)  (AL)

If DF = 0, then (DI)  (DI) + 1

If DF = 1, then (DI)  (DI) – 1

STOSW MAE = (ES) x 1610 + (DI)

(MAE ; MAE + 1 )  (AX)

If DF = 0, then (DI)  (DI) + 2

If DF = 1, then (DI)  (DI) – 2

86
8086
Microprocessor Instruction Set

5. Processor Control Instructions

Mnemonics Explanation
STC Set CF  1

CLC Clear CF  0

CMC Complement carry CF  CF/

STD Set direction flag DF  1

CLD Clear direction flag DF  0

STI Set interrupt enable flag IF  1

CLI Clear interrupt enable flag IF  0

NOP No operation

HLT Halt after interrupt is set

WAIT Wait for TEST pin active

ESC opcode mem/ reg Used to pass instruction to a

coprocessor which shares the address
and data bus with the 8086

LOCK Lock bus during next instruction 87

8086
Microprocessor Instruction Set

6. Control Transfer Instructions

Transfer the control to a specific destination or target

instruction Do not affect flags

 8086 Unconditional transfers

Mnemonics Explanation
CALL reg/ mem/ disp16 Call subroutine

RET Return from subroutine

JMP reg/ mem/ disp8/ disp16 Unconditional jump

88
8086
Microprocessor Instruction Set

6. Control Transfer Instructions

 8086 signed conditional  8086 unsigned conditional
branch instructions branch instructions

Checks flags

If conditions are true, the program control is

transferred to the new memory location in the
same segment by modifying the content of IP

89
8086
Microprocessor Instruction Set

6. Control Transfer Instructions

 8086 signed conditional  8086 unsigned conditional
branch instructions branch instructions

Name Alternate name Name Alternate name

JE disp8 JZ disp8 JE disp8 JZ disp8
Jump if equal Jump if result is 0 Jump if equal Jump if result is 0

JNE disp8 JNZ disp8 JNE disp8 JNZ disp8

Jump if not equal Jump if not zero Jump if not equal Jump if not zero
JG disp8 JNLE disp8 JA disp8 Jump JNBE disp8
Jump if greater Jump if not less or if above Jump if not below
equal or equal
JGE disp8 JNL disp8 JAE disp8 JNB disp8
Jump if greater Jump if not less Jump if above or Jump if not below
than or equal equal
JL disp8 JNGE disp8 JB disp8 Jump JNAE disp8
Jump if less than Jump if not if below Jump if not above
greater than or equal
or equal
JLE disp8 JNG disp8 JBE disp8 JNA disp8
Jump if less than Jump if not Jump if below or Jump if not above
or equal greater equal 90
8086
Microprocessor Instruction Set

6. Control Transfer Instructions

 8086 conditional branch instructions affecting individual

flags
Mnemonics Explanation

JC disp8 Jump if CF = 1

JNC disp8 Jump if CF = 0

JP disp8 Jump if PF = 1

JNP disp8 Jump if PF = 0

JO disp8 Jump if OF = 1

JNO disp8 Jump if OF = 0

JS disp8 Jump if SF = 1

JNS disp8 Jump if SF = 0

JZ disp8 Jump if result is zero, i.e, Z = 1

JNZ disp8 Jump if result is not zero, i.e, Z = 1

91
8086 Bus Cycle and Timing Diagram
The BIU initiates all external operations which are also called
bus activity. The external bus activities are repetitions of certain
basic operations. The basic operation performed by the CPU bus
are called bus cycles.

Depending on the activities of 8086 , the bus cycles can be

classified as
● Memory read cycle
● Memory write cycle
● I/O read cycle
● I/O write cycle
● Interrupt acknowledge cycle

T- states - The time taken to perform a bus cycle.

one T-state - Equal to one time period of the interval clock of

the processor.
Timing diagram provides information about the various conditions
(high state or low state) of the signals while a bus cycle is
executed.

Timing diagram is a graphical representation of the operations of

microprocessor with respect to time.

State - one cycle of the clock

Machine cycle: The basic microprocessor operation such as reading

a byte from memory or writing a byte to a port is called machine
cycle and made up of more than one state.

Instruction cycle: The time required for a microprocessor to fetch

and execute an entire instruction is called Instruction cycle and
made up of more than one machine cycle.

An instruction cycle is made up of machine cycles, and a machine

cycle is made up of states. The time for a state is determined by
the frequency of the clock signal.
Read cycle - timing diagram
The read cycle begins in T1 with the assertion of the address latch enable (ALE)
signal and also M/IO’ signal.

During the negative going edge of this signal, the valid address is latched on the
local bus. The BHE’ and A0 signals address low, high or both bytes.

From T1 to T4, the M/IO’ signal indicate a memory or I/O operation.

At T2, the address is removed from the local bus and is sent to the output.

The bus is then tristated. The read (RD ) control signal is also activated in T2.

The read (RD ) signal causes the addressed device to enable its data bus drivers.

After RD goes low, the valid data is available on the data bus.

The addressed device will drive the READY line high. When the processor returns
the read signal to high level, the addressed device will again tristate its bus
driver
Write cycle - timing diagram
A write cycle also begins with the assertion of ALE and the
emission of the address. The M/IO’ signal is again asserted to
indicate a memory or I/O Operation.

In T2, after sending the address in T1, the processor sends the
data to be written to the addressed location. The data remains
on the bus until the middle of T4 state.

The WR’ becomes active at the beginning of T2 (unlike RD’

is somewhat delayed in T2 to provide time for floating).

The BHE’ and A0 signals are used to select the proper byte or
bytes of memory or I/O word to be read or written.

The M/IO’, RD’ and WR’ signals indicate the types of data
transfer as specified in Table.
Program for block transfer of data written in 8086
Largest
Number
MOV SI, 5000 MOV AL, [SI]

MOV CL, [SI] SVEC: INC SI

MOV CH, 00 LOOP SVEW

INC SI MOV [6000], AL

MOV AL, [SI] HLT

DEC CL

INC SI

SVEW : CMP AL,[SI]

JNC SVEC
ASCENDING ORDER

MOV SI, 5000H

XCHG AL, [SI]

DEC SI
MOV CL, [SI]

DEC CL XCHG AL, [SI]

L1: MOV SI, 5000H INC SI

MOV CH, [SI] SVEW: DEC CH

DEC CH
JNZ VEMU
INC SI
DEC CL
VEMU: MOV AL, [SI]
JNZ L1
INC SI
HLT
CMP AL, [SI]

JC SVEW
Smallest
Number
MOV SI, 5000 MOV AL, [SI]

MOV CL, [SI] SVEC: INC SI

MOV CH, 00 LOOP SVEW

INC SI MOV [6000], AL

MOV AL, [SI] HLT

DEC CL

INC SI

SVEW : CMP AL,[SI]

JC SVEC
DESCENDING ORDER

MOV SI, 5000H

XCHG AL, [SI]

DEC SI
MOV CL, [SI]

DEC CL XCHG AL, [SI]

L1: MOV SI, 5000H INC SI

MOV CH, [SI] SVEW: DEC CH

DEC CH
JNZ SVEC
INC SI
DEC CL
SVEC: MOV AL, [SI]
JNZ L1
INC SI
HLT
CMP AL, [SI]

JNC SVEW
Factorial

MOV CX, [5000]

MOV AX, 0001

MOV DX, 0000

SVEW: MUL CX

LOOP SVEW

MOV [6000], AX

MOV [6002], DX

HLT
Fibonacci sequence

MOV AL, 00H

MOV SI, 5000H

ADD SI, 01H

MOV [SI], AL
MOV [SI], AL
ADD SI, 01H
LOOP L1
ADD AL, 01H
HLT
MOV [SI], AL

SUB CX, 0002H

L1: MOV AL, [SI-1]

ADD AL, [SI]

Fibonacci sequence

MOV AL, 00H

MOV SI, 5000H

ADD SI, 01H

MOV [SI], AL
MOV [SI], AL
ADD SI, 01H
LOOP L1
ADD AL, 01H
HLT
MOV [SI], AL

SUB CX, 0002H

L1: MOV AL, [SI-1]

ADD AL, [SI]

STRING MANIPULATION – MOVE

MOV CL,05H
MOV SI,1100H
MOV DI,1200H
CLD
L1 MOVSB
LOOP L1
HLT
Assembl directiv
er es
8086
Microprocessor Assemble
Directives

Instructions to the Assembler regarding the program being

executed.

Control the generation of machine codes and organization

of the program; but no machine codes are generated for
assembler directives.

Also called ‘pseudo

instructions’ Used to :
› specify the start and end of a
program
› attach value to variables
› allocate storage locations to
input/ output data
› define start and end of
segments, procedures, macros
etc..

93
8086
Microprocessor Assemble
Directives
DB Define Byte

DW Define a byte type (8-bit) variable

SEGMENT Reserves specific amount of memory

ENDS locations to each variable

ASSUME Range : 00H – FFH for unsigned value;

00H – 7FH for positive value and
ORG
80H – FFH for negative value
END
EVEN
EQU General form : variable DB value/ values

PROC
FAR Example:
NEAR LIST DB 7FH, 42H, 35H
ENDP
Three consecutive memory locations are reserved for
SHORT the variable LIST and each data specified in
the instruction are stored as initial value in the
MACRO reserved memory location
ENDM 94
8086
Microprocessor Assemble
Directives
DB Define Word

DW Define a word type (16-bit) variable

SEGMENT Reserves two consecutive memory locations

ENDS to each variable

ASSUME Range : 0000H – FFFFH for unsigned value;

0000H – 7FFFH for positive value and
ORG
8000H – FFFFH for negative value
END
EVEN
EQU General form : variable DW value/ values

PROC
FAR Example:
NEAR ALIST DW 6512H, 0F251H, 0CDE2H
ENDP
Six consecutive memory locations are reserved for
SHORT the variable ALIST and each 16-bit data specified in
the instruction is stored in two consecutive memory
MACRO location.
ENDM 95
8086
Microprocessor Assemble
Directives
DB SEGMENT : Used to indicate the beginning
of
DW a code/ data/ stack segment
ENDS : Used to indicate the end of a code/
SEGMENT data/ stack segment
ENDS
General form:
ASSUME

ORG
END Segnam SEGMENT
EVEN …
EQU … Program code
… or
PROC … Data Defining
… Statements
FAR …
NEAR
Segnam ENDS
ENDP

SHOR
T
MACRO User defined name of
the segment
ENDM 96
8086
Microprocessor Assemble
Directives
DB Informs the assembler the name of the
program/ data segment that should be used
DW for a specific segment.

SEGMENT General form:

ENDS
ASSUME segreg : segnam, .. , segreg :
ASSUME
segnam
ORG
User defined name of
END Segment Register
the segment
EVEN
EQU

PROC Example:
FAR
NEAR ASSUME CS: ACODE, DS:ADATA Tells the compiler that the
ENDP instructions of the program are
stored in the segment ACODE and
data are stored in the
SHORT segment ADATA

MACRO
ENDM 97
8086
Microprocessor Assemble
Directives
ORG (Origin) is used to assign the starting
DB
address (Effective address) for a program/ data
segment
DW END is used to terminate a program;
statements after END will be ignored
SEGMENT
ENDS EVEN : Informs the assembler to store program/
data segment starting from an even address
ASSUME
EQU (Equate) is used to attach a value to a
variable
ORG
Examples:
END
EVEN ORG 1000H Informs the assembler that the statements
EQU following ORG 1000H should be stored in
memory starting with effective address
1000H
PROC
FAR
LOOP EQU 10FEH Value of variable LOOP is 10FEH
NEAR
ENDP
_SDATA SEGMENT In this data segment, effective address of
SHOR ORG 1200H memory location assigned to A will be 1200H
A DB 4CH and that of B will be 1202H and 1203H.
T EVEN
B DW
MACRO 1052H 98
_SDATA ENDS
ENDM
8086
Microprocessor Assemble
Directives
PROC Indicates the beginning of a
DB
procedure
ENDP End of
DW procedure
FAR Intersegment call
SEGMENT
ENDS NEAR Intrasegment call

General form
ASSUME

ORG
procname PROC[NEAR/ FAR]
END
EVEN …
Program statements of the
…
EQU … procedure

Last statement of
PROC RET
the procedure
ENDP
FAR procname ENDP
NEAR

SHORT User defined name of

the procedure
MACRO
ENDM 99
8086
Microprocessor Assemble
Directives
DB
Examples:
DW

SEGMENT ADD64 PROC NEAR The subroutine/ procedure named ADD64 is

ENDS declared as NEAR and so the assembler will
… code the CALL and RET instructions involved
… in this procedure as near call and return
ASSUME …

RET
ORG ADD64 ENDP
END
EVEN
EQU CONVERT PROC FAR The subroutine/ procedure named CONVERT
is declared as FAR and so the assembler will
… code the CALL and RET instructions involved
PROC … in this procedure as far call and return
ENDP …
FAR RET
NEAR CONVERT ENDP

SHOR
T
MACRO
ENDM 100
8086
Microprocessor Assemble
Directives
DB Reserves one memory location for 8-bit
signed displacement in jump instructions
DW
Example:
SEGMENT
ENDS

ASSUME JMP SHORT The directive will reserve one

AHEAD memory location for 8-bit
displacement named AHEAD
ORG
END
EVEN
EQU

PROC
ENDP
FAR
NEAR

SHORT

MACRO
ENDM 101
8086
Microprocessor Assemble
Directives
DB MACRO Indicate the beginning of a macro

DW ENDM End of a macro

SEGMENT General form:

ENDS

ASSUME macroname MACRO[Arg1, Arg2 ...]

Program
… statements
ORG … in the macro
END …
EVEN
EQU macroname ENDM

PROC
ENDP
FAR User defined name of
NEAR the macro

SHORT

MACRO
ENDM 102
INTERRUPTS AND INTERRUPT SERVICE
ROUTINES
Interrupts
• A signal to the processor to halt its current
operation and immediately transfer control to
an interrupt service routine is called as
interrupt.
• Interrupts are triggered either by
hardware, as when the keyboard detects a key
press, or by software, as when a program
executes the INT instruction.
Interrupt structure of 8086

8086 Interrupt response

• Interrupt functions make the programming much
easier.
• There are also interrupt functions that work with
disk drive and other hardware. They are called as
software interrupts.
• Interrupts are also triggered by different hardware,
these are called hardware interrupts.
• To make a software interrupt there is an INT
instruction, it has very simple syntax: INT value.
• Where value can be a number between 0 to 255 (or
00 to FF H).
Interrupt Service Routines (ISRs)

• ISR is a routine that receives processor control when a

specific interrupt occurs.
• The 8086 will directly call the service routine for 256
vectored interrupts without any software processing. This
is in contrast to non vectored interrupts that transfer
control directly to a single interrupt service routine,
regardless of the interrupt source.
Interrupt vector table:
When an interrupt occurs, regardless of source, the
8086 does the following:
• The CPU pushes the flags register onto the stack.
• The CPU pushes a far return address (segment:offset)
onto the stack, segment value first.
• The CPU determines the cause of the interrupt (i.e., the
interrupt number) and fetches the four byte interrupt
vector from address 0 : vector x 4 (0:0, 0:4, 0:8 etc)
• The CPU transfers control to the routine specified by the
interrupt vector table entry.
After the completion of these steps, the interrupt service
routine takes control. When the interrupt service routine
wants to return control, it must execute an IRET
(interrupt return) instruction. The interrupt return pops
the far return address and the flags off the stack
Types of Interrupts
• Hardware Interrupt - External uses INTR and NMI
• Software Interrupt - Internal - from INT or INTO
• Processor Interrupt - Traps and 10 Software
Interrupts
• External - generated outside the CPU by other
hardware (INTR, NMI)
• Internal - generated within CPU as a result of an
instruction or operation (INT, INTO,
Divide Error and Single Step)
Dedicated Interrupts
• Divide Error Interrupt (Type 0)
This interrupt occurs automatically following the
execution of DIV or IDIV instructions when the
quotient exceeds the maximum value that the
division instructions allow.
• Single Step Interrupt (Type 1)
This interrupt occurs automatically after execution
of each instruction when the Trap Flag (TF) is set to
1. It is used to execute programs one instruction at a
time, after which an interrupt is requested.
Following the ISR, the next instruction is executed
and another single stepping interrupt request
occurs.
• Non Maskable Interrupt (Type 2)
It is the highest priority hardware interrupt that
triggers on the positive edge.
This interrupt occurs automatically when it
receives a low-to-high transition on its NMI input
pin.
This interrupt cannot be disabled or masked. It is
used to save program data or processor status in
case of system power failure.
• Breakpoint Interrupt (Type 3)
This interrupt is used to set break points in
software debugging programs.
• Overflow Interrupt (Type 4)
Software Interrupts (INT n)
• The software are non maskable
interrupts
interrupts. They are higher priority than
hardware interrupts.
Hardware Interrupts
• INTR and NMI are called hardware interrupts.
INTR is maskable and NMI is non-maskable
interrupts.
Interrupt Priority