History of the Intel 80x86

• 1971: Intel invents microprocessor – 4004–( 4-bit)

• 1975: 8080 introduced / 1976 : 8085
– 8-bit microprocessor
– Accumulator machine
• 1978: 8086 introduced /1979: 8088 8-bit version of 8086
– 16 bit microprocessor
– Accumulator plus dedicated registers
• 1980: IBM selects 8088 as basis for IBM PC
– 8088 is 8-bit external bus version of 8086
• 1980: 8087 floating point coprocessor
– adds 60 floating point instructions
– 80 bit floating point registers
– uses hybrid stack/register scheme 1
2
History of the Intel 80x86
• 1982: 80286 introduced
– 24-bit address
– memory mapping & protection
• 1985: 80386 introduced
– 32-bit address
– 32-bit GP registers
• 1989: 80486 introduced
• 1992: Pentium introduced
• 1995: Pentium Pro introduced
• 1996: Pentium with MMX extensions
– 57 new instructions
– Primarily for multimedia applications
3
• 1997: Pentium II (Pentium Pro with MMX)
History of the Intel 80x86
• 1999: Pentium III Introduced
• Supports Intel’s Internet Streaming SIMD technology
– Additional multimedia instructions
– Four 32-bit floating point operations in parallel
– Average, absolute difference, packed maximum/minimum
– Useful in speech recognition, video encoding/decoding
• 2000: Iitanium introduced
– Release of IA-64 (RISC-like) architecture
– Explicitly Parallel Instruction Computing (EPIC)
– 128-bit bundle with three instructions and a template
– 128 general purpose registers and 128 floating point registers
– Done by a partnership between HP and Intel
– Able to run both UNIX and Microsoft windows
• Intel architecture was due to the desire for backward compatibility
– Highly irregular architecture
– Over 50 million sold per year
4
MEMORY& IO 8086 ARCHITECTURE
INTERFACE

C-BUS

BIU ∑
6
INSTRUCTION
QUEUE
5
6-BYTE 4
B-BUS 3
(4-byte in 8088)
ES 2
CS 1
SS
DS
IP
TIMING & CONTROL

A- BUS

EU
AH AL
BH BL
CH CL
DH DL ALU 16-bit
SP
BP
SI
DI 5
FLAG
8086 Features
• 16-bit Arithmetic Logic Unit

• 16-bit data bus (8088 has 8-bit data bus)

• 20-bit address bus - 220 = 1,048,576 = 1 mega

The address refers to a byte in memory. In the 8088, these bytes come in on
the 8-bit data bus. In the 8086, bytes at even addresses come in on the low
half of the data bus (bitsD0-D7) and bytes at odd addresses come in on the upper
half of the data bus (bitsD8-D15).

The 8086 can read a 16-bit word at an even address in one operation and at an
odd address in two operations. The 8088 needs two operations in either case.

The least significant byte of a word on an 8086 family microprocessor is at the

lower address.

6
8086 Architecture
• The 8086 has two parts, the Bus Interface Unit (BIU) and the
Execution Unit (EU).

• The BIU fetches instructions, reads and writes data, and computes the
20-bit address.

• The EU decodes and executes the instructions using the 16-bit ALU.

• The BIU contains the following registers:

IP - the Instruction Pointer

CS - the Code Segment Register
DS - the Data Segment Register
SS - the Stack Segment Register
ES - the Extra Segment Register

The BIU fetches instructions using the CS and IP, written CS:IP, to construct
the 20-bit address. Data is fetched using a segment register (usually the DS)
and an effective address (EA) computed by the BIU depending on the
addressing mode.

7
8086
Architecture
The EU contains the following 16-bit registers:
Data group:
AX - the Accumulator
BX - the Base Register
CX - the Count Register
DX - the Data Register
Pointer group:
SP - the Stack Pointer
BP - the Base Pointer
Index group:
SI - the Source Index Register
DI - the Destination Register

These are referred to as general-purpose registers, although, as seen by

their names, they often have a special-purpose use for some instructions.

The AX, BX, CX, and DX registers can be considers as two 8-bit registers, a
High byte and a Low byte. This allows byte operations and compatibility with
the previous generation of 8-bit processors, the 8080 and 8085. 8085 source
code could be translated in 8086 code and assembled. The 8-bit registers
are:

AX --> AH,AL
BX --> BH,BL 8
CX --> CH,CL
8086 Programmer’s
Model
ES Extra Segment
BIU registers CS Code Segment
(20 bit adder) SS Stack Segment
DS Data Segment
IP Instruction Pointer

AX AH AL Accumulator
BX BH BL Base Register
CX CH CL Count Register
DX DH DL Data Register
SP Stack Pointer
BP Base Pointer
SI Source Index Register
EU registers
DI Destination Index Register
16 bit arithmetic
FLAGS

9
Overflow Flag Auxiliary Carry Flag
Direction Flag Parity Flag
Interrupt Flag Carry Flag

Trap Flag Sign Flag Zero Flag

10
The EU also contains the Flag Register which is a collection of condition
bits and control bits. The condition bits are set or cleared by the execution
of an instruction. The control bits are set by instructions to control some
operation of the CPU.

Bit 0 - CF Carry Flag - Set by carry out of MSB

Bit 2 - PF Parity Flag - Set if result has even parity
Bit 4 - AF Auxiliary Flag - for BCD arithmetic
Bit 6 - ZF Zero Flag - Set if result is zero
Bit 7 - SF Sign Flag = MSB of result
Bit 8 - TF Single Step Trap Flag
Bit 9 - IF Interrupt Enable Flag
Bit 10 - DF String Instruction Direction Flag
Bit 11 - OF Overflow Flag

Bits 1, 3, 5, 12-15 are undefined.

Bits 0-7 are 8085 compatible.

11
FORMATION OF PHYSICAL ADDRESS
• The data address used in the instruction is 16-bit called
“ Effective address” (EA) or offset. (it may be the content
of BX,BP,SI,DI and a displacement).

• CS:IP ; DS:SI; ES:DI and SS:SP or BP This way of

representing address are called Logical address .

• The Address appeared on (A0-A19) address bus is 20 bit

physical address computed is as:
PA= SEGMENT * 10H + EA

12
FORMATION OF PHYSICAL ADDRESS

16-bit 0 0 0 0 Segment Address

16-bit
Effective address or
offset

Σ Adder

20-bit Physical Address

13
The advantages of using segment registers are that they :
1. Allow the memory capacity to be 1 megabytes
even though the address associated with individual
instructions are only 16 bit wide.
2. Allow the instruction, data, or stack portion to be
more than 64K bytes long by using more than one
code, data, or stack segment.
3. Facilitate the use of separate memory area for a
program , its data, and the stack.
4. Permit a program and/or its data to be put into
different areas of memory each time the program
is executed.
14
Segments
Address
00000H
Segment Starting address is segment

register value shifted 4 places to the left.

CODE
64K Data
STACK Segment

DATA

EXTRA  CS:0000
64K Code
Segment
Segment
Registers

Segments are < or = 64K,

can overlap, start at an address
that ends in 0H. FFFFFH
MEMORY 15
16
8086 PIN DIAGRAM

17
8088 PIN DIAGRAM

18
8086 Pin Description
Vcc (pin 40) : Power (+5V±10% VDC)
Gnd (pin 1 and 20) : Ground
AD0-AD15 , A19/S6, A18/S5, A17/S4, A16/S3 : 20 -bit Address Bus
MN/MX’ (input) : Indicates Operating mode (MN/MX=+5V Minimum mode;
MN?MX=0V maximum mode)
READY (input , Active High) : take uP to wait state
CLK (input) : Provides basic timing for the processor
RESET (input, Active High) : At least 4 clock cycles Causes the uP immediately
terminate its present activity. (CS=FFFFH and IP=0000H)
TEST’ (input , Active Low) : Connect this to HIGH
HOLD (input , Active High) : Connect this to LOW
HLDA (output , Active High) : Hold Ack
INTR (input , Active High) : Interrupt request
INTA’ (output , Active Low) : Interrupt Acknowledge
NMI (input , Active High) : Non-maskable interrupt
19
8086 Pin Description
DEN’ (output) : Data Enable. It is LOW when processor wants to
receive data or processor is giving out data (to74245)
DT/R’ (output) : Data Transmit/Receive.
When High, data from uP to memory
When Low, data is from memory to uP (to74245 dir)
M/IO’ (output) : If High uP access memory
If Low uP access I/O Device.
RD’ (output) : When Low, uP is performing a read operation
WR’ (output) : When Low, uP is performing a write operation
ALE (output) : Address Latch Enable , Active High
Provided by uP to latch address
When HIGH, uP is using AD0..AD15, A19/S6,
A18/S5, A17/S4, A16/S3 as address lines
20
8086 Pin Description
• S7=1;S5=IF S4 S3 SEG.R
• S6=1 , 8086 is bus EG
master. 0 0 ES
• S6=0, 8086 not a bus
0 1 SS
master.
1 0 CS

1 1 DS

21
MAXIMUM MODE PIN DESCRIPTION

• LOCK- (output) used to lock the bus

• RQ/GT0,RQ/GT1- (input/output) used for co-processor
and DMA type data transfer.
• S0,S1,S2-Status O/P (Used to generate control signals)
• QS0,QS1- (output) Used in multiprocessor configuration.

22
QS1 QS0 FUNCTION
0 0 QUEUE IDLE
0 1 FIRST BYTE OF OPCODE
1 0 QUEUE IS EMPTY
1 1 SUBSEQUENT BYTE OF OPCODE

23
S2 S1 S0 FUNCTION
0 0 0 Interrupt Acknowledge (INTA)
0 0 1 I/O Read
0 1 0 I/O Write
0 1 1 Halt
1 0 0 Op-code fetch
1 0 1 Memory read
1 1 0 Memory write
1 1 1 Passive
24
BUS CYCLE STATUS (8088)

IO/M DT/R SS0 FUNCTION

0 0 0 Interrupt Acknowledge (INTA)
0 0 1 Memory read
0 1 0 Memory write
0 1 1 Halt
1 0 0 Op-code fetch
1 0 1 I/O Read
1 1 0 I/O Write
1 1 1 Passive
25
26
27
28
S3,S4,S5,S6,S7

74LS373
A16/S3-A9/S6 OCTAL A16-A19
LATCH

BHE/S7 BHE
MICROPROCESSOR
8086

74LS373
AD8-AD15 A8-A15

74LS245 D8-D15

AD0-AD7 74LS373 A0-A7

74LS245 D0-D7

CONTROL BUS RD,WR,M/IO,DEN,DT/R etc

8086 BUS CONFIGURATION 29

SYSTEM READY TO INTERFACE MEMORY AND I/O
MINIMUM MODE BUS CONFIUGURATION

30
MAXIMUM MODE BUS CONFIGURATION

31
TDVCL

BUS TIMING MINIMUM MODE READ

READ
FOR 5 MHz TCLAV = 110nS & TDVCL=30nS 32
FOR 8MHz TCLAV = 60nS & TDVCL=20nS
33
MINIMUM MODE WRITE

34
MAXIMUM MODE READ CYCLE

35
MAXIMUM MODE WRITE BUS TIMING

36
37
38
39
5Mhz 8Mhz

40
41
42
43
44
MEMORY ACCESS TIME
Time lapsed between valid address to valid data (Tacc)

45
WAIT STATE CALCULATION (CASE-1)
Add./Data
Add.
Ai
373 Meme.
8086
latch
Add. CE
Di
decder

Data Data
245

110ns 18ns 30ns 450ns 10ns 30ns 46

Example:
A. Processor - 8MHZ

Memory Tacc=45 ns
Latch 74ls373 propagation delay
T373 =18ns
Decoder
Tides = 30ns
T245 =10ns

If n=0 ; 375> 183

So, no Wait state
47
WAIT STATE CALCULATION ( CASE-2)

MEMOREY

48
Example:

Memory

Other components propagation delay

To satisfy the condition

49
Either one formula can be used to
calculate the wait states

50
ADD.BUS
A0-A19,

DATA BUS
CPU
8088

D0-D7

ROM/
RAM

MEMORY INTERFACE WITH 8088 51

ADD.BUS
A1-A19,
DATA BUS
D8-D15 HIGH ORDER
CPU
8086

D0-D7 LOW ORDER

BHE
A0
ROM/ ROM/
RAM RAM
EVEN ODD
ADD. ADD.

MEMORY INTERFACE WITH 8086 52

BHE A0 DATA LINES ACTIVE
0 0 D0-D15 WORD TRANSFER
0 1 D8-D15 BYTE TRANSFER
1 0 D0-D7 BYTE TRANSFER
WORD TRANSFER AT ODD ADD
0 1
LSB OF WORD TRANSFER ON D8-D15
1 0 MSB OF WORD TRANSFER ON D0-D7

1 1 PASSIVE
53
BHE = 0 A0 = 0 ( BLE )
FFFF FFFE
FFFD FFFC
FFFB FFFA

HIGH BANK LOW BANK

ODD EVEN

0005 0004
0003 0002
0001 0000
D15 D8 D7 D0
54
Memory banks (8086)
MEMORY
• TYPES OF MEMORY
• READ ONLY MEMORY (ROM)
• READ / WRITE MEMORY (RAM)
• ROM NEEDED TO STORE SYSTEM STARTUP
PROGRAMS
• AND RAM NEEDED TO STORE USER
PROGRAM AND DATA

55
EPROM PIN OUT

56
SRAM PIN OUT
61256 32K X 8
6164 8K X 8
15 13 6116 2K X8
11
A14 NC 1 28 VCC VCC
A12 A12 2 27 WR WR
A7 3 (1) (24) 26 VCC CS2 A13
A6 A8
A5 A9
A4 WR A11 A11
A3 RD
A2 A10
A1 CS CS CS
A0 D7
D0 D6
D1 D5
D2 D4
GND 14 (12) (13)15 D3

57
1 15
A Y0
2 14
B Y1
3 13
C Y2
12
Y3
6 11
G1
Y4
4 10
G2A Y5
5 9
Y6
G2B 7
Y7

Logical diagram of 74Ls138 58

TRUTH TABLE (74138)
G1 G2A G2B A B C Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

1 X 0 X X X X X X X X X X x
1 0 0 0 0 0 0 1 1 1 1 1 1 1
1 0 0 0 0 1 1 0 1 1 1 1 1 1
1 0 0 0 1 0 1 1 0 1 1 1 1 1
1 0 0 0 1 1 1 1 1 0 1 1 1 1
1 0 0 1 0 0 1 1 1 1 0 1 1 1
1 0 0 1 0 1 1 1 1 1 1 0 1 1
1 0 0 1 1 0 1 1 1 1 1 1 0 1
1 0 0 1 1 1 1 1 1 1 1 1 1 0
59
1A
1Y0

1B
1Y1

1E 1Y2

1Y3

2A 2Y0

2B 2Y1

2Y2
2E
2Y3

Logical diagram of 74Ls139 (Dual 2:4 decoder) 60

ADDRESS DECODING SCHEMES

There are three types of address decoding

scheme:
1. Partial decoding
2. Exhaustive decoding
3. Linear select

61
Partial decoding

• In this scheme all the processor address

lines are not decoded due to that in system
64k-bytes of memory is not available
• Decoding hardware is less so system
development cost is less
• Used for small system

62
Exhaustive decoding
• In this scheme all processor address lines
are decode due to that 64k-bytes of memory
address space is available
• Decoding hardware is more due to that
system cost increases
• Used for large systems where all 64k
address space is Required

63
Linear select
• In this address decoding scheme decoding
hardware is not used linearly unused
address lines are used to select the memory
chips in this scheme also 64-k memory
address space is not available
• Used for very small system

64
Example 1: In the 8086(8 MHZ) based microcomputer system requires 32k-
bytes of EPROM and 32k-bytes of RAM select suitable memory chips to
implement the EPROM and RAM . Draw address decoding logic and its memory
map also calculate the required access time of memory chips for zero wait state
Assuming propagation delays
T373 =30ns; T decoders =18ns; T245 =10ns TCLAV =60ns; TDVCL=20ns.

Solution: TCLCL =125ns

T data valid = T 373 + T decoder +T245 +TCLAV+TDVCL +Tacc
T data valid = 30ns +18ns +10ns +60ns +20ns +Tacc
T data valid = 138ns +Tacc
(3+n) * TCLCL ≥ T data valid if n=0 i.e. zero wait state
375 ≥ 138ns + Tacc
T acc ≤ 237ns
Access time of memory chips in 8MHz system must be
less than 237ns .Select memory chip whose access time is
230ns 65
Address Bit Map
To Address decoder To 16K Memory
A19A18A17A16 A15 A14A13A12 A11A10A9A8 A7A6A5A4 A3A2A1 A0 (BLE)

0 0 0 0 0 X X X X X X X X X X X X X X 0= 00000H
74139 74138 RAM EVEN ADDRESSED
07FFEH
(EVEN)
0 0 0 0 0 X X X X X X X X X X X X X X 1= 00001H
RAM ODD ADDRESSED 07FFFH
(ODD)

1 1 1 1 1 X X X X X X X X X X X X X X 0= F8000H
EPROM EVEN ADDRESSED FFFFEH
(EVEN)

1 1 1 1 1 X X X X X X X X X X X X X X 1= F8001H
EPROM ODD ADDRESSED FFFFFH
(ODD)

66
A1
A15
EXAMPLE-1. A Y0 A14 16KX 8
A16
ADD.DECODING LOGIC B Y1 OE RAM
A17 Y2 RD

EVEN
8086 SYSTEM C EVEN
Y3 WR WE
USING SEPARATE BANK M/IO G1 Y4
DECODERS GND G2A Y5
G2B Y6
Y7 A1
A15 A14 16K X 8
A16 A Y0 EPROM
B Y1

EVEN

D0-D7
A17 C Y2 RD OE EVEN
G1
Y3
M/IO Y4
A18 GND G2A Y5
A19
1A 1Y0 G2B Y6
Y7
EVEN

1B 1Y1
A0 A15 A1
1E 1Y2 A Y0 A14 16K X 8
1Y3 A16 B Y1 OE
ODD
RD RAM
A18 A17 C Y2
2A 2Y0 Y3 WE ODD
ODD

A19 2B 2Y1 M/IO G1

Y4 WR

D8-D15
GND G2A
2E 2Y2 Y5
BHE 2Y3 G2B Y6
Y7
A15 A1
A16 A Y0 A14
ODD

B Y1 16K X 8
A17 C Y2 EPROM
Y3 OE
M/IO G1 RD ODD
Y4
GND G2A Y5
G2B Y6 67
Y7
BHE =0 (HIGH BUS) A0 = 0 (LOW BUS)
FFFFFH FFFFEH

EPROM 16K EPROM 16K

F8001H F8000H
F7FFFH F7FFEH
ED
ED U S
S 480K 480K
U UN
UN
08001H 08000H
07FFFH 07FFEH
RAM 16K RAM 16K

00001H 00000H
D8 D15 D0 D7 68
MEMORY MAP EXAMPLE-1
Example 2: In the 8086(5 MHZ) based microcomputer system requires 64k-
bytes of EPROM and 128k-bytes of SRAM. Implement EPROM using 32k*8 and
RAM using 64k*8 . Draw address decoding logic and its memory map also
calculate the required access time of memory chips for zero wait state
Assuming propagation delays
T373 =30ns; T decoders =18ns; T245 =10ns TCLAV =110ns; TDVCL=30ns.

Solution: TCLCL =200ns

T data valid = T 373 + T decoder +T245 +TCLAV+TDVCL +Tacc
T data valid = 30ns +18ns +10ns +110ns +30ns +Tacc
T data valid = 198ns +Tacc
(3+n) * TCLCL ≥ T data valid if n=0 i.e. zero wait state
600 ≥ 198ns + Tacc
T acc ≤ 402ns
Access time of memory chips in 8MHz system must be
less than 402ns .Select memory chip whose access time is
400ns 69
To 64K Memory
Add. decoder To 32K Memory
A19A18A17 A16 A15 A14A13A12 A11A10A9A8 A7A6A5A4 A3A2A1 A0 (BLE)

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0= 00000H
0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0= 0FFFEH
RAM EVEN

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1= 00001H
0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1= 0FFFFH
RAM ODD

1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0= E0000H
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0= FFFFEH
EPROM EVEN

1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1= E0001H
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1= FFFFFH
EPROM ODD
Address Bit Map Exhaustive 70
A1
A16
EXAMPLE-2. A Y0 A15 32KX 8
A17 Y1
ADD.DECODING B OE RAM
A18 Y2 RD

EVEN
LOGIC C EVEN
Y3 WR WE
8086 SYSTEM M/IO G1 Y4
USING A19 G2A Y5 CS
SEPARATE BANK A0 G2B Y6
DECODERS Y7 A1
A16 A16 64K X 8
A17 A Y0 EPROM
B Y1

EVEN
A18

D0-D7
C Y2 RD OE EVEN
G1
Y3
A19 M/IO Y4
G2A Y5
A0 CS
G2B Y6
Y7
A16 A1
A17 A Y0 A15 32K X 8
A18 B ODD
Y1 OE RAM
C Y2 RD
Y3 WE ODD
M/IO G1
Y4 WR

D8-D15
A19 G2A Y5
BHE G2B Y6 CS
Y7
A16 A1
A17 A Y0 A16
ODD

B Y1 64K X 8
A18 C Y2 EPROM
Y3 OE
RD ODD
A19 M/IO G1
Y4
G2A Y5
G2B Y6 CS 71
BHE Y7
BHE BHWR

WR
BLWR
A0

SEPARATE BANK WRITE SIGNALS

• During a read 16-bits are always
transferred. The 8086 microprocessor uses
the data it needs (low byte, high byte, word)
without any conflicts or problems.
Example 1 will be solved using separate bank write signals
72
A1
D0-7
A15 32KX 8
EXAMPLE-2. RAM
ADD.DECODING LOGIC RD OE A1
EVEN
8086 SYSTEM WE A15 32K X 8
BLWR
RAM DO-7
RD OE
A16 Y0 CS ODD
A WE
A17 B Y1 BHWR
A18 C Y2
Y3 CS
M/IO G1 Y4
A19 G2A Y5

D0-D7
GND G2B Y6
Y7
A16 A1
A17 A Y0 A16

BUS
SYSTEM
B Y1 64K X 8
A18 C Y2 EPROM

BUS
SYSTEM
Y3 OE
RD EVEN
A19 M/IO G1
Y4
G2A Y5
GND
G2B Y6 CS
Y7

D8-D15
BHE BHWR
A1
A16
64K X 8
EPROM
OE
WR RD ODD
BLWR
A0 CS
73
SEPARATE BANK WRITE SIGNALS
BHE =0 (HIGH BUS) A0 = 0 (LOW BUS)
FFFFFH FFFFEH

EPROM 64K EPROM 64K

E0001H E0000H
DFFFFH DFFFEH
ED
ED U S
S 416K 416K
U UN
UN
10001H 10000H
0FFFFH 0FFFEH
RAM 32K RAM 32K

00001H 00000H
D8 D15 D0 D7 74
MEMORY MAP EXAMPLE-2
T1 T2 T3 T4

TCLCL

75
76