Computer Organisation and Architecture

UNIT III: Basic Computer Organisation and

Design
Topic :Instruction Codes & Computer
Registers
Contents:
Instruction Codes.
Computer Registers.
Computer Instruction.
Memory reference Instructions.
Register Reference Instructions.
Input-Output.
Instruction Cycle.
Interrupt.
Instruction Codes

The internal organization of a digital system is defined by the

sequence of micro-operations, it performs on the data stored in its
registers.

Program:
A Program is a set of instructions that specify the operations,
operands and the sequence by which processing has to occur.
Instruction Codes:

An Instruction code is a group of bits that instructs the computer to

perform a specific operation.
Instruction code is divided into two parts:
Opcode – Specifies the operation (Addition/subtraction/…
Address – Specifies the Operand/register/Memory word
15 12 11 0

Opcode Address
Cont..
Opcode specifies the operation to be performed on some data stored in
processor registers (or) in memory.

Therefore, an instruction code specifies not only the operations but also
the registers (or) memory words where the operands to be stored.
Stored Program Organization

The simplest way to organize the computer is to have one processor register
and an instruction code format with two parts.

The first part specifies the operation to be performed and the second
specifies an address which tells to the control where to find an operand in
memory.

 This operand is read from memory and used as the data to be operated on
together with the data stored in the processor register.
Stored Program Organization:
Cont..
Instructions are stored in one section of memory and data in another.
For a memory unit with 4096 word we need 12 bits to specify an
address (2^12 =4096).

If we store each instruction code in one 16 – bit memory word, 12 – bits
for address 4 -bits for opcode.

The control reads 16 – bits instruction from the program portion of

memory and then executes the operation specified by the opcode.
Cont..
Computers having a single – processor register usually which is “Accumulator or
AC”.
The operation is performed with the memory operand and the content of AC.

If an operation is an instruction code does not require an operand from the
memory, the rest of bits in the instruction can be used for other purpose.

Ex : Operations clear AC, complement AC, Increment AC operate on data stored
in AC register. They do not need an operand from memory.

For these type of operations, the 2nd part of the instruction code (0-11) is not
needed for specifying the memory address and can be used for other purpose.
Instruction Format

Generally in the Instruction Format 12 – bits are reserved for Address,

3 – Bits are reserved for Opcode and 1 – Bit is reserved for Mode
(Direct or Indirect Addressing mode).
Direct and Indirect addressing
If the second part of an instruction format specifies the address of an operand, then
the instruction is said to have a direct address.

 In Indirect address, the bits in the second part of the instruction designate an
address of a memory word in which the address of the operand is found.

One bit of the instruction code can be used to distinguish between a direct and an
indirect address.

 The mode bit is 0 for a direct address and 1 for an indirect address.
Direct and Indirect addressing
Direct Address
 A direct address instruction is shown in Figure 2.2. It is placed in address
22 in memory.

The I bit is 0, so the instruction is recognized as a direct address

instruction.

The opcode specifies an ADD instruction, and the address part is the binary
equivalent of 457.

The control finds the operand in memory at address 457 and adds it to the
content of AC.
Indirect Address

The instruction in address 35 shown in Figure 2.3 has a mode bit I = 1,

recognized as an indirect address instruction.

The address part is the binary equivalent of 300.

The control goes to address 300 to find the address of the operand. The
address of the operand in this case is 1350.

The operand found in address 1350 is then added to the content of AC.
Indirect Address
The indirect address instruction needs two references to memory to fetch an operand.

 The first reference is needed to read the address of the operand

 Second reference is for the operand itself.

The memory word that holds the address of the operand in an indirect address
instruction is used as a pointer to an array of data.
Difference between Direct and Indirect address
Computer Registers
A register is a group of flip-flops with each flip-flop capable of storing
one bit of information.
An n-bit register has a group of n flip-flops, a register may have
combinational gates that perform certain data-processing tasks.
A register consists of a group of flip-flops and gates that effect their
transition.
The flip-flops holds the binary information and the gates control when
and how new information is transferred into the register.
Computer Registers
Computer Registers
Cont..
 The data register (DR) holds the operand read from the memory.

 The accumulator (AC) register is a general purpose processing register.

 The instruction read from memory is placed in the instruction register (IR).

 The temporary register (TR) is used for holding temporary data during the processing.

 The memory address register (AR) has 12 bits since this is the width of a memory address.

 The program counter (PC) also has 12 bits and it holds the address of the next instruction to be read
from memory after the current instruction is executed.

 The input register (INPR) receives an 8-bit character from an input device.

 The output register (OUTR) holds an 8-bit character for an output device.
Common Bus system
The basic computer has eight registers, a memory unit and a control unit.

There must be a path to transfer information from one register to another or

between memory and registers.

The number of wires will be excessive if connections are made between the
outputs of each register and the inputs of the other registers.

A more efficient scheme for transferring information in a system with many

registers is to use a common bus.

The figure shown below shows Basic Computer Registers using Common bus
system.
Common Bus System for Basic Computer

 The outputs of seven registers and memory are connected to the common bus.

 The specific output that is selected for the bus lines at any given time is determined from the
binary value of the selection variables S2, S1, and S0.

 The particular register whose LD (load) input is enabled receives the data from the bus during
the next clock pulse transition.

 The memory receives the contents of the bus when its write input is activated.

 The memory places its 16-bit output onto the bus when the read input is activated and
S2 S1 S0 = 1 1 1
Common Bus System for Basic Computer

 Four registers, DR, AC, IR, and TR have 16 bits each.



 Two registers, AR and PC, have 12 bits each since they hold a memory address.

 When the contents of AR or PC are applied to the 16-bit common bus, the four most
significant bits are set to 0’s. When AR and PC receive information from the bus, only the
12 least significant bits are transferred into the register.

 The input register INPR and the output register OUTR have 8 bits each and communicate
with the eight least significant bits in the bus.

 INPR is connected to provide information to the bus but OUTR can only receive
information from the bus.
Common Bus System for Basic Computer

 Five registers have three control inputs: LD (load), INR (increment), and CLR (clear).
 Two registers have only a LD input.
 AR must always be used to specify a memory address; therefore memory address is connected to
AR.
 ALU has three sets of inputs:
 Set of 16-bit inputs come from the outputs of AC.
 Set of 16-bits come from the data register DR.
 Set of 8-bit inputs come from the input register INPR.
 The result of ALU is transferred to AC and if any end carry is there it will be transferred to the
flip-flop E (extended AC bit).
 The clock transition at the end of the cycle transfers the content of the bus into the designated
destination register and the output of the adder and logic circuit into AC
Computer Instructions
The basic computer has three instruction code formats.
Each format has 16 bits.
The operation code (opcode) part of the instruction contains three bits and the
meaning of the remaining 13 bits depends on the operation code encountered.
For Memory – Reference Instructions the opcode is 011, and the mode value will be
either 0 or 1.
A memory-reference instruction uses 12 bits to specify an address and one bit to
specify the addressing mode I.
I is equal to 0 for direct addressing.
I is equal to 1 for indirect addressing.
The Register-Reference instructions are recognized by the opcode 111 with a 0 in the
leftmost bit (bit 15) of the instruction.
The Input-Output instructions are recognized by the opcode 111 with a 1 in the
leftmost bit (bit 15) of the instruction.
Basic Computer Instruction Formats
Cont..
Instruction Set Completeness
A Computer should have a set of instructions so that the user can
construct machine language programs to evaluate any function that is
known to be computable.
The set of instructions are said to be complete if the computer includes
a sufficient number of instructions from the following categories:
Arithmetic, Logical and shift instructions.
Instructions from moving information to and from memory and processor
registers.
Program control instructions together with instructions that check the status
conditions.
Input and output instructions.
Instruction Cycle
The program is executed in the computer by going through a cycle for
each instruction:
Fetch an instruction from the memory.
Decode the instruction.
Read the effective address from the memory if the instruction has an
indirect address.
Execute the instruction.
Instruction Cycle

Fetch and Decode:

T0: AR PC (S0S1S2=010, T0=1)
T1: IR  M [AR], PC  PC + 1 (S0S1S2=111, T1=1)
T2: D0, . . . , D7  Decode IR(12-14), AR  IR(0-11), I  IR(15)
Instruction Cycle

T1
S2
T0 S1 Bus

S0

Memory Unit 7
Address
Read

AR 1

LD
PC 2

INR

IR 5

LD Clock
Common bus
Instruction Cycle
Instruction Cycle
The selected operation is activated with the clock transition associated
with timing signal T3. This can be symbolized as follows:
 M[AR]
 Nothing
 Execute a Register – reference Instruction
 Execute an input – output Instruction
At time T4 executing memory reference instruction is completed.
Memory Reference Instructions
In order to specify the microoperations needed for the execution of
each instruction, it is necessary that the function that they are intended
to perform be defined precisely.

Symbol Operation Symbol Description

Decoder
AND D0 AC  AC ˄ M[AR]
ADD D1 AC  AC + M[AR], E  COUT
LDA D2 AC  M[AR]
STA D3 M[AR]  AC
BUN D4 PC  AR
BSA D5 M[AR]  PC, PC  AR+1
ISZ D6 M[AR]  M[AR] +1,
If M[AR] +1 = 0 then PC  PC+1
Memory Reference Instructions
ADD to AC

This instruction adds the content of the memory word specified by the effective address to the
value of AC. The sum is transferred into AC. The sum is transferred into AC and the output carry C out is
transferred to the E (extended accumulator) flip-flop. The following is the micro operation required for
this:

DR ← M [AR]

AC ← AC+DR, E ← Cout , SC ← 0
Memory Reference Instructions

LDA: Load to AC

This instruction transfers the memory word specified by the effective address to AC.
The following is the micro operation required for this:

DR ← M [AR]

AC ← DR, SC ← 0
Memory Reference Instructions

STA: Store AC

This instruction stores the content of AC into the memory word specified by the
effective address. Since the output of AC is applied to the bus and the data input of memory is
connected to the bus. The following is the micro operation required for this:

M [AR] ← AC, SC ← 0
Memory Reference Instructions
BUN: Branch Unconditionally

PC holds the address of the instruction to be read from the next instruction cycle. And PC is
incremented at time T1 to prepare it for the address of the next instruction in the program sequence.

This instruction allows the programmer to specify an instruction out of sequence and we say that the
program branches or jumps unconditionally. The following is the micro operation required for this:

PC ← AR, SC ← 0

The effective address from AR is transferred through the common bus to PC. Resetting the SC to 0
transfers the control to T0. The next instruction is then fetched and executed from the memory address given
by the new value in PC.
Memory Reference Instructions

BSA: Branch and save Return Address

The BSA instruction stores the address of the next instruction in sequence (which is
available in PC) into a memory location specified by the effective address. The effective address
plus one is then transferred to PC to serve as the address of the first instruction in the subroutine.
The following is the micro operation required for this:

M [AR] ← PC, PC ← AR + 1
Memory Reference Instructions
ISZ: Increment and Skip if Zero

This instruction increment the word specified by the effective address, and if the incremented
value is equal to 0, PC is incremented by 1. The programmer usually stores a negative number (in 2’s
complement) in the memory word. As this negative number is incremented by 1, it eventually reaches
the value of zero. At that time PC is incremented by 1 in order to skip the next instruction in the
program.

DR ← M [AR]

DR ← DR + 1

M [AR] ← DR, if (DR=0) then PC ← PC +1), SC ← 0

Memory Reference Instructions
AND to AC

This is an instruction that performs the AND logic operation on pairs of bits in AC and the
memory word specified by the effective address. The result of the operation is transferred to AC. The
following is the micro operation r3equired for this:

DR ← M [AR]

AC ← AC ^ DR, SC ← 0
Register Reference Instructions

The register reference instructions are recognized by the control when

D7=1 and I=0.
These instructions use bits 0 through 11 of the instruction code to
specify one of 12 instructions.
These 12 bits are available in IR(0-11)
Register Reference Instructions
Input – output configuration
Serial Computer
Input – output Communication registers and flip
Terminal Interface - flops

FGO

Receiver
Printer OUTR
interface

AC

Transmitter
Keyboard INPR
interface

FGI
Input Output Instructions
 Input output instructions are needed for transferring information to and from AC.
 Input output instructions have an Opcode and recognized by the control D7=1 and I=1
 Initially, the input flag FGI is cleared to 0. When a key is struck in the keyboard, an 8-
bit alphanumeric code is shifted into INPR and the input flag FGI is set to 1. As long as
the flag is set, the information in INPR cannot be changed by striking another key. The
computer checks the flag bit; if it is 1, the information from INPR is transferred in
parallel into AC and FGI is cleared to 0. Once the flag is cleared, new information can
be shifted into INPR by striking another key.
 The output register OUTR works similarly but the direction of information flow is
reversed. Initially, the output flag FGO is set to 1. The computer checks the flag bit; if it
is 1, the information from AC is transferred in parallel to OUTR and FGO is cleared to
0. The output device accepts the coded information, prints the corresponding
character, and when the operation is completed, it sets FGO to 1. The computer does
not load a new character into OUTR when FGO is 0 because this condition indicates
that the output device is in the process of printing the character.
Input Output Instructions
Input Output Instructions
The INP instruction transfers the input information from INPR into the eight
low-order bits of AC and also clears the input flag to 0.
 The OUT instruction transfers the eight least significant bits of AC into the
output register OUTR and clears the output flag to 0.
 The next two instructions in check the status of the flags and cause a skip of the
next instruction if the flag is 1.
The instruction that is skipped will normally be a branch instruction to return
and check the flag again.
 The branch instruction is not skipped if the flag is 0. If the flag is 1, the branch
instruction is skipped and an input or output instruction is executed.
 The last two instructions set and clear an interrupt enable flip-flop IEN. The
purpose of IEN is explained in conjunction with the interrupt operation.
Program Interrupt
The interrupt enable flip-flop IEN can be set and cleared with two
instruction.

When IEN is cleared to 0, the flags can not interrupt the computer.

When IEN is cleared to 1, the computer can be interrupted.

Flow chart for Interrupt Cycle
Program Interrupt
An interrupt flip – flop R is included in the computer. When R =0, the
computer goes through an instruction cycle.

During the execution phase of instruction cycle IEN is checked by the

computer. If it is 0, it indicates that there is no interrupt. So the control
continues with the next instruction in the instruction cycle.

If IEN =1, control checks the flag bits (FGI &FGO) If both flags are 0,
the control continues with the next instruction cycle.
Demonstration of the interrupt cycle