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Chapter Input/
Output
7
William Stallings , Computer Organization and Architecture, 9 th Edition
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Objectives
 Why are peripherals not connected directly to the system bus?
 Why IO module is needed?
 How to control IO devices?
 How to increase IO operations?
 After studying this chapter, you should be able to:
 Explain the use of I/O modules as part of a computer
organization.
 Understand the difference between programmed I/O
and interrupt-driven I/O and discuss their relative
merits.
 Present an overview of the operation of direct memory
access.
 Explain the function and use of I/O channels.
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Contents
 7.1 External Devices
 7.2 I/O Modules
 7.3 Programmed I/O
 7.4 Interrupt-Driven I/O
 7.5 Direct Memory Access
 7.6 I/O Channels and Processors
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Why are devices not connected to
system bus?
 There are a wide variety of peripherals with various methods of
operation. It would be impractical to incorporate the necessary logic
within the processor to control a range of devices.
 The data transfer rate of peripherals is often much slower than that of
the memory or processor. Thus, it is impractical to use the high-speed
system bus to communicate directly with a peripheral.
 The data transfer rate of some peripherals can be faster than that of the
memory or processor. Again, the mismatch would lead to
inefficiencies if not managed properly.
 Peripherals often use different data formats and word lengths than the
computer to which they are attached.
+ Generic
Model
of an I/O
Module

Why an IO module is
needed?
• Interface to the
processor and memory
via the system bus or
central switch

• Interface to one or more

peripheral devices by
tailored data links
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7.1- External Devices

 Provide a means of
 Three categories:
exchanging data between  Human readable
the external environment  Suitable for communicating with
and the computer the computer user
 Video display terminals (VDTs),
 Attach to the computer by a printers
link to an I/O module
 Machine readable
 The link is used to exchange  Suitable for communicating with
control, status, and data equipment
between the I/O module and  Magnetic disk and tape systems,
the external device
sensors and actuators (thiết bị
khởi phát)
 peripheral device
 An external device
 Communication
connected to an I/O module  Suitable for communicating with
remote devices such as a
terminal, a machine readable
device, or another computer
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External
Device
Block
Diagram
bộ chuyển đổi
+ Keyboard/ Most common means of
computer/user interaction

Monitor
International Reference
User provides input through
the keyboard
Alphabet (IRA) The monitor displays data
provided by the computer
 Basic unit of exchange is the
character Keyboard Codes
 Associated with each character is a  When the user depresses a key it
code generates an electronic signal that is
 Each character in this code is interpreted by the transducer in the
represented by a unique 7-bit binary keyboard and translated into the bit
code pattern of the corresponding IRA
 128 different characters can be code
represented
 This bit pattern is transmitted to the
 Characters are of two types: I/O module in the computer
 Printable  On output, IRA code characters are
 Alphabetic, numeric, and special transmitted to an external device
characters that can be printed on from the I/O module
paper or displayed on a screen
 Control  The transducer interprets the code
 Have to do with controlling the and sends the required electronic
printing or displaying of characters signals to the output device either to
 Example is carriage return display the indicated character or
7.2-I/O Modules Control and timing
• Coordinates the flow of
Module Functions traffic between internal
resources and external
devices

Processor
Error detection communication
• Detects and reports • Involves command
transmission errors decoding, data, status
reporting, address
The major recognition
functions for an I/O
module fall into the
following
categories:

Data buffering Device

• Performs the needed communication
buffering operation to • Involves commands,
balance device and status information, and
memory speeds data
I/O Module Structure

IO Module
+ 7.3- Programmed I/O
 Three techniques are possible for I/O operations:

 Programmed I/O
 Data are exchanged between the processor and the I/O module
 Processor executes a program that gives it direct control of the I/O
operation
 When the processor issues a command it must wait until the I/O operation
is complete
 If the processor is faster than the I/O module this is wasteful of processor
time
 Interrupt-driven I/O
 Processor issues an I/O command, continues to execute other instructions,
and is interrupted by the I/O module when the latter has completed its
work
 Direct memory access (DMA)
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I/O Commands
 There are four types of I/O commands that an I/O module may
receive when it is addressed by a processor:

1) Control
- used to activate a peripheral and tell it what to do

2) Test
- used to test various status conditions associated with an I/O
module and its peripherals

3) Read
- causes the I/O module to obtain an item of data from the
peripheral and place it in an internal buffer

4) Write
- causes the I/O module to take an item of data from the data
bus and subsequently transmit that data item to the
peripheral
Three
Techniques
for Input of
a
Block of
I/O Instructions
With programmed I/O there is a close correspondence between the I/O-
related instructions that the processor fetches from memory and the I/O
commands that the processor issues to an I/O module to execute the
instructions

Each I/O device connected through I/O modules is given a

unique identifier or address

The form of the

When the processor
issues an I/O
Memory-mapped I/O
instruction depends command, the
on the way in which command contains
external devices are the address of the
addressed desired device

Thus each I/O module There is a single address space for A single read line and a single write
must interpret the memory locations and I/O devices line are needed on the bus
address lines to
determine if the
command is for itself
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I/O Mapping Summary

 Memory mapped I/O

 Devices and memory share an address space
Memory and
 I/O looks just like memory read/write IO devices
 No special commands for I/O share a
 Large selection of memory access commands available
common
address bus

 Isolated I/O
2 different
 Separate address spaces
address buses
 Need I/O or memory select lines for Memory
and IO devices
 Special commands for I/O
 Limited set
Memory
Mapped
I/O

Isolated
I/O
Example

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7.4- Interrupt-Driven I/O
The problem with programmed I/O is that the
processor has to wait a long time for the I/O
module to be ready for either reception or
transmission of data

An alternative is for the processor to issue an I/O

command to a module and then go on to do
some other useful work

The I/O module will then interrupt the processor

to request service when it is ready to exchange
data with the processor

The processor executes the data transfer and

resumes its former processing
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Simple Interrupt
Processing
+ (1)
(2) (1)

(3) (2)

Changes
in Memory
and Registers
for an
Interrupt call
(4) (3)
Design Issues
• Because there
will be multiple
I/O modules how
does the
Two design processor
determine which
issues arise device issued
in the interrupt?
implementin • If multiple
g interrupt interrupts have
I/O: occurred how
does the
processor decide
which one to
process?
+ Device Identification
Four general categories of techniques are in
common use:
 Multiple interrupt lines
 Between the processor and the I/O modules
 Most straightforward approach to the problem
 Consequently even if multiple lines are used, it is likely that each line will have
multiple I/O modules attached to it
 Software poll
 When processor detects an interrupt it branches to an interrupt-service routine whose
job is to poll each I/O module to determine which module caused the interrupt
 Time consuming

 Daisy chain (hardware poll, vectored)

 The interrupt acknowledge line is daisy chained through the modules
 Vector – address of the I/O module or some other unique identifier
 Vectored interrupt – processor uses the vector as a pointer to the appropriate device-
service routine, avoiding the need to execute a general interrupt-service routine first
 Bus arbitration (vectored)
 An I/O module must first gain control of the bus before it can raise the interrupt
request line
 When the processor detects the interrupt it responds on the interrupt acknowledge
line
 Then the requesting module places its vector on the data lines
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Intel
82C59A
Interrupt
Controller
Intel 82C55A
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Programmable Peripheral Interface
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Keyboard/
Display
Interfaces to
82C55A
Drawbacks of Programmed and
Interrupt-Driven I/O

 Both forms of I/O suffer from two inherent

drawbacks:

1) The I/O transfer rate is limited by the

speed with which the processor can
test and service a device

2) The processor is tied up in managing

an I/O transfer; a number of
instructions must be executed for
each I/O transfer
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 When large volumes of data are to be moved a
more efficient technique is direct memory access
(DMA)
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7.5- Direct
Memory
Access
Typical DMA
Module Diagram
DMA Operation
Click icon to add picture
DMA

DMA

+ 7.12 shows where in the instruction cycle the processor may be suspended.
Figure
In each case, the processor is suspended just before it needs to use the bus.
The DMA module then transfers one word and returns control to the processor.
Note that this is not an interrupt; the processor does not save a context and do
something else. Rather, the processor pauses for one bus cycle. The overall effect
is to cause the processor to execute more slowly. Nevertheless, for a multiple-word
I/O transfer, DMA is far more efficient than interrupt-driven or programmed I/O.
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Alternative
DMA
Configuration
s
8237 DMA Usage of System Bus
8237 contains four DMA channels Data does not pass through an
• Programmed independently is not stored in DMA chip
• Any one active • DMA only between I/O port an
• Numbered 0, 1, 2, and 3 memory
Can do memory to memory via
• Not between
register two I/O ports or
two memory locations
Fly-By DMA Controller
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Table 7.2 – Intel 8237A Registers

E/D =
enable/disable
+ 7.6- IO Channels and
Processors
Evolution of the I/O Function
1. The CPU directly controls 4. The I/O module is given direct
a peripheral device. access to memory via DMA. It can
now move a block of data to or
2. A controller or I/O module from memory without involving
is added. The CPU uses the CPU, except at the beginning
programmed I/O without and end of the transfer.
interrupts.
5. The I/O module is enhanced to
3. Same configuration as in become a processor in its own
step 2 is used, but now right, with a specialized
instruction set tailored for I/O
interrupts are employed.
The CPU need not spend
6. The I/O module has a local
time waiting for an I/O
memory of its own and is, in fact,
operation to be
a computer in its own right. With
performed, thus
this architecture a large set of I/O
increasing efficiency.
devices can be controlled with
minimal CPU involvement.
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I/O
Channel
Architecture
+ Exercises

 7.1- List three broad classifications of external, or

peripheral, devices.
 7.2- What is the International Reference Alphabet?
 7.3- What are the major functions of an I/O module?
 7.4- List and briefly define three techniques for
performing I/O.
 7.5- What is the difference between memory-mapped
I/O and isolated I/O?
 7.6- When a device interrupt occurs, how does the
processor determine which device issued the interrupt?
 7.7- When a DMA module takes control of a bus, and
while it retains control of the bus, what does the
processor do?
+ Summary
Input/Output
Chapter 7
 Direct memory access
 External devices
 Drawbacks of programmed and
interrupt-driven I/O
 Keyboard/monitor  DMA function
 Disk drive  Intel 8237A DMA controller
 I/O modules
 Module function  I/O channels and processors
 I/O module structure  The evolution of the I/O function
 Programmed I/O  Characteristics of I/O channels
 Overview of programmed I/O
 I/O commands
 The external interface
 Types of interfaces
 I/O instructions
 Point-to-point and multipoint
 Interrupt-driven I/O configurations
 Interrupt processing  Thunderbolt
 Design issues  InfiniBand
 Intel 82C59A interrupt controller
 Intel 82C55A programmable