BCSE205L

Computer Architecture and Organization

Module 1 – Introduction to CAO

BCSE205L - Computer Architecture and Organization
•Course Objectives

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BCSE205L - Computer Architecture and
Organization
•Course Outcomes

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BCSE205L - Computer Architecture and
• Syllabus
Organization

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BCSE205L - Computer Architecture and
Organization
• Syllabus

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BCSE205L - Computer Architecture and
• Syllabus
Organization

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BCSE205L - Computer Architecture and
Organization
• Text and Reference Books

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Overview of Organization and Architecture
•Computer Architecture and Computer Organization are related but
distinct concepts in the field of computer science.
•Computer Architecture
• refers to the design of the internal workings of a computer system, including
the CPU, memory, and other hardware components.
• involves decisions about the organization of the hardware, such as the
instruction set architecture, the data path design, and the control unit design.
• is concerned with optimizing the performance of a computer system and
ensuring that it can execute instructions quickly and efficiently.
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Overview of Organization and Architecture
•Computer Architecture
• refers to those attributes of a system visible to a programmer.
• Architectural attributes includes
• Instruction set
• the number of bits used to represent various data types

(e.g., numbers, characters),

• I/O mechanisms and techniques
• Addressing memory
• Example: “Whether a computer will have a multiply

instruction?” - Architectural design issue. 10

Overview of Organization and Architecture
•Organizational attributes includes
• Hardware details transparent to the programmer
• Control signals
• Interfaces between the computer and peripherals
• Memory technology used

• Example: “Whether that multiply instruction will be

implemented by a special multiply unit or by a
mechanism that makes repeated use of the add unit of the
system" 13
Overview of Organization and Architecture
Computer Architecture Computer Organization

1. Architecture describes what the computer Organization describes how it does it.
does

Computer Architecture Computer Organization deals with

2. structural relationship.
deals with functional behavior of a
computer system.
3. it deals with high-level design issues. it deals with low-level design issues.

As a programmer, you can view The implementation of the architecture is

4. called organization.
architecture as a series of instructions,
addressing modes, and registers.
For designing a computer, its architecture For designing a computer, an organization is
5. is fixed first. decided after its architecture.

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Overview of Organization and Architecture
Computer Architecture Computer Organization
6. Computer Architecture is also called as Computer Organization is frequently
Instruction Set Architecture (ISA). called
as micro architecture.
Computer Architecture comprises
7. logical functions such as instruction Computer Organization consists of physical
sets, registers, data types and addressing units like circuit designs, peripherals and
modes. adders.

8. The different architectural categories CPU organization is classified into three

found in our computer systems are: categories based on the number of address
• Von-Neumann Architecture fields:
• Harvard Architecture • Organization of a single
Accumulator.
• Instruction Set Architecture
• Organization of general registers
• Micro-architecture
• Stack organization
• System Design

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Overview of Organization and Architecture
• Organizational decision may be based on
• the anticipated frequency of use of the multiply instruction
• the relative speed of the two approaches
• cost and physical size of a special multiply unit
•Many computer manufacturers offer a family of computer models,
all
with the same architecture but with differences in organization.
•Architecture – Long term (span for many years)
•Organization – Short term (changing with technology)
•Example - IBM System/370 architecture (1970)
• Customer with modest requirements – prefer Cheaper and slower model
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Functional Components of Computer
• Input Unit
• Output Unit
• Memory Unit
• Central Processing Unit (CPU)
• Arithmetic and Logic Unit (ALU)
• Control Unit
• Memory Registers
Functional components of a computer
•Basic functional units of a computer – Five functionally
independent
main parts. Arithmetic and logic
unit(ALU):
Input unit accepts • Performs the desired
•information:
Human operations on the input
• Electromechanical
operators, devices information as
• Other
(keyboard) determined
computers by instructions in the
memory

Control unit
Output unit sends coordinates
results of various actions
• Input,
processing: Stores
• To a monitor • Output
information • Processing
display, :
• To a printer • Instruction
s,
• Data
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Functional components of a computer
•Basic functional units of a computer – Five functionally
independent main parts.

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Functional components of a computer
• Input Unit :
• A computer accepts the information through input device.
• Input device writes data into the memory through the data path. Some of
the
common input devices are keyboard, mouse, joystick, scanner etc.
• Output Unit:
• The Output unit send the processed result to the user using output device.
• It reads the data from memory through data path.
• Some devices are monitor, printer etc.
Functional components of a computer
• Central Processing Unit (CPU) :
• Brain of the computer - control center of the computer.
• It first fetches instructions from memory and then interprets them so as to
know what is to be done.
• CPU executes or performs the required computation and then either stores the
output or displays on the output device
• Arithmetic and Logic Unit (ALU) :
• performs mathematical calculations and takes logical
decisions. Arithmetic
calculations include addition, subtraction, multiplication and division
Functional components of a computer
• Central Processing Unit (CPU) :
• Control Unit :
• coordinates and controls the data flow in and out of CPU and also controls
all the operations of ALU, memory registers and also input/output units.
• It is also responsible for carrying out all the instructions stored in the
program.
• It decodes the fetched instruction, interprets it and sends control signals to
input/output devices until the required operation is done properly by ALU
and memory.
Functional components of a computer
• Central Processing Unit (CPU) :
• Memory Registers :
• A register is a temporary unit of memory in the CPU. These are used to
store the data which is directly used by the processor.
• Registers can be of different sizes(16 bit, 32 bit, 64 bit and so on) and
each register inside the CPU has a specific function like storing data,
storing an instruction, storing address of a location in memory etc.
• The user registers can be used by an assembly language programmer for
storing
operands, intermediate results
Functional components of a computer
• Memory Unit (MU) :
• Memory unit stores instructions and data.
• Recall, data is represented as a series of bits.
• To store data, memory unit thus stores bits.
• Processor reads instructions and reads/writes data from/to the memory during
the execution of a program.
• In theory, instructions and data could be fetched one bit at a time.
• In practice, a group of bits is fetched at a time.
• Group of bits stored or retrieved at a time is termed as “word”
• Number of bits in a word is termed as the “word length” of a computer.
• In order to read/write to and from memory, a processor should know where to
look:
• “Address” is associated with each word location.

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Functional components of a computer
• Memory Unit (MU) :
• Processor reads/writes to/from memory based on the memory address:
• Access any word location in a short and fixed amount of time based on the
address.
• Random Access Memory (RAM) provides fixed access time independent
of the location of the word.
• Access time is known as “Memory Access Time”.
• Memory and processor have to “communicate” with each other in order
to read/write information.
• In order to reduce “communication time”, a small amount of RAM (known
as Cache) is tightly coupled with the processor.
• Modern computers have three to four levels of RAM units with different
speeds and sizes:
• Fastest, smallest known as Cache
• Slowest, largest known as Main memory. 26
Memory unit (contd..)
• Primary storage is insufficient to store large amounts of data and
programs.
• Primary storage can be added, but it is expensive.
• Store large amounts of data on secondary storage devices:
• Magnetic disks and tapes,
• Optical disks (CD-ROMS).
• Access to the data stored in secondary storage in slower, but take advantage of the
fact that some information may be accessed infrequently.
• Cost of a memory unit depends on its access time, lesser access time
implies higher cost.

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Information in a computer -- Instructions
• Instructions specify commands to:
• Transfer information within a computer (e.g., from memory to ALU)
• Transfer of information between the computer and I/O devices (e.g.,
from keyboard to computer, or computer to printer)
• Perform arithmetic and logic operations (e.g., Add two numbers,
Perform a logical AND).

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Information in a computer -- Instructions
• A sequence of instructions to perform a task is called a program,
which is stored in the memory.
• Processor fetches instructions that make up a program from the
memory and performs the operations stated in those instructions.
• What do the instructions operate upon?
-----Data

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Information in a computer -- Data
• Data are the “operands” upon which instructions operate.
• Data could be:
• Numbers,
• Encoded characters.
• Data, in a broad sense means any digital information.
• Computers use data that is encoded as a string of binary digits called bits.

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How are the functional units connected?
• For a computer to achieve its operation, the functional units need to communicate with
eac other.
• In order to communicate, they need to be connected.

Input Output Memory Processor

Bus

• Functional units may be connected by a group of parallel wires.

• The group of parallel wires is called a bus.
• Each wire in a bus can transfer one bit of information.
• The number of parallel wires in a bus is equal to the word length of a
computer
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Drawbacks of the Single Bus Structure
• The devices connected to a bus vary widely in their speed of operation
• Some devices are relatively slow, such as printer and keyboard
• Some devices are considerably fast, such as optical disks
• Memory and processor units operate are the fastest parts of a computer
• Efficient transfer mechanism thus is needed to cope with this problem
• A common approach is to include buffer registers with the devices to hold
the information during transfers
• An another approach is to use two-bus structure and an additional transfer
mechanism
• A high-performance bus, a low-performance, and a bridge for transferring
the data between the two buses - ARMA Bus belongs to this structure.
Basic Operational Concepts
•Activity in a computer is governed by instructions.
•To perform a task, an appropriate program consisting of a list
of instructions is stored in the memory.
•Individual instructions are brought from the memory into
the
processor, which executes the specified operations.
•Data to be used as operands are also stored in the memory.
•Typical Instruction - Add LOCA, R0
•What is the function of Add LOCA, R0 and How does it execute!!??
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Basic Operational Concepts
•Typical Instruction - Add LOCA, R0
• Add the operand at memory location LOCA to operand in a
the
register R0 in the processor.
• Place the sum into register R0.
• The original contents of LOCAare preserved.
• The original contents of R0 is overwritten.
The instruction combines a memory access
•Steps: operation with an ALU operation.
1. Instruction is fetched from the memory into the processor.
2. The operand at LOCA is fetched and added to the contents of
R0
3. The resulting sum is stored in register R0.
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Basic Operational Concepts
•Separate Memory Access and ALU Operation
• In many modern computers, those two types of operation are performed by separate
instructions – Performance reason.
• Same instruction can be realized by the following two instruction sequence.

Load LOCA, # Transfer content of LOCA to

R1 Add R1, R0 R1 # R0=R1+R0
•Here the content of R1 and R0 destroyed & LOCAcontent is preserved.

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Basic Operational Concepts
•Connection between the processor and the memory
• Instruction register (IR)
• Program counter (PC)
• Memory address register (MAR)
• Memory data register (MDR)
• General-purpose register (R0 – Rn-1) are used
to store temporary data during any
ongoing operation. Its content can be
accessed by assembly programming.

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Basic Operational Concepts
•In addition to ALU and CU circuitry, processor
has special purpose and general purpose
registers
•Instruction register (IR) - Holds the instruction
that is currently being executed.
•Program counter (PC) – Holds the memory
address of the next instruction to be fetched
and executed. During the execution
of an instruction, the content of the PC
are updated to the address of the next
instruction to be executed.
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Basic Operational Concepts
•To facilitate the communication with memory and
processor
•Memory address register (MAR) – Holds the
address of the location to be accessed.
•Memory data register (MDR) – Contains the
data to be written into or read out
of the addressed location

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Basic Operational Concepts
Steps to Fetch Instruction from memory
1. Program - stored in memory through input unit
2. PC is set to point to the first instruction (holds
the address of the first instruction)
3. The contents of PC are transferred to MAR and
Read
control signal is sent to the memory
4. The instruction in the corresponding address (MAR)
is fetched from memory and loaded into MDR.
5. The contents of MDR are transferred to IR
6. Instruction - ready for execution
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Basic Operational Concepts
Steps to Fetch Data
• If operand is in memory, the corresponding address
should be sent to MAR – initiating Read
Cycle.
• Data fetched from memory and stored in MDR ,
then to
ALU
• Perform operation in ALU
• Store the result back in the memory
• To general-purpose register
• To memory (address to MAR, result to MDR
– Write in memory in specified 41
Basic Operational Concepts
•Interrupt – It is a request from an I/O device for the service by the processor
1. Normal execution of programs may be preempted if some device requires urgent
servicing.
2. The normal execution of the current program must be interrupted – the
device raises an interrupt signal.
3. Processor provide requested service by executing an Interrupt-service routine (ISR).
4. Current system information backup and restore (PC, general-purpose registers,
control information, specific information)
5. When ISR is completed, program execution is continued.

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Registers and Register Files
Registers:
• To speed up the processor operations, the processor includes some internal
memory
storage locations called registers.
• Memory hierarchy
1. Registers
2. Cache memory
3. Main memory
4. Secondary memory
• At higher level of hierarchy, memory is faster, more expensive.
• Registers are top level of hierarchy. 43
Registers and Register Files
Registers:
• Registers are temporary storage locations inside the processor circuit that hold data and
addresses.
• Some registers are used internally (by processor only) and cannot be accessed outside
the processor, while others are user-accessible.
• Most modern processor architectures include both types of registers
• Internal registers include the program counter (PC), instruction register (IR), memory
data register (MDR), and memory address register (MAR)
• The storage time of internal registers is extremely temporary, as they often hold data
for less than a millisecond
• The register file is the component that contains all the general purpose registers of 44
the
processor.
Registers – User Visible Registers
• Register - Two roles
• User visible registers – referenced by machine instruction – visible to the users
• Control and Status registers – employed to control the operation – Not visible to
the users
• User-Visible Registers
• General Purpose Registers
• Data Registers
• Address Registers
• Condition Codes Registers

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Registers – User Visible Registers
• General Purpose
Registers Add R1, R0
• True GP Registers
• Registers that can contain the operand for any Opcode.
• Restricted / Dedicated GP Registers
• Used for specific operations like floating point and stack operations
(dedicated registers).
• Data Registers - Used only to hold data and cannot be employed in the calculation
of an operand address.
• Accumulators (AC) - temporary storage location which holds intermediate
value in
arithmetic and logic operation results.
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Registers – User Visible Registers
• Address Registers – devoted for particular addressing mode.
• Segment registers - holds the address of the base segment.
• Index registers – used for indexed addressing and may be auto-indexed (increment).
• Stack pointer (SP) – points to the top of the stack.
• Condition Codes (Flag) Registers
• FLAG register is the status register that contains the current state of the processor (reflects
the result of arithmetic operation).
• Machine instructions allow these bits to be read by implicit reference (No explicit call
needed).
• Programmers cannot alter them.
• registers,
Example:to Inbe
some machines,
restored on sub-routine calls will result in automatic saving of all user
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Registers – User Visible Registers
• Condition Codes (Flag) Registers
• CCR contains five flag bits – set by CPU Hardware (ALU)– to hold information
about the result of an arithmetic or logical operation instruction that has just been
executed.
• Flag Bits:
• Carry C: Set to 1 if an add operation produces a carry or a subtract
operation produces a borrow; otherwise cleared to 0.
• Overflow V: Useful only during operations on signed integers.
• Zero Z: Set to 1 if the result is 0, otherwise cleared to 0.
• Negate N: Meaningful only in signed number operations. Set to 1 if a
negative result is produced.
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• Extend X: Functions as a carry for multiple precision arithmetic operations.
Registers – Control and Status registers
• Control and Status Registers
• Not visible to the user, May be visible in a control or operating system
mode (supervisory mode).
• Program counter (PC) holds the address of the instruction that should
be executed next.
• Instruction register(IR) holds the actual instruction to be executed.
• Memory Address Register (MAR) connects to address bus
• Memory Buffer Register (MBR) connects to data bus, feeds other registers.

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Example of Register Organizations

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Register Files
• A register file is an array of processor registers (Array of GP registres) in a
CPU. Dedicated read and write
ports
• Implemented by way of fast static RAMs with multiple ports.
• Ordinary multi-ported SRAMs will usually read and write through the same Dedicated write
• Example: Register file port
ports.
with
3 access ports
Dedicated read
ports

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Register Files
• Example: Register file with 3 access ports – Logic
Diagram

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Register Files
• Example: Register file with 3 access ports – Logic
Diagram

01

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Register Files
• Example: Register file with 3 access ports – Logic
Diagram

0101
0101
0101

01
0101
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Register Files
• Example: Register file with 3 access ports – Logic
Diagram

0101
0101
0101

01 10
0101
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Register Files
• Example: Register file with 3 access ports – Logic
Diagram

0110 0101
0110 0110
0101
0101 0110

01 10
0101 0110
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Given to ALU
Register Files
• Example: Register file with 3 access ports – Logic
Diagram

11

0110 0101
0110 0110
0101
0101 0110

01 10
0101 0110
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Register Files
• Example: Register file with 3 access ports – Logic
Diagram
1011 (from ALU)
11
1011
1011

0110 0101
0110 0110
0101
0101 0110

01 10
0101 0110
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Interconnection of Components - Bus Structures
• All five functional units must be connected
in some way to form an
operational system.
• There are many ways to connect different parts
inside a computer together.
• Bus
• Agroup of lines that serves as a connecting
path for several devices.
• Group of conducting lines that carries
data, address and control signals.
• Data Bus, Address Bus, Control Bus

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Interconnection of Components - Bus Structures
• The simplest way to interconnect
functional units is to use single
bus.
• It can support only one transfer at a
time.
• Only two units can actively use the bus
at any given time.
• Advantages: Simple, low cost,
flexibility for attaching peripheral
devices.

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Interconnection of Components - Bus Structures
• Multiple Bus structure achieve more
concurrency in operations by allowing two
or more transfers to be carried out at the
same time.
• It provides better performance at an
increased cost and complexity.

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Interconnection of Components - Bus Structures
• Speed Issues
•Different devices have different transfer/operate speed.
•If the speed of bus is bounded by the slowest device connected to it, the
efficiency will be very low.
•How to solve this?
•A common approach – Use buffer registers.
•Buffer registers are used to prevent a high speed processor from
being
locked to a slow I/O device during a sequence of data transfer.
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Instruction Formats

• In designing an instruction set, consideration is given to

•Instruction length – whether short, long or variable
•Number of Operands
•Number of addressable registers
•Memory Organization – byte addressable or Word addressable
•Addressing Modes – direct, indirect or indexed
Byte Ordering (Big Endian and Little Endian Formats)
Terminologies
• Bit - the smallest piece of information
- represents a digit of the binary numeral system
• Byte - A string of 8 bits
• Two ways to store a string of data (Bytes) in computers:
• Big Endian
• Little Endian
• Least Significant Byte (LSB) is the right-most bit in a string - because it has the
least effect on the value of the binary number.
• Most Significant Byte (MSB) - the left-most byte that carries the greatest
numerical value.
Big Endian and Little Endian Formats
• In Big Endian, the MSB of the data is placed at the
byte with the lowest address. (First byte stored in the memory
first)

•In Little Endian, the LSB of the data is placed at the

byte with the lowest address. (Last byte stored in the
Byte Ordering (Big Endian and Little Endian Formats)
• Big Endian - the most common format in data networking (TCP, UPD, IPv4 and IPv6
are using Big endian order to transmit data)
• Little Endian - on microprocessors
CPU Organization
•Classified on the basis of the number of address involves a special
register called the
fields accumulator.

multiple registers
used for the
computation
purpose

work on stack basis

operation due to
which it does not
contain any address
field
Comparison of Architectures
Instruction Formats
•Three-Address Instructions First operand - Destination

•ADD R1, R2, R3 R1 ← [R2] +

[R3]
•Two-Address Instructions
•ADDR1, R2 R1 ← [R1] + [R2]
•ADDM AC ← [AC] +
•One-Address Instructions
•Zero-Address Instructions M[AR]
•ADD TOS ← [TOS[ + [TOS –
•RISC Instructions 1]
•Lots of registers. Memory is restricted to Load & Store

Opcode Operand(s) or
Address(es)
Stack Architecture
Stack Architecture
Instruction Formats
Example: Evaluate (A+B) *
(C+D) CPU Organization :
• Three-Address General Register
1. ADD R1, A, B; R1 ← M[A] + M[B]
2. ADD R2, C, D; R2 ← M[C] + M[D];
3. MUL X, R1, R2; M[X] ← R1  R2

LOAD, STORE, MOV instructions - Not allowed

Instruction Formats
Example: Evaluate (A+B) *
(C+D) CPU Organization :
• Two-Address General Register
1. MOV R1, A ; R1 ← M[A] MOV – Loads
the Data from
2. ADD R1, B ; R1 ← R1 + M[B]
Memory to
3. MOV R2, C ; (Except Accumulator & MQ)
4. ADD R2, D ; R2 ← R2 + M[D] &
5. MUL R1, R2 ; R1 ← R1  R2 Viceversa
6. MOV X, R1 ; M[X] ← R1
Only MOV instruction allowed
LOAD, STORE operations – Not allowed
Instruction Formats
Example: Evaluate (A+B) *
(C+D) CPU Organization :
• One - A
Address Accumulator
1. LOAD AC ← M[A]
2. ADD B AC ← AC + LOAD – Loads the
3. STORE T M[B] M[T] ← Data from Memory to
4. LOAD C Accumulator
AC
STORE – Stores the
AC ← M[C] data from
5. ADD D AC ← AC + M[D]
Accumulator to
6. MUL T AC ← AC  M[T] Memory Location
7. STORE X M[X] ← AC
MOV instruction – Not allowed
Only LOAD, STORE operations allowed
Instruction Formats
Example: Evaluate (A+B) * (C+D)
• Zero - Address CPU Organization :
1. PUSH A; TOS ← A Stack
2. PUSH B; TOS ← B
3. ADD; TOS ← (A + B)
4. PUSH C; TOS ← C
5. PUSH D; TOS ← D
6. ADD; TOS ← (C + D)
7. MUL; TOS ← (C+D)(A+B)
8. POP X; M[X] ← TOS
Disadvantages of Addresses
choice of instruction format - depends on the specific
requirements of the computer architecture and the trade-
• Zero-address offs between code size, execution time, and flexibility.
instructions
• They can be limited in their functionality and do not allow for much flexibility
in terms of addressing modes or operand types.
• One-address instructions
• They can be slower to execute since they require operand fetching and
addressing.
• Two-address instructions
• They require more memory space than one-address instructions and can be
slower to execute since they require operand fetching and addressing.
• Three-address instructions
• They require even more memory space than two-address instructions and can
Example Instructions
Example Instructions
Example Instructions
• Write a program to evaluate the following arithmetic statement
X = [A (B + C) - D] / (E + F - G)
i) using a general register computer with three-address
and two- address instructions
ii) using an accumulator type computer with one-address
instructions
iii) using a stack organized computer with zero-address operation
instructions.
• Write a program to evaluate the arithmetic statement

a. Using general register with 3 address instructions

b. Using general register with 2 address instructions
Organization of Von Neumann Machine
(IAS Computer)
• Developed by John Von Neumann in 1940 at Princeton University.
• IAS - Institute for Advanced Studies.
• The task of entering and altering programs for ENIAC was extremely tedious
• ENIAC - (Electronic Numerical Integrator And Computer) - world's first general-
purpose electronic computer - the world's first programmable computer
• Disadvantage: programming the computer was a complex, manual process that
could take days.

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Organization of Von Neumann Machine
(IAS Computer)
• IAS computer is the father of all modern computers
• Primary concept - storing the program in memory.
• Stored program concept – program stored in the computer along with
any relevant data
• A stored program computer consists of a processing unit and an
attached memory system.
• The processing unit consists of data-path and control.
• Thedata-path contains registers to hold data and units,
functional such as arithmetic logic units 86
Structure of Von Neumann Machine
ALU - capable of operating on binary data (CA: central
main memory, - arithmetical)
stores both data
and
I/O equipment operated
instructions
by the control unit

Control unit - interprets the instructions in the memory and

causes them to be executed (CC: central control)
IAS Architecture
• Both data and instructions are stored in the same memory.

• Numbers are represented in binary form, and each instruction is a binary code.

• Memory Unit of the IAS consists of

• 1000 storage locations, called words
• Each word - 40 binary digits (bits) – 5 bytes
• Data Storage: Each number is represented by 1 sign bit + 39-bit value -- (Total
40 bits)
IAS Architecture
• Memory Unit of the IAS consists of
• Instruction Storage: A word may alternatively contain two 20-bit instructions
• Each instruction
• An Opcode (8-bits) - specifying the operation to be performed
• An Address (12-bits) - designating one of the words in memory (numbered from 0 to
999).
 If Address - Memory address – requires 12 bits
 If Address - Registers – 4 bits required – remaining 8 bits left unused

• Control Unit operates the IAS by fetching instructions from memory and executing them one at a
time.
Von Neumann Machine
(Expanded structure of IAS)
• Basic Elements
• Processor
• Memory
• Note:
• Each word – 40 bits
• Two instructions (each 20 bits)
stored
IAS Architecture
The control unit and the ALU contain storage locations - registers, defined
as follows:
•Memory buffer register (MBR): Contains a word to be stored in memory
or sent to the I/O unit, or is used to receive a word from memory or from
the I/O unit.
•Memory address register (MAR): Specifies the address in memory of the
word to be written from or read into the MBR.
•Instruction register (IR): Contains the 8-bit opcode instruction being
executed.
•Instruction buffer register (IBR): Employed to hold temporarily the
righthand instruction from a word in memory.
IAS Architecture
•Program counter (PC): Contains the address of the next instruction pair to
be fetched from memory.
•Accumulator (AC) and Multiplier Quotient (MQ): Employed to
hold temporarily operands and results of ALU operations.
For example, the result of multiplying two 40-bit numbers is an 80-bit
number – (40 bits are stored in the AC and the least significant in the
MQ).

Each word – 40 bits. Hence two registers MQ and AC are used for temporarily storing 80
bits. Then transferred to memory and stored in two consecutive 40 bit words in the memory…
Example
ACAC
=7 MQ
MEMORY 3
1. LOAD M(500), ADD M(501)
2. STOR M(500), (Other Ins)
.....
500. 3
501. 4
AMBRDODA=
MBR
L MD
M35B= R4
(500 0510)
PC 1 PC 2 0 STOR

MAR 500 MAR 501

MBR 3 MBR 4
IR LOAD M(500) IR ADD M(501)
IB5R
IBR ADD M(501) IBR ADD M(501) Add MPaCr
01 ←P
M =APC
1CR
AC 3 AC 7 LOAD M(500), ADD3 M(501)
=←P2C
4
PC 2 IR MAR
MA
MAR
MARadR
MAR ==
=dre1=s
500 STOR M(500),
5=500
s2 =0 5 1 0 (Other Ins)
MAR 500 ad1a ddrerses
address = 500

MBR 7 = s =2 1

IR STOR M(500)
IBR Other Ins
AC 7
Example
MEMORY
1. LOAD M(500), ADD M(501)
2. STOR M(500), (Other Ins)
.....
500. 3
501. 4

PC 1 PC 2
MAR 500 MAR 501
MBR 3 MBR 4
IR LOAD M(500) IR ADD M(501)
IBR ADD M(501) IBR ADD M(501)
AC 3 AC 7
PC 2
MAR 500 500 7
MBR 7
IR STOR M(500)
IBR Other Ins
AC 7
IAS Architecture
Register transfer operation for addition operation
1. LOAD M(500), ADD M(501) 2.STOR M(500), Other Instructions
Register transfer operations: (PC = 1)
MAR ← PC
MBR ← M[MAR]
IBR ← MBR[20:39]
IR ← MBR[0:7]
MAR ← MBR[8:19]
MBR ← M[MAR]
AC ← MBR
IR ← IBR[0:7]
MAR ← IBR[8:19]
PC PC+1
MBR ← M[MAR]
AC ← AC + MBR
IAS Instructions
The IAS computer had a total of 21 instructions grouped as follows:
• Data transfer: Move data between memory and ALU registers or between
two ALU registers.
•Unconditional branch: Normally, the control unit executes instructions in
Sequence from memory. This sequence can be changed by a branch
instruction, which facilitates repetitive operations.
•Conditional branch: The branch can be made dependent on a
condition, thus allowing decision points.
•Arithmetic: Operations performed by the ALU.
•Address modify: Permits addresses to be computed in the ALU and then
inserted into instructions stored in memory.
Problems
1. Write an appropriate assembly language code for the following operation and
interpret to Von Neumann IAS architecture. (Assume that data variables ‘Y’ & ‘Z’
available at memory locations 801 & 802 respectively. And X will be stored 803
onwards.)
Solution X=Y*Z
LOAD MQ, M(801) MQM[801] Note: The result of multiplying two 40-bit numbers is an
MUL M(802) ACMQ * M[802] 80-bit number;

STOR M(803) M[803]AC 40 bits are stored in the ACC and the least significant in the
MQ.
LOAD MQ ACMQ
STOR M(804) M[804]AC They are then transferred to Memory and stored in two
consecutive 40 bit word.
Problems
2.Write an ALP for the given expression using Von Neumann instruction set and
write the register transfer notation for the same. Assume that B,C and D are
available in the memory locations 450, 451 and 452 respectively.
A= ( B + C ) * D

Note: The result of multiplying two 40-bit

numbers is an 80-bit number;

40 MSB bits are stored in the ACC and the

remaining ‘n’ LSB least significant in the MQ.

They are then transferred to Memory and stored

in two consecutive 40 bit word.
Problems
3.Write an ALP for the given expression using Von Neumann instruction set and

write the register transfer notation for the same. Assume that A, B and X are available

in the memory locations 451, 450 and 452 respectively.

X = A+ B/2
Problems
4.Write an ALP for the given expression using Von Neumann
instruction set and
write the register transfer notation for the same. Assume that B, C, D and Z are
available

in the memory locations 800,801,802 and 803 respectively.

Z=(B-C)/D
LOAD M[800]
SUB
M[801]
DIV
M[802]
S
Problems
Disadvantages Of Von Neumann Architecture
• Shared bus can become a bottleneck if too many devices are connected
to it.
• This can lead to slow performance and reduced scalability.
• Additionally, the CPU can only execute one instruction at a time, which
can limit the overall speed of the system.
Harvard architecture
• Von Neumann architecture
• instructions, and data both are stored in the same memory.
• So same buses are used to fetch instructions and data.
• Hence, CPU cannot do both things together (read the instruction and read/write
data).
• Harvard Architecture - computer architecture that contains separate storage
and separate buses (signal path) for instruction and data.
• It was basically developed to overcome the bottleneck of Von
Neumann’s Architecture.
• Adv: having separate buses for instruction and data - the CPU
can access
instructions and read/write data at the same time.
Harvard architecture - Components
• CPU: The central processing unit performs all the calculations and
operations
required to execute instructions.
• Instruction memory: This memory holds instructions that the CPU needs to
execute. It is typically implemented as read-only memory (ROM) or
flash memory.
•Data memory: This memory holds data
that the CPU needs to perform computations.
It is typically implemented as RAM.
Harvard architecture - Components
• Input/output (I/O) devices: used to communicate with the outside world.
• System bus: The system bus is a collection of wires that connect the CPU, instruction
memory, data memory, and I/O devices - used to transmit data, instructions, and
control signals between these components.
Advantage of Harvard Architecture:
• Fast and efficient data access
• Better performance
• Suitable for real-time applications
• Security
Disadvantages of Harvard Architecture:
• Complexity
• Limited flexibility
• Higher memory requirements
Von Neumann Vs Harvard architecture
Von Neumann Vs Harvard architecture
Aspect Von Neumann Architecture Harvard Architecture

Memory Single memory for instructions and data Separate memory for instructions and data

CPU accesses instructions and data through a CPU accesses instruction and data memory spaces
Access
shared bus separately
Improved performance because the CPU can
Can become a bottleneck if too many devices are
Performance access both instruction and data memory
connected to the shared bus
simultaneously

Easier to modify programs as instructions and More difficult to modify programs that require the
Modification
data are stored in the same memory CPU to modify its own code

Easy to share data between different parts of a More difficult to share data between different
Data sharing
program parts of a program
Suitable for embedded systems where
Suitable for general-purpose computing where
Applications performance is critical and code is not frequently
flexibility is required
modified
Modified Harvard Architecture
• Very similar to Harvard architecture machine - CPU concurrent
access to two (or more) memory buses
• But
• Separate Data cache & Instruction cache – placed in CPU
• No strict separation between instruction and data memory
(Can
used be cache - separate – like Harvard
combinedly)
• While the CPU executes from cache, it acts as a pure Harvard
machine.
• When accessing backing memory, it acts like a von Neumann
machine. Memory - not separate– like Von Neumann
Harvard Vs Modified Harvard Architecture
RISC and CISC Architecture

RISC Characteristics
• RISC stands for Reduced Instruction • It has simpler instructions and
Set thus simple instruction decoding.
Computer Processor • More general-purpose registers.
• is a microprocessor architecture with a • The instruction takes one clock cycle in
simple collection and highly order to get executed.
customized set of instructions. • The instruction comes under the size of
• It is built to minimize the instruction a single word.
execution time by optimizing • Pipeline can be easily achieved.
and limiting the number of • Few data types.
instructions. • Simpler addressing modes
RISC Architecture
• Hardware of RISC architecture is designed to execute the
instruction quickly - because of the more precise and
smaller number of instructions and a large number of
CPU registers.
• Data path - store and manipulate data in a computer.
• responsible for managing data within the processor and
its movement between the processor and the memory.
• Cache - to reduce the access time to the main memory.
• Instruction cache - for retrieving and storing the data of
frequently used instructions - speeds up the process of
instruction execution.
• Data cache - provides storage for frequently used data
from the main memory.
RISC and CISC Architecture

CISC Characteristics
• Instructions are complex, and thus it has
• CISC Stands for Complex Instruction
complex instruction decoding.
Set Computer, developed by the
• Instructions may take more than one clock
Intel.
cycle in order to get executed.
• has a large collection of complex
• Instruction is larger than one-word size.
instructions that range from simple to
• Lesser general-purpose registers since the
very complex. operations get performed only in the memory.
• specialized in the assembly language • More data types.
level, which takes a long time to • Complex addressing modes.
CISC Architecture
• Cache memory - for holding both data and instructions.
• Thus, they share the same path for both instructions and
data.
• Instructions with variable length format - Thus, the number
of
clock cycles required to execute the instructions may be varied.
• Microprogram control unit - uses a series of microinstructions
of the microprogram stored in the “control memory” of
the microprogram control unit and generate the control
signals.
• Control units - access the control signals produced by the
microprogram control unit & operate the functioning
of processors hardware.
RISC and CISC Architecture
Example: A= B+C

RISC instruction CISC instruction

Load R2, B Move A, B

Load R3, C Add A, C
Add R4, R2, R3
Store R4, A
RISC and CISC Architecture
RISC and CISC Architecture
End of Module 1