24-Sep-20

PERIPHERAL ICS PPI 8255 – Programmable keyboard display –

Interface 8279 – Programmable interrupt controller 8259 –
Programmable DMA controller 8257 – USART 8251 – Basic Interfacing Concept
Programmable interval timer 8253. 8255 - PROGRAMMABLE
PERIPHERAL INTERFACE (PPI )
• Any application of Microprocessor Based system
The Intel 8255 (or i8255) Programmable Peripheral Interface Requires the transfer of data between external circuitry
8255A (PPI) chip is a peripheral chip, is used to give the CPU access to the Microprocessor and Microprocessor to the
to programmable parallel I/O. It can be programmable to External circuitry. User can give information (i.e. input)
transfer data under various conditions from simple I/O to to the Microprocessor using keyboard and user can see
interrupt I/O. it is flexible versatile and economical (when the result or output information from the
multiple I/O ports are required) but somewhat complex. It is Microprocessor with the help of display.
an important general purpose I/O device that can be used
• Hence interfacing is used to exchange information
with almost any microprocessor.
between two different applications/devices.

1 2 3

Memory Mapped I/O INTERFACING IN MEMORY MAPPED I/O

A15
A14 D0 D0
D7
• Device address is of 16 Bit. means A0 to A15 lines are A13 D7 PA0

used to generate device address. A12 A0 A0

A1
PA7
• MEMR and MEMW control signals are used to control A11 A1
8255
A10
read and write I/O operations. MEMR RD
PB0
A9
• Data transfer is between Any register and I/O device. A8 MEMW WR PB7
• Maximum number of I/O devices are 65536. A7 RESET OUT
RESET
PC0
• Decoding 16 bit address may requires more hardware. A6

• For e.g. MOV R M, ADD M,CMP M etc. A5

CS
PC7
A4
A3
A2

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I/O Mapped I/O INTERFACING IN I/O MAPPED I/O

8255 PPI
D0 D0 • The INTEL 8255 is a 40 pin IC having total 24 I/O pins.
D7
• Device address is of 8 Bit. means A0 to A7 or A8 to A15 D7 PA0 consisting of 3 numbers of 8 –bit parallel I/O ports
A7
lines are used to generate device address. A0 A0 PA7 (i.e. PORT A, PORT B,PORT C). The ports can be
A1
• IOR and IOW control signals are used to control read A6 A1
8255 programmed to function either as a input port or as
and write I/O operations. IOR RD PB0 a output port in different operating modes. It
A5
• Data transfer is between Accumulator and I/O device. IOW WR PB7
requires 4 internal addresses and has one logic LOW
• Maximum number of I/O devices are 256. A4 chip select pin. Its main functions are to interface
RESET OUT RESET
PC0 peripheral devices to the microprocessor. Basically
• Decoding 16 bit address may requires less hardware. A3
used for parallel data transfer. operates in mainly
• For e.g. IN, OUT etc. A2
PC7
two modes.
• (1) Bit Set Reset Mode (BSR Mode).
CS

• (2) I/O Mode.

7 8 9

Block Diagram of 8255 PPI

Function of Blocks Pin Diagram of 8255 PPI
POWER +5V
PA
SUPPLIES Ground GROUP A
GROUP A BLOCK FUNCTION OF BLOCK
PORT A (8)
CONTROL PA7-PA0
Bidirectional It is used to interface the internal data bus of 8255 to the system data bus by
Data Bus Data Bus Buffer reading and writing operations.
D7- D0 GROUP A PCU
DATA BUS It accepts the input from the address bus and issues commands to the individual
BUFFER PORT C Read/write group blocks. also issues appropriate enabling signals to access the required
8 Bit UPPER (4) PC7-PC4 Control logic data/control words/status words.
Internal
Data Bus
GROUP B PCL Port A
It can be programmed in three modes Mode0, Mode1 and Mode2.
8255 Pin
PORT C
LOWER (4) PC3-PC0
It can be programmed in three modes Mode0 and Mode1.
Diagram
READ/ Port B
RD
WR WRITE
A0 CONTROL GROUP B PB
GROUP B
A1
LOGIC CONTROL It can be programmed for Bit Set/reset operation.
RESET PORT B (8)
PB7-PB0 Port C

cs

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Function of Pins Function of Pins Function of Pins

PIN FUNCTION OF PIN
PIN FUNCTION OF PIN PIN FUNCTION OF PIN

These are bidirectional, tri-state data bus lines are connected to the system data bus. They A0-A1 The selection of input port and control word register is done by using A0 and A1 pins In
are used to transfer data and control word from microprocessor (8085) to 8255 or receive These are 8 bit bidirectional I/O pins divided into two groups PCL (PC3-PC) and PCU (PC7-
conjunction with RD and WR pins.
D0-D7 (Data Bus) data or status word from 8255 to the 8085. PC4).these groups can individually transfer data in or out when programmed for simple I/O,
PC0-PC7 and used as handshake signals when programmed for handshake or
(Port C) bidirectional modes. A1 A0 RD WR CS Operations

0 0 0 1 0 PORT A TO DATA BUS

These are 8 Bit bidirectional I/O pins used to send data to output device and to receive data 0 1 0 1 0 PORT B TO DATA BUS
from input device. It functions as an 8 Bit data output latch/buffer when used in output When this pin is low, the CPU can read data in the ports or the status word through the data
PA0-PA7 (Port A) mode and as an 8 Bit data input latch/buffer when used in input mode. RD bus buffer. 1 0 0 1 0 PORT C TO DATA BUS

0 0 1 0 0 DATA BUS TO PORT A

When this pin is low, the CPU can write data on the ports or in the control register through
WR the data bus buffer. 0 1 1 0 0 DATA BUS TO PORT B

These are 8 Bit bidirectional I/O pins used to send data to output device and to receive data 1 0 1 0 0 DATA BUS TO PORT C
from input device. It functions as an 8 Bit data output latch/buffer when used in output This pin can be enabled for data transfer operation between the CPU and 8255.
PB0-PB7 (Port B) mode and as an 8 Bit data input latch/buffer when used in input mode. CS 1 1 1 0 0 DATA BUS TO CONTROL REGISTER

x x x x 1 DATA BUS TRI STATED

This pin is used to reset 8255.i.e control register gets cleared and all the ports are set to the
RESET input mode. 1 1 0 1 0 ILLEGAL CONDITION

x x 1 1 0 DATA BUS TRI STATED

13 14 15

Operating Modes Of 8255 MODE 0 MODE 1

• In this mode, the ports can be used for simple input/output operations • When we wish to use port A or port B for handshake (strobed) input or
• There are two main operational modes of 8255: without handshaking. output operation, we initialize that port in mode 1.
(1) Input/output mode, • If both port A and B are initialized in mode 0, the two halves of port C can • For port B in this mode (irrespective of whether is acting as an input port
(2) Bit set/reset mode (BSR Mode). be either used together as an additional 8-bit port, or they can be used as or output port), PC0, PC1 and PC2 pins function as handshake lines.
individual 4-bit ports.
• Since the two halves of port C are independent, they may be used such that
I/O mode again classified into three types
one-half is initialized as an input port while the other half is initialized as an
• (1) Mode 0, output port. The mode 1 has following features:
• (2) Mode 1, • Two ports i.e. port A and B can be use as 8-bit i/o port.
• (3) Mode 2. The mode 0 has following features: • Each port uses three lines of port c as handshake signal and remaining two
signals can be function as i/o port.
• Interrupt logic is supported.
• O/p are latched.
• Input and Output data are latched.
• I/p are buffered not latched.
• Port do not have handshake or interrupt capability.

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Control Word Format in I/O Mode

MODE 2 0 D6 D5 D4 D3 D2 D1 D0 GROUP B
PORT C (LOWER) 1=I/P,
• Only group A can be initialized in this mode. 0=O/P

PORT B
• Port A can be used for bidirectional handshake data 1=I/P, 0=O/P

transfer. This means that data can be input or output on MODE SELECTION
0 = MODE 0

the same eight lines (PA0 - PA7). 1 = MODE 1

• Pins PC3 - PC7 are used as handshake lines for port A.

• The remaining pins of port C (PC0 - PC2) can be used as GROUP A
PORT C (UPPER) 1=I/P,
input/output lines if group B is initialized in mode 0. 0=O/P

• In this mode, the 8255 may be used to extend the system

PORT A
1=I/P, 0=O/P

bus to a slave microprocessor. MODE SELECTION

00 = MODE 0
01 = MODE 1
1X = MODE 2
MODE SET FLAG
1 = ACTIVE

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Control Word Format in BSR Mode

0 D6 D5 D4 D3 D2 D1 D0
BIT SET/RESET
1 = SET
2 = RESET

DON’T CARE

BIT SELECT

0 1 2 3 4 5 6 7

0 1 0 1 0 1 0 1 B0

0 0 1 1 0 0 1 1 B1

0 0 0 0 1 1 1 1 B2

BIT SET/RESET FLAG

0 = ACTIVE

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24-Sep-20

Write a program to initialize 8255 in the configuration

Write a program to initialize 8255 in the configuration
below.(assume address of the CW register as 83H). below.(assume address of the CW register as 23H).
(1) Port A: simple input (2) Port B: simple output (1) Port A: output with handshake
(3) Port CL: output (4)Port CU: input (2) Port B: input with handshake
(3) Port CL: output (4)Port CU: input
• Solution : • Solution :

1 0 0 1 1 0 0 0

= 98H 1 0 1 0 1 1 1 0

= AEH
Program: Program:
MVI A,98H ; LOAD CONTROL WORD MVI A,AEH ; LOAD CONTROL WORD

OUT 83H ; SEND CONTROL WORD OUT 23H ; SEND CONTROL WORD

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Find the control word for the register arrangement Find the control word for the register arrangement 82C55A Programmable Peripheral
of the ports of intel 8255 for mode 0 operation. of the ports of intel 8255 for mode 0 operation. Interface (cont.)
• Port A: Output, Port B: Output, • Port A: Input, Port B: Input,
• Port CU: Output, Port CL: Output • Port CU: Input, Port CL: Input EXAMPLE:
What is the addresses of port A, port B, port C
of the 82C55A device?
Solution: Solution: Solution:
To access port A, A1 A0 = 00, A15 = A = 1, A =
14 13

1 0 0 0 0 0 0 0 1 0 0 1 1 0 1 1 A12 = … = A2 = 0, which gives the port A address

= 80H = 9BH as
1100 0000 0000 00002 = C000 16

Similarly, it can be determined that the address of

The control word register for the above ports of intel The control word register for the above ports of intel port B equals C001 , that of port C is C002 ,
16 16

8255 is 80H. 8255 is 9BH. and the address of the control register is C003 . 16

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24-Sep-20

8255 MODE INSTRUCTION FORMAT

82C55A Programmable Peripheral
BSR Mode Interface (cont.)
PORT C LOWER)
1- Input
0- Output D3 D2 D1 Selected Bits of PORT C Mode 0 – Simple I/O operation

0 0 0 C0
0 0 1 C1
0 1 0 C2
Mode select
0 - Mode 0 0 1 1 C3
1 – Mode 1

1 0 0 C4
PORT C (UPPER) 1 0 1 C5
1- Input
0- Output
1 1 0 C6 Mode 0 port pin functions
1 1 1 C7

31 32 33

82C55A Programmable Peripheral

Interface (cont.)

Mode 0 control words and corresponding input/output configurations

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24-Sep-20

82C55A Programmable Peripheral 82C55A Programmable Peripheral

Interface (cont.) Interface (cont.)
EXAMPLE: The next for bits configure the upper part of
What is the mode and I/O configuration for port C and port A:
ports A, B, and C of an 82C55A after its control D3 = 0 Upper four bits of port C are outputs.
register is loaded with 8216? D4 = 0 Port A is an output port.
Solution: D6 D5 = 00 Mode 0 for both port A and the
Expressing the control register contents in binary
upper four bits of port C
form, we get
D 7D6 D5 D4 D3 D2 D1 D0 = 100000102
Since D7 is 1, the modes of operation of the ports
are selected by the control word.
D0 = 0 Lower four bits of port C are outputs.
D1 = 1 Port B is an input port.
D2 = 0 Mode 0 for both port B and the lower four bits of
port C.

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82C55A Programmable Peripheral 82C55A Programmable Peripheral 82C55A Programmable Peripheral

Interface (cont.) Interface (cont.) Interface (cont.)
Mode 1 – Strobed I/O Mode 1 – Strobed I/O Mode 1 – Strobed I/O
In mode 1, the A and B ports are configured as
two independent byte-wide I/O ports, each of
which has a 4-bit control/data port associated
with it.
The control/data ports are formed from the lower and
upper nibbles of port C, respectively
In mode 1, data applied to an input port must be
strobed in with a signal produced in external
hardware
An output port in mode 1 is provided with
handshake signals that indicate when new data
Mode 1 port pin functions
are available at its outputs and when an external Mode 1, port A output and input configuration
device has read these values

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24-Sep-20

82C55A Programmable Peripheral 82C55A Programmable Peripheral 82C55A Programmable Peripheral

Interface (cont.) Interface (cont.) Interface (cont.)
EXAMPLE: SOLUTION:
The following figures show how port B can be As STB Bis pulsed, the byte of data at PB 7
configured for mode 1 operation. Describe through PB0 is latched into the port B register.
what happens in the left figure when the This causes the IBF output
B
to switch to 1. Since
STB B input is pulsed to logic 0. Assume that INTE is 1, INTR switches to logic 1.
B B
INTE B is already set to 1.

Mode 1, port A input and output timing diagram

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82C55A Programmable Peripheral 82C55A Programmable Peripheral 82C55A Programmable Peripheral

Interface (cont.) Interface (cont.) Interface (cont.)
Mode 2 – Strobed Mode 2 – Strobed bidirectional I/O Mode 2 – Strobed bidirectional I/O
bidirectional I/O

Mode 2 port pin functions

Mode 2 input/output configuration Mode 2 bit set/reset format

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82C55A Programmable Peripheral

Interface (cont.) 82C55A Programmable Peripheral 82C55A Programmable Peripheral
Interface Interface
EXAMPLE Mixed modes EXAMPLE:
The interrupt-control flag INTEA for output port A in mode What control word must be written into the
control register of the 82C55A such that port A is
1 is controlled by PC6 . Using the set/reset feature of the configured for bidirectional operation and port B
82C55A, what command code must be written to the is set up with mode 1 outputs?
control register of the 82C55A to set it to enable the Solution:
control flag?
To configure the operating mode of the ports of
Solution: the 82C55A, D7 must be 1.
To use the set/reset feature, D7 must be logic 0. Moreover, Port A is set up for bidirectional operation by
INTEA is to be set; therefore, D0 must be logic 1. Finally, to
making D6 logic 1.
In this case, D 5 through D 3 are don’t-care states:
select PC 6, the code at bits D3 D2 D1 must be 110. The rest of
the bits are don’t-care states. This gives us the control D 5D 4D3 = XXX2
word Mode 1 is selected for port B by logic 1 in D 2and
D 7D6 D5 D4 D3 D2 D1 D0 = 0XXX11012
output operation by logic 0 in D 1.
D0 is a don’t-care state
Replacing the don’t-care states with the 0 logic level, we
DD7 D D 4D 3D 2 D1 D0 = 11XXX10X2 = 110001002 =
get 6 5
Combined mode 2 and mode 0 (input) control word and I/O configuration C416
D 7D6 D5 D4 D3 D2 D1 D0 = 000011012 = 0D16

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82C55A Programmable Peripheral 82C55A Programmable Peripheral 82C55A Programmable Peripheral

Interface Interface Interface
Mixed modes EXAMPLE When the 82C55A is configured in mode 1 or
Write the sequence of instructions needed to load mode 2 operations, most of the pins of port C
the control register of an 82C55A with the control
word formed in the previous example. Assume perform I/O control functions.
that the control register of the 82C55A resides at
address 0F 16 of the I/O address space?
Solution:
First we must load AL with C4 . 16This is the value
of the control word that is to be written to the
control register at address 0F 16. The move
instruction used to load AL is
MOV AL, 0C4H
These data are output to the control register with
OUT instruction
OUT 0FH, AL Mode 1 status information for port C Mode 1 status information for port C
Because the I/O address of the control register is
Combined mode 2 and mode 1 (output) control word and I/O configuration less than FF 16, this instruction uses direct I/O.

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82C55A Implementation of Parallel 82C55A Implementation of Parallel 82C55A Implementation of Parallel

Input/Output Ports Input/Output Ports Input/Output Ports
EXAMPLE: EXAMPLE
What must be the address bus inputs of the Assume that in the previous figure, PPI 14 is
circuit in the previous figure if port C of PPI 14 is configured so that port A is an output port, both
to be accessed? ports B and C are input ports, and all three ports
Solution: are set up for mode 0 operation. Write a program
that will input that data at port B and C, find the
To enable PPI 14, the 74F138 must be enabled difference (port C) – (port B), and output this
for operation and its O7 output switched to logic difference to port A.
0. This requires enable input G2B = 0 and chip Solution:
select code CBA = 111. This in turn requires from
the bus that Port A address = 00111000 2= 38 16
A 0= 0 to enable 74F138 Similarly, Port B address = 3A ,16Port C address =
and A A5 A = 111 to select PPI 14 3C16 Therefore,
4 3

Port C of PPI 14 is selected with A 1A 0 = 10, IN AL, 3AH ; Read port B

MOV BL, AL ; Save data from port B
which from the bus requires that IN AL, 3CH ; Read port C
A A2 1= 10 SUB AL, BL ; Subtract B from C
The rest of the address bits are don’t-care OUT 38H, AL ; Write to port A
82C55A parallel I/O ports in an 8088-based microcomputer states: XXXXXXXXXX111100

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82C55A Implementation of Parallel Memory-Mapped Input/Output Memory-Mapped Input/Output

Input/Output Ports Ports Ports
The full 20-bit address is available for
addressing I/O.
Memory-mapped I/O devices can reside anywhere in
the 1Mbyte memory address space of the 8088.
During I/O operations, memory read and write
bus cycles are initiated instead of I/O bus
cycles.
Memory instructions, not input/output instructions, are
used to perform data transfer.

82C55A parallel I/O ports in an

8086-based microcomputer

Memory-mapped 82C55A parallel I/O ports in an 8088-

based microcomputer

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Memory-Mapped Input/Output Memory-Mapped Input/Output Memory-Mapped Input/Output

Ports Ports Ports
EXAMPLE: EXAMPLE: From the circuit diagram, the memory address of
Which I/O port in the previous figure is selected the control register for PPI 0 is found to be
for operation when the memory address output Write the sequence of instructions needed to
on the bus is 0040216? initialize the control register of PPI 0 in the circuit 00000000010000000110 2= 00406 16

Solution: of the previous figure so that port A is an output Since PPI 0 is memory mapped, the following
We begin by converting the address to binary port, ports B and C are input ports, and all three move instructions can be used to initialized the
form. This gives ports are configured for mode 0 operation. control register:
A 19
…A A
1 0 = 000000000100000000102 Solution: MOV AX, 0 ; Create data segment at
In this address, bits A 10= 1 and A 0= 0. 00000H
The control byte required to provide this
Therefore, the 74F138 address decoder is MOV DS, AX
enabled whenever IO/M = 0. configuration is:
MOV AL, 8BH ; Load AL with control byte
A 5A 4A 3 = 000
MOV [406H], AL ; Write control byte to PPI 0
This input code switches decoder output O to 0 control register
logic 0 and chip selects PPI 0 for operation.
The address bits applied to the port select inputs
of the PPI are A 2A1 = 01. These inputs cause port
B to be accessed. Thus, the address 0040216
selects port B on PPI 0 for memory-map I/O.

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Memory-Mapped Input/Output
Ports
EXAMPLE:
Assume that PPI 0 in the previous figure is configured
as described in the previous example. Write a program
that will input the contents of ports B and C, AND
them together, and output the results to port A.
Solution:
The addresses of the three I/O ports on PPI 0 are:
Port A = 00400 16Port B = 00402 16Port C = 00404 16
Now we set up a data segment at 00000 16and the
program is:
AND AX, 0 ; Create data segment at 00000H
MOV DS, AX
MOV BL, [402H] ; Read port B
MOV AL, [404H] ; Read port C
AND AL, BL ; AND data at port B and C
MOV [400H], AL ; Write to port A

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