MICROPROCESSORS & MICROCONTROLLERS

Module-1(Evolution of microprocessors):
8085 microprocessor (-Basic Architecture only). 8086 microprocessor – Architecture and signals, Physical Memory organization,
Minimum and maximum mode of 8086 system and timings. Comparison of 8086 and 8088.Machine language Instruction format .
Module-2 (Addressing modes and instructions):
Addressing Modes of 8086. Instruction set – data copy /transfer instructions, arithmetic instructions, logical instructions, string
manipulation instructions, branch instructions, unconditional and conditional branch instruction, flag manipulation and
processor control instructions. Assembler Directives and operators. Assembly Language Programming with 8086.
Module- 3 (Stack and interrupts):
Stack structure of 8086, programming using stack- Interrupts - Types of Interrupts and Interrupt Service Routine- Handling
Interrupts in 8086- Interrupt programming. - Programmable Interrupt Controller - 8259, Architecture (Just mention the control
word, no need to memorize the control word)- Interfacing Memory with 8086.
Module- 4 (Interfacing chips):
Programmable Peripheral Input/output port 8255 - Architecture and modes of operation Programmable interval timer 8254-
Architecture and modes of operation- DMA controller 8257 Architecture (Just mention the control word, no need to memorize
the control word of 8254 and 8257).
Module- 5 (Microcontrollers):
8051 Architecture- Register Organization- Memory and I/O addressing- Interrupts and Stack- 8051 Addressing Modes- Instruction
Set- data transfer instructions, arithmetic instructions, logical instructions, Boolean instructions, control transfer instructions-
Simple programs.

MODULE 4
8255 – Programmable Peripheral Interface
• The Intel 8255A is a general purpose programmable I/O device designed for use with Intel microprocessors.
• It consists of three 8-bit bidirectional I/O ports (24 I/O lines) that can be configured to meet different system I/O needs.
• The three ports are designated as PORT A, PORT B and PORT C.
Ports of 8255
• Port A contains one 8-bit output latch/buffer and one 8-bit input buffer.
• Port B is same as PORT A.
• However, PORT C is split into two parts- PORT C lower (PC3-PC0) and PORT C upper (PC7-PC4) by the control word.
• The four ports – two 8-bit PORTs and two 4-bit PORTs are divided in two groups for programming purpose
Group A (PORT A and upper PORT C)
Group B (PORT B and lower PORT C)
Modes of 8255 – It works in two modes:
1.Bit set reset (BSR) mode
2.Input/output (I/O) mode
• To know in which mode the interface is working we need to know the value of Control word.
• Control word is a part of control register in 8255 which specify an I/O function for each port.
• If the most significant bit of control word or D7 is 1 then 8255 works in I/O mode else, if its value is 0 it works in BSR mode.
1. BSR Mode – When MSB of the control register is zero (0), 8255 works in Bit Set Reset mode.in this only PC bit are used for set
and reset.
2. I/O Mode – When MSB of the control register is one (1), 8255 works in Input-Output mode.it is further divided into three
categories.
3. Mode 0 – In this mode all three ports (PA, PB, PC) can work as simple input function or output function also in this mode there
is no interrupt handling capabilities.
4. Mode 1 – In this either port A or port B can work and port C bits are used as Handshake signal before actual data transmission
plus it has interrupt handling capabilities.
5. Mode 2 – In this only port A works
and port B can work either in Mode 0 or
Mode 1 and the 6 bits of port C are used as
Handshake signal plus it also has to
interrupt handling capability.
Format of control word 8255 - BSR
Mode
Format of control word 8255 - IO Mode

Operating Modes of 8255
8255A has three different operating modes −
• Mode 0 − In this mode, Port A and B is used as two 8-bit ports and Port C as two 4-bit ports. Each port can be programmed in
either input mode or output mode where outputs are latched and inputs are not latched. Ports do not have interrupt capability.
• Mode 1 − In this mode, Port A and B is used as 8-bit I/O ports. They can be configured as either input or output ports. Each port
uses three lines from port C as handshake signals. Inputs and outputs are latched.
• Mode 2 − In this mode, Port A can be configured as the bidirectional port and Port B either in Mode 0 or Mode 1. Port A uses
five signals from Port C as handshake signals for data transfer. The remaining three signals from Port C can be used either as
simple I/O or as handshake for port B
ARCHITECTURE OF 8255

Functional Description:
This support chip is a general purpose I/O component to interface peripheral equipment to the microcomputer system bus. It is
programmed by the system software so that normally no external logic is necessary to interface peripheral devices or structures.
• Data Bus Buffer:
It is a tri-state 8-bit buffer used to interface the chip to the system data bus. Data is transmitted or received by the buffer upon
execution of input or output instructions by the CPU. Control words and status
information are also transferred through the data bus buffer.
•Read/Write and Logic Control:
The function of this block is to control the internal operation of the device and to
control the transfer of data and control or status words. It accepts inputs from the CPU
address and control buses and, in turn, issues command to both the control groups.
•CS (Chip Select):
A low on this input selects the chip and enables the communication between 8255A &
the CPU. It is connected to the decoded address, and A0 & A1 are connected to the
microprocessor address lines.
Their result depends on the following conditions 

• RESET
This is an active high signal. It clears the control register and sets all ports in the input mode.
• RD (Read):
A low on this input enables the 8255A to send the data or status information to the CPU on the data bus.
• WR (Write):
A low on this input pin enables the CPU to write data or control words into the 8255A.
• A1, A0 Port Select:
These input signals, in conjunction with the RD and WR inputs, control the selection of one of the three ports or the control word
registers. They are normally connected to the least significant bits of the address bus (A0 and A1).
A1 A0 RD WR CS Result
Input Operation
0 0 0 1 0
PORT A → Data Bus
0 1 0 1 0 PORT B → Data Bus
1 0 0 1 0 PORT C → Data Bus
Output Operation
0 0 1 0 0
Data Bus → PORT A
0 1 1 0 0 Data Bus → PORT A
1 0 1 0 0 Data Bus → PORT B
1 1 1 0 0 Data Bus → PORT D
To communicate with peripherals through 8255 three steps are necessary:
1.Determine the addresses of Port A, B, C and Control register according to Chip Select Logic and the Address lines A0 and A1.
2.Write a control word in control register.
3.Write I/O instructions to communicate with peripherals through port A, B, C.
The common applications of 8255 are:
• Traffic light control
• Generating square wave
• Interfacing with DC motors and stepper motors
DMA Controller 8257
• The 8257, on behalf of the devices, requests the CPU for bus access using local bus request input i.e., HOLD in minimum mode.
• In maximum mode of the microprocessor RQ/GT pin is used as bus request input.
• On receiving the HLDA signal (in minimum mode) or RQ/GT signal (in maximum mode) from the CPU, the requesting devices
gets the access of the bus.
• It completes the required number of DMA cycles for the data transfer and then hands over the control of the bus back to the
CPU
Architecture of 8257 
• The chip support four DMA
channels, i.e., four
peripheral devices can
independently request for
DMA data transfer through
these channels at a time
• Each of four channels of
8257 has a pair of two 16-bit
registers, viz. DMA address
register and terminal count
register.
• There are two common
registers for all the channels,
namely, mode set
register and status register.
• Thus, there are a total of
ten registers.
• The CPU selects one of
these ten registers using address lines A0-A3.
DMA Address Register
• Each DMA channel has one DMA address register
• The function of this register is to store the address of the starting memory location, which will be accessed by the DMA channel
Terminal Count Register
• Each of the four DMA channels of 8257 has one terminal count
register (TC).
• This 16-bit register is used for ascertaining that the data transfer
through a DMA channel cease or stops after the required number of
DMA cycles.
• The low order 14-bits of the terminal count register are
initialised with the binary equivalent of the number of required
DMA cycles minus one.
• The bits 14 and 15 of this register indicate the type of the DMA operation.
Mode Set Register
• The function of the mode set register is to
enable the DMA channels individually and
also to set the various modes of operation
• The DMA channel should not be enabled till
the DMA address register and the terminal
count register contains valid information
Data Bus Buffer
• The 8-bit tristate, bidirectional buffer
interfaces the internal bus of 8257 with the external system bus under the control of various control signals
Read/Write Logic
• In the slave mode, the read/write logic accepts the I/O Read or I/O Write signals, decodes the Ao-A3 lines and either writes the
contents of the data bus to the addressed internal register or reads the contents of the selected register
• In master mode, the read/write logic generates the IOR and IOW signals to control the data flow to or from the selected
peripheral.
Control Unit
•The control logic controls the sequences of operations and generates the required control signals like AEN, ADSTB, MEMR,
MEMW, TC and MARK along with the address lines A4-A7, in master mode.
Priority Resolver
•The priority resolver resolves the priority of the four DMA channels depending upon whether normal priority or rotating
priority is programmed.
PIN DIAGRAM 
Signal Description of
8257:
DRQ0-DRQ3
• These are the four
individual channel DMA
request inputs, used by
the
peripheral devices for
requesting the DMA
services.
• The DRQo has the
highest priority while
DRQ3 has the lowest
one, if the
fixed priority mode is
selected.
DACK0 - DACK3
• These are the active-
low DMA acknowledge
output lines which inform the requesting peripheral that the request has been honoured
Do-D7
• These are bidirectional, data lines used to interface the system bus with the internal data bus of 8257.
• These lines carry command words to 8257 and status word from 8257, in slave mode.
• When the 8257 is the bus master, it uses Do-D7 lines to send higher byte of the generated address to the latch
IOR
• This is an active-low bidirectional tristate line that acts as an input in the slave mode.
• In slave mode, this input signal is used by the CPU to read internal registers of 8257.
• In master mode, this signal is used to read data from a peripheral during a memory write cycle.
IOW
• This is an active low bidirectional tristate line.
• It acts as input in slave mode to load the contents of the data bus to the upper/lower byte of a 16-bit DMA address register or
terminal count register.
• In master mode, this signal is used to write data to a peripheral during a memory read cycle
CLK
• This is a clock frequency input required to derive basic system timings for the internal operation of 8257
RESET
• This active-high asynchronous input disables all the DMA channels by clearing the mode register and tri-states all the control
lines
A0-A3
• These are the four least significant address lines.
• In slave mode, they act as input which select one of the registers to be read or written.
• In the master mode, they are the four least significant memory address output lines generated by 8257.
A4-A7
• This is the higher nibble of the lower byte address generated by 8257 during the master mode of DMA operation.
READY
• This is an active-high asynchronous input used to stretch memory read and write cycles of 8257 by inserting wait states.
• This is used while interfacing slower peripherals
CS
• This is an active-low chip select line that enables the read/write operations from/to 8257, in slave mode.
• In the master mode, it is automatically disabled to prevent the chip from getting selected while performing the DMA operation
HRQ
• The hold request output requests the access of the system bus.
• In the non-cascaded 8257 systems, this is connected with HOLD pin of CPU
• In the cascade mode, this pin of a slave is connected with a DRQ input line of the master 8257, while that of the master is
connected with HOLD input of the CPU
HLDA
• The CPU drives this input to the DMA controller high, while granting the bus to the device.
• This pin is connected to the HLDA output of the CPU.
• This input, if high, indicates to the DMA controller that the bus has been granted to the requesting peripheral by the CPU.
MEMR
• This active –low memory read output is used to read data from the addressed memory locations during DMA read cycles.
MEMW
• This active-low output is used to write data to the addressed memory location during DMA write operation.
ADSTB
• This output from 8257 strobes the higher byte of the memory address generated by the DMA controller into the latches.
AEN
• This may be used to disable the system address and data bus
MARK
• The modulo 128-mark output indicates to the selected peripheral that the current DMA cycle is the 128th cycle since the
previous MARK output
• The mark will be activated after each 128 cycles or integral multiples of it from the beginning of the data block (the first DMA
cycle).
TC
• Terminal count output indicates to the currently selected peripherals that the present DMA cycle is the last for the previously
programmed data block.
Vcc • This is a +5v supply pin required for operation of the circuit.
GND • This is a return line for the supply (ground pin of the IC).

Intel 8253/8254 – Programmable Interval Timer

• It is always possible to generate accurate time delays using the microprocessor system by using software loop programs. But
that will waste the precious time of CPU.
• INTEL introduced the chips 8253/8254 which is a hardware solution for the problem of generating accurate time delays.
• Programmable interval timer/counter
• Has six modes of operation
• It has three independent 16-bit down counters.
• Operation
- A 16-bit count is loaded on the counter and on command it starts decrement
- When the count reaches zero it generates a pulse
Features of 8253 / 54
• It can handle inputs from DC to 10 MHz.
• 3 counters can be programmed for either binary or BCD count.
• To operate a counter, a 16-bit count is loaded in its register on command, it begins to decrement the count until it reaches 0. At
the end of the count, it generates a pulse that can be used to interrupt the CPU.
• It is compatible with almost all microprocessors.
• 8254 has a powerful command called READ BACK command, which allows the user to check the count value, the programmed
mode, the current mode, and the current status of the counter.
ARCHITECTURE 

Data Bus Buffer

• It is a tri-state, bi-directional, 8-bit buffer, which is used
to interface the 8253/54 to the system data bus. It has
three basic functions −
• Programming the modes of 8253/54.
• Loading the count registers.
• Reading the count values.

Read/Write Logic
• It includes 5 signals, i.e., RD, WR, CS, and the address
lines A0 & A1.
• In the peripheral I/O mode, the RD and WR signals are
connected to IOR and IOW, respectively. In the memory-
mapped I/O mode, these are connected to MEMR and
MEMW.
• Address lines A0 & A1 of the CPU are connected to lines A0 and A1 of the 8253/54, and CS is tied to a decoded address.
• The control word register and counters are selected according to the signals on lines A0 & A1.

Control Word Register

• This register is accessed when lines A0 & A1 are at logic 1.
• It is used to write a command word, which specifies the
counter to be used, its mode, and either a read or write
operation. Following table shows the result for various control
inputs. 

Counters
• Each counter consists of a single, 16 bit-down counter, which can be operated in either binary or BCD.
• Its input and output is configured by the selection of modes stored in the control word register.
• The programmer can read the contents of any of the three counters without disturbing the actual count in process.
• Counters are programmed by writing a Control Word and then an initial count.
• GATE=1 enables counting, GATE=0 disables counting.

Counter Latch Command

• It is written to the Control Word Register like a Control Word, but two bits (D5,D4) distinguish this command from a Control
Word.
• The selected Counter latches the count at the time the Counter Latch Command is received.
• The count is held in the latch until it is read by the CPU.
Read-Back Command (Available only for 8254)
• This command allows the user to check the count value, programmed Mode, and current states of the OUT pin, etc...
Intel 8253/54 - Operational Modes

Mode 0 ─ Interrupt on Terminal Count

• It is used to generate an interrupt to the microprocessor after a certain interval.
• Initially the output is low after the mode is set. The output remains LOW after the
count value is loaded into the counter.
• The process of decrementing the counter continues till the terminal count is reached,
i.e., the count become zero and the output goes HIGH and will remain high until it reloads a new count.
• The GATE signal is high for normal counting. When GATE goes low, counting is terminated and the current count is latched till
the GATE goes high again.

Mode 1 – Programmable One Shot

• It can be used as a mono stable multi-vibrator.
• The gate input is used as a trigger input in this mode.
• The output remains high until the count is loaded and a trigger is applied.
• In Mode 1, after sending the 0-to-1 pulse to GATE, OUT becomes low and stays low for a duration of count, then becomes high
and stays high until the GATE is triggered again

Mode 2 – Rate Generator

• The output is normally high after initialization.
• After loading the counter and triggering(gate=1) it, the output will be high till the last one period (i.e. The output will be high
for (N-1) clock pulses and then it will go low for one cycle of input clock and then return HIGH and the count value is
automatically reloaded into the counter
• If the gate is low, the output will be HIGH and no counting will be performed.

Mode 3 – Square Wave Generator

• This mode is similar to Mode 2 except the output remains low for half of the timer period and high for the other half of the
period.
• This is accomplished internally by decrementing the counter by two on the falling edge of each pulse
• When the count N loaded is EVEN, then for half of the count, the output remains high and for the remaining half it remains
low.
• If the loaded count value N is ODD, then for (N+1)/2 pulses the output remains high & for (N-1)/2 pulses it remains low

Mode 4 − Software Triggered Mode

• In this mode, the output will remain high until the timer has counted
to zero, at which point the
output will pulse low and then go high again.
• The count is latched when the GATE signal goes LOW.
• On the terminal count, the output goes low for one clock cycle then
goes HIGH. This low pulse can be used as a strobe.
• Here, the counter is not reloaded automatically. To repeat the strobe,
the count must be reloaded
• This is called software triggered strobe as the countdown is initiated by a program
Mode 5 – Hardware Triggered Mode
• This mode generates a strobe in response to an externally generated signal.
• This mode is similar to mode 4 except that the counting is initiated by a signal at the gate input, which means it is hardware
triggered instead of software triggered.
• After it is initialized, the output goes high.
• When the terminal count is reached, the output goes low for one clock cycle.