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Microprocessor 2

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48 views30 pages

Microprocessor 2

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Komal pandey
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Transmitter section: a © The transmitter section accepts parallel data from CPU and converts them into serial data. The transmitter section is double buffered, ic., it has a buffer register to hold an 8-bit parallel data and another register called output register to convert the parallel data into serial bits. * When output register is empty, the data is transferred from buffer to output register. Now the processor can again load another data in buffer register. * If buffer register is empty, then TxRDY goes high. * If output register is empty then TxEMPTY goes high © The clock signal, TxC (low) controls the rate at which the bits are transmitted by the USART. * The clock frequency can be 1,16 or 64 times the baud rate. Receiver Section: * The receiver section accepts serial data and converts them into parallel data. + The receiver section is double buffered, ic., it has an input register to receive serial data and convert to parallel, and a buffer register to hold the parallel data. + When the RxD line goes low, the control logic assumes it as a START bit, waits for half a bit time and samples the line again. * Ifthe line is still low, then the input register accepts the following bits, forms a charac- ter and loads it into the buffer register. * The CPU reads the parallel data from the buffer register. * When the input register loads a parallel data to buffer register, the RxRDY line goes high. * The clock signal RxC (low) controls the rate at which bits are received by the USART. * During asynchronous mode, the signal SYNDET/BRKDET will indicate the break in » the data transmission. * During synchronous mode, the signal SYNDET/BRKDET will indicate the reception of synchronous character. MODEM Control: ain is 8251 called a USAR? Define the mode word register a * The MODEM control unit allows to interface a MODEM to 8251A and to establish data communication through MODEM over telephone lines. « This unit takes care of handshake signals for MODEM interface. - [=] ronous mode. U USART: ‘ammable chip designed for sy It includes Read(The input port and an output are requir Gi) In data transmission, the MPU converts a Par! bits. (iii) In data reception, the MPU converts se! (iv) Data transfer is synchronized between the through time delays. * Since 8251 performs all the above functions on t Mode Word Register of 8251 allel word into a stream rial bits into parallel word, MPU and slow responding perip} the chip, it is called Us Dy | D5 00> 5 bits y 01 6 bite Parity Contot 10-7 bits "> iy 11 ebits ' Framing Control eager eRe E- Barea cone 11 EVEN panty 01 1 stop bit 10-5 1% stop bt 11.5 2600p bts & Fig. 9. 48911. Bxplain 8279 Programmable Keyboard/display i i i play interface with block diag oR Di aw and explain the block diagram of keyboard display controller 8279, >>two key lockout mode or >>N-key rollover, ~ In two key lockout mode if 2 keys are pressed InN key rollover mode, simultaneous keys an can also be set up so that no key is recongnized This has a FIFO RAM. The status logic RQ(interrupt request) signal when FIFO ig until only one key ig Keeps track ;Butlors: (RAM Status eee | pai os Lal ase 254 = Jt esa OUT Ay RY OUT, 8, a Ao Pugh, CMUSTB Fig. 11. 8279 Block Diagram DISPLAY SECTION: This section has 8 output lines divided into 2 groups of 4. A, —A, and B, —B,. These lines can be used in both ways, 8 lines or 2 sets of 4 lines. The display can be blanked using BD line. The section has 16x8 display RAM. SCAN SECTION: This section has scan counter and 4 scan lines. SL, ~ SL,. These 4 scan lines can be decoded using a 4 - 16 decoder to generate 16 lines for scanning. These 16 lines can be connected to rows of a matrix keyboard and digit drivers of multiplexed display. MPU INBTERFACE SECTION: This section has 8 bi-directional lines. DB, — DB,,. 1 ints rupt request line(IRQ). 6 lines for interfacing including buffer address lines A,. When A, is high - signals are interpreted as control word or status. When A, is low - signal is interpreted as data IRQ goes high whenever data is ready to be loaded into MPU. aso] 0! C Q12. Give the block diagram and features of 8259. Ans, Features: * 8 levels of interrupts. * Can be cascaded in master-slave configuration to handle 64 levels of inte * Internal priority resolver. __ * Fixed priority mode and rotating priority mode. . Beeridcally maskable interrupts.— — ye ‘apvancen M ncn 98 — uty} —re.rech)— (UN 086 mode, Provides Ini ion. LL inetruct a byte CA + In 8085 mode, provides number, i pit + Polled and vectored mode umber is Prot Starting address of ISR or vector * No clock required oe m £8259 internal block diagra i. sl roe = Data bus oa able. butter | Read/ We] we | No) toe Beer ssanas— Fig. 12. wv [e253] : Q.13. Explain the block diagram of 8253. Ans. Il examine the block diagram and next I'l explore the internal registers ar tl they are all identical. The block labeled data bus bi i i n to/from the microprocessor, and to the interna se cuties ee ding and the vriting eral 7, contains the programmed £oryln effect this register defines hig Each counter in the block diagram ha in and gate, are inputs, The third, labeled ounce nd depends on how the device i initialized gs on out PUt, The Counters: SRE: There are 3 counters ®t Of €ach othen controls thea oo 39 — [UTU]— [B.TECH — [UNTTAN]— ADVANCED MICROPROCESSORS & en.wikipedia org/wiki/DRAM> memory. The last counter (A1=1, A0=0) generates tones | PC speaker . Besides the counters, a typical Intel 8253 microchip also contains the following components: ote bas |-—cuxo or vo ae) ts 1 cone SED sito: Ky] KO] 70 >= oar cure ieort a —_+d la} w—a4 Foo | fl |-—cuxs ao——+| we ef [o— GATE 1 M+ booie 3) -— our ee ona |—caxe woes a o [oure VA Fig. 13. Block diagram of an 8253 programmable interval timer Data/Bus Buffer: This block contains the logic to buffer the data bus to/ pro- cessor, and i s. Ithas 8 input pins, usually labelled as D7..D0, where D7 is _ the MSB . Read/Write Logic: The Read/Write Logic block has 5 pins, which are listed below. Notice that /K denotes an active low signal. P/RD: read signal + TWR: write signal 4 ICS: chip select signal 4 AO, Al: address lines Operation mode of the PIT is changed by setting the above hardware signals. For example, to write to the Control Word Register, one needs to set /CS=0, /(RD=1, /WR=0, A1=A0=1. . Control Word Register ‘This register contains the programmed information which will be sent (by the microproces- sor ) to the device. It defines how the PIT logi- cally works. Each access to these ports takes about 1 pis. ‘i To initialize the counters, the microprocessor must write a control word (CW) in ter. This can be done by setting proper'values for the pins of the Read/Write Logi then by sending the control word to the Data/Bus Buffer block. Q.14, What are the operating modes of 8253? Miniatiione

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