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Peripheral Interfacing

The document provides an overview of various peripheral interfacing components, including the Intel 8254 programmable interval timer, the 8279 keyboard display interface, and the 8255 programmable interrupt controller. It details the architecture, functions, and operating modes of these components, highlighting their roles in facilitating communication between the CPU and external devices. Additionally, it discusses programming requirements and operational characteristics, emphasizing the flexibility and performance improvements offered by these interfacing devices.

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0% found this document useful (0 votes)
13 views21 pages

Peripheral Interfacing

The document provides an overview of various peripheral interfacing components, including the Intel 8254 programmable interval timer, the 8279 keyboard display interface, and the 8255 programmable interrupt controller. It details the architecture, functions, and operating modes of these components, highlighting their roles in facilitating communication between the CPU and external devices. Additionally, it discusses programming requirements and operational characteristics, emphasizing the flexibility and performance improvements offered by these interfacing devices.

Uploaded by

Sk Surya
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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UNIT-III

PERIPHERAL INTERFACING

1. With neat block diagram, explain the description and function of 8254.
 Intel 8254 is a programmable interval timer designed by intel is a
programmable external timer device built with an aim to resolve the time
control issues that occur in between various processes occurring within the
microprocessor. In order to communicate with the processor, it has a total of 8
data lines.
 There are overall 24 pin signals in which it operates and the power supply
provided to it is +5V.

 It consists of a total of 3 counters of 16-bit each and adequate programming is


performed so that each one operates properly in one of the six possible
modes.
 It has 2 inputs namely clock and gate while 1 output i.e., counter. The counter
operates in a way that initially a count value is stored in the count register and
at this time gate signal will be high and input is provided through clock input.
After each cycle of the clock input, the counter decrements the value by 1,
and output is obtained according to the mode of operation.
 Overall 8 data lines are there through which 8254 communicates with the
processor. Through the data bus buffer, registers store the control words and
count values.
 The read and write operations are performed through control signals RD’ and
WR’. Out of the four internal devices i.e., the three counters and a control
register, anyone is selected using address lines A0 and A1.
 It is to be noted here that there is another timer called Intel 8253 which offers
a clock frequency of 2.6 MHz. Thus is regarded as a low clock version of 8254.
Both of these function in a similar manner however, the only difference exists
in their operating clock frequency.

Programming of 8254
 At the time of programming the timer it is necessary that each individual
counter of 8254 is to be programmed separately using control word and count
value. The figure below shows the format of the control word:

 The control word format, B 0 selects the BCD or binary count while B 1, B2, and
B3 are used to select one of the modes of operation for the counter which bits
B6 and B7 specify.
 For the operation to take place, the control word is needed to be sent for each
separate counter at the same control address register. The identification of
the control word of the particular counter is done using bits B 6 and B7 of the
control word format.
 The read/ write operations are performed using bits B 4 and B5. Through these
bits, the 16-bit count value is read and written in an orderly sequence. Also,
each time the read operation will take place the count value is to be read by
stopping the counter. Here basically the count value is latched to an internal
latch present at the output of each counter before the read operation.
 It includes a data bus buffer, read/write logic, control word register and
counters.
(a) Data Bus Buffer:
 It is tristate, bidirectional 8-bit data bus buffer.
 It is used to interface 8254 data bus with system data bus.
 It is internally connected to internal data bus and its outer pins D0-D7 are
connected to system data bus. The direction of data buffer is decided by read
and write control signals.

(b) Read/Write Logic:


 This block accepts inputs from system control bus and address bus.
 In I/O mapped I/O, the signals RD and WR are connected to IOR and IOW .
 In memory mapped I/O RD and WR , are connected to MEMR and MEMW .
 A0 and A1 are directly connected to address lines A 0 and A1.
 CS is connected to address decoder.
 The 8254 operation/selection is enables/disabled by CS signal. A0, A1 selects a
specific part RD , WR decides writing data to 8254 or reading data from 8254.
 The control word registers and the counters are selected according to the
signals on line A0 and A1.

A1 A0 Selection
0 0 Counter 0
0 1 Counter 1
1 0 Counter 2
1 1 Control Word Register

(c) Control Word Register:


 This register of 8254 programmable interval timer gets selected when A 0=1
and A1=1.
 It is used to specify the BCD or binary counter to be used, its mode of
operation and the data transfer to be used i.e. read or write the data bytes.
 If the CPU performs a write operation, the data is stored in the control word
register and is preferred to as control word. It is used to define counter
operation.
 The data can only be written into control word register, no read operation is
allowed. Status information is available with the help of read back command.

(d) Counters:
 There are three independent, 16-bit down counters.
 They can be programmed separately through control word register to decide
mode of counter.
 Each counter is having 2 inputs viz. CLK and GATE.
 CLK is used as an input to counter and GATE is used to control the counter.
 The counters give output on OUT pin.
 The loaded count value in counter will be decremented by counter at each
clock input pulse. The programmer can read counter without disturbing
counter operation.
2. Sketch the block diagram of the 8279 Keyboard Display Interface and
explain the functions of Keyboard and Display section.
 Intel’s 8279 is a dedicated controller designed by Intel that offers simultaneous
keyboard and display operations. It provides interfacing for 64-contact keys
that are arranged in 8*8 matrix format. Also, through 8279 multiplexed
interfacing can be obtained for 7-segment LEDs as well as other popular
display devices.
 Methods of Interfacing Keyboard with CPU
Mainly there are two ways by which the keyboard can be interfaced with the
CPU, these are as follows:
(a) Interrupt Mode: In this mode of operation, the CPU continues to
perform its original task until and unless any request is generated to that a
key is pressed and is required to be serviced.
(b) Polled Mode: In the polled mode of operation the CPU itself checks for
any pressed key in a periodic manner by reading the flags of 8279. So, in
this case whenever the CPU gets a signal that shows the pressed key then
the requested service is served.

 This architecture by considering its 4 separate sections.


(i) Keyboard Section
 This section is composed of Return Buffer and Keyboard Debounce and
Control. It holds the 8 return lines denoted by RL 0 to RL7 that forms the column
of the keyboard matrix. Shift and Control/Strobe are the two additional inputs
provided to this unit.
 The two operating modes are 2-key lockout and N-key rollover. In the 2-key
lockout mode of operation, if two keys are pressed at the same time then the
first recognized key will be considered by the system. While N-key rollover
mode, whenever it is found that two keys are pressed at the same time then
key codes of both of them get stored with the FIFO and are further serviced.
 It has 8*8 FIFO RAM that works on the First–In–First–Out approach and can
store 8 keycodes (code of pressed key) at a time in a sequential manner.
 The status of two additional input keys i.e., shift and control are also stored
within FIFO RAM.
 In scan keyboard mode, 8 keycodes are stored and anytime whenever an
entry is made in the FIFO RAM then 8279 generates an interrupt signal that
tells the processor to perform FIFO read operation till the time everything
within FIFO is serviced. While in sensor matrix mode, the FIFO RAM holds the
condition of 64 switches within it regarding whether these are open or closed.
Whenever the condition of any switch is changed then 8279 generates an
interrupt request for the processor.
(ii) Display Section
 This section is constituted by display address registers and display RAM. This
section contains 8 output lines i.e., A 0-A3 and B0-B3 and these are connected to
the 7-segment LEDs. There is a 16*8 display RAM and the processor simply
performs read and write operations within this RAM.
 The display address registers contain the address of that word on which the
processor is currently performing the read/write operation.
(iii) Scan Section:
 The scan counter and four scan lines (SL 0 to SL3) are part of this section. There
are two modes of scan counter namely, encode and decode. In encode mode,
a binary count will be obtained as the output of scan lines and this requires
external decoding to give rise to decoded output.
 These output scan lines are the same for the keyboard and display and 4 scan
lines can drive up to 16 displays. However, in decode scan mode, internal
decoding is performed that will provide a decoded 1 out of 4 scan lines and
thus can drive up to 4 displays. Through scan lines, rows of the matrix
keyboard are formed, and also it forms the connection to the drivers of the
display unit.
(iv) CPU Interface Section:
 This section is composed of I/O control and Data Buffers along with Timing and
Control Registers. The timing and control unit is also a part of this unit. This
section is responsible for data transfer between 8279 and the CPU and hence
consists of bidirectional data lines DB0 to DB7.
 There are two internal addresses whose specified value i.e., either 0 or 1
makes the selection for either data buffer or control register. Here we have
pins A0, CS, RD, and WR that are used for command, status, read and write
operations.
 The IRQ is an interrupt request line that is specified for data transfer that is
associated with generated interrupt requests.

Operating Modes of 8279


 Mainly, the operating modes of 8279 is classified as:

(i) Input Modes


 The input which is provided by the keyboard to the system specifies the input
mode. This mode is classified into the following categories:
a) Scanned Keyboard Mode: In this operating mode, the key matrix is
interfaced with either encoded or decoded scan. In encoded scan, 8*8
keyboard is interfaced while in the decoded scan, 4*8 keyboard is interfaced.
The keycodes are stored in the FIFO RAM.
b) Scanned Sensor Matrix: This helps in interfacing the sensor array with 8279
by making use of an encoder or decoder scan. Similar to scanner keyboard
mode, 8*8 sensor matrix for encoder scan and 4*8 sensor matrix interfacing
for decoder scan.
c) Strobed Input: This mode of operation, if control is not offered by the
processor and the control line shows low signal then the data present on the
return lines is stored in FIFO RAM byte by byte.
(ii) Output Modes
 This mode is also known as a display mode. It is further classified into two
modes. This mode helps in selecting the display options.
a) Display Scan: The 8279 generates 8 or 16 characters multiplexed displays
that are organized in either dual 4-bit or single 8-bit display units.
b) Display Entry: The data which gets displayed can be either displayed starting
from either the right side or left side.
(iii) Display Modes
 This mode is associated with data display and has two further classifications.
a) Left Entry Mode: It is also known as typewriter mode. In this, the first type
of character is present at the left-most position while further incoming
characters appear successively towards the right. This means data begins to
appear from the left side of the display unit. So, the bit value at address 0 in
the display RAM will appear at the left-most position whereas the bit value at
address 15 will appear at the right-most position.
b) Right entry Mode: This mode is also known as calculator mode. This is so
because in the calculator the first entered character appears at the rightmost
position and then successively when a new character has entered the position
of the former one is shifted towards the left. Thus, in this mode, the first entry
will appear at the rightmost position but as soon as a new entry is made then
the previous one will get shifted towards the left by one and the present entry
will take the rightmost position.

3. With a functional block diagram, briefly discuss the architecture of the


8255 programmable interrupt controller.

 PPI 8255 is a general purpose programmable I/O device designed to interface


the CPU with its outside world such as ADC, DAC, keyboard etc.
 It consists of three 8-bit bidirectional I/O ports i.e. PORT A, PORT B and PORT C

Block diagram:

a) It consists of 40 pins and operates in +5V regulated power supply. Port C is


further divided into two 4-bit ports i.e. port C lower and port C upper and port
C can work in either BSR (bit set rest) mode or in mode 0 of input-output
mode of 8255.
b) Port B can work in either mode 0 or in mode 1 of input-output mode. Port A
can work either in mode 0, mode 1 or mode 2 of input-output mode.
c) It has two control groups, control group A and control group B.
d) Control group A consist of port A and port C upper. Control group B consists of
port C lower and port B. Depending upon the value if CS’, A1 and A0 we can
select different ports in different modes as input-output function or BSR. This
is done by writing a suitable word in control register (control word D0-D7).

CS A A Selection Addres
’ 1 0 s
0 0 0 PORT A 80 H
0 0 1 PORT B 81 H
0 1 0 PORT C 82 H
0 1 1 Control 83 H
Register
1 X X No Seletion X

Operating modes:
a) Bit set reset (BSR) mode – If MSB of control word (D7) is 0, PPI works in
BSR mode. In this mode only port C bits are used for set or reset.

b) Input-Output mode – If MSB of control word (D7) is 1, PPI works in input-


output mode. This is further divided into three modes:

(i) Mode 0 –In this mode all the three ports (port A, B, C) can work as simple
input function or simple output function. In this mode there is no interrupt
handling capacity.
(ii) Mode 1 – Handshake I/O mode or strobed I/O mode. In this mode either port
A or port B can work as simple input port or simple output port, and port C
bits are used for handshake signals before actual data transmission. It has
interrupt handling capacity and input and output are latched. Example: A
CPU wants to transfer data to a printer. In this case since speed of processor
is very fast as compared to relatively slow printer, so before actual data
transfer it will send handshake signals to the printer for synchronization of
the speed of the CPU and the peripherals.
(iii) Mode 2 – Bi-directional data bus mode. In this mode only port A works, and
port B can work either in mode 0 or mode 1. 6 bits’ port C are used as
handshake signals. It also has interrupt handling capacity.

Advantages:
a) Flexibility: A microprocessor with an 8255 PPI allows for flexible
input/output (I/O) operations. The PPI can be programmed to operate in a
variety of modes, and the microprocessor can handle the data transfer
between the PPI and other devices.
b) Improved system performance: The use of a microprocessor with an 8255
PPI can improve system performance by offloading I/O operations from the
CPU. This allows the CPU to focus on other tasks while the PPI handles the
data transfer.
c) Easy to interface with other devices: The 8255 PPI can be easily
programmed and interfaced with other devices, which makes it easy to use in
a variety of applications.
d) Low cost: The 8255 PPI is a relatively low-cost component, which makes it
an affordable option for many different applications.

Disadvantages:
a) Complexity: Using a microprocessor with an 8255 PPI can add complexity to
a system, particularly for novice programmers. The PPI requires
programming, and the microprocessor must be programmed to handle the
data transfer between the PPI and other devices.
b) Limited functionality: While the 8255 PPI is versatile, it has limited
functionality compared to newer I/O interface components. It is not capable
of high-speed data transfer and has limited memory capacity.
c) Limited number of ports: The 8255 PPI provides only three 8-bit ports,
which may not be sufficient for some applications that require more I/O ports.
d) Obsolete technology: While the 8255 PPI is still used in some applications,
it is considered an older technology and is being replaced by newer, more
advanced I/O interface components.

Applications of 8255 are:


 Traffic light control
 Generating square wave
 Interfacing with DC motors and stepper motors

4. Draw and explain block diagram of 8259A programmable interrupt


controller in detail. Explain control word definition of the same.

 Intel 8259 is a Programmable Interrupt Controller (PIC). There are 5 hardware


interrupts and 2 hardware interrupts in Intel 8085 and Intel 8086
microprocessors respectively. But by connecting Intel 8259 with these
microprocessors, we can increase their interrupt handling capability.
 Intel 8259 combines the multi-interrupt input sources into a single interrupt
output. Interfacing of single PIC provides 8 interrupts inputs from IR0-IR7.
 For example, Interfacing of 8085 and 8259 increases the interrupt handling
capability of 8085 microprocessor from 5 to 8 interrupt levels.

Features of Intel 8259 PIC are as follows:


1. Intel 8259 is designed for Intel 8085 and Intel 8086 microprocessor.
2. It can be programmed either in level triggered or in edge triggered interrupt
level.
3. We can mask individual bits of interrupt request register.
4. We can increase interrupt handling capability upto 64 interrupt level by
cascading further 8259 PICs.
5. Clock cycle is not required.

Pin Diagram of 8259


Block Diagram of 8259 PIC microprocessor
 The Block Diagram consists of 8 blocks which are – Data Bus Buffer,
Read/Write Logic, Cascade Buffer Comparator, Control Logic, Priority Resolver
and 3 registers- ISR, IRR, IMR.

a) Data bus buffer – This Block is used as a mediator between 8259 and
8085/8086 microprocessor by acting as a buffer. It takes the control word from
the 8085 (let say) microprocessor and transfer it to the control logic of 8259
microprocessor. After selection of Interrupt by 8259 microprocessors (based on
priority of the interrupt), it transfers the opcode of the selected Interrupt and
address of the Interrupt service sub routine to the other connected
microprocessor. The data bus buffer consists of 8 bits represented as D0-D7 in
the block diagram. Thus, shows that a maximum of 8 bits data can be
transferred at a time.
b) Read/Write logic – This block works only when the value of pin CS is low (as
this pin is active low). This block is responsible for the flow of data depending
upon the inputs of RD and WR. These two pins are active low pins used for read
and write operations.
c) Control logic – It is the center of the PIC and controls the functioning of every
block. It has pin INTR which is connected with other microprocessor for taking
interrupt request and pin INT for giving the output. If 8259 is enabled, and the
other microprocessor Interrupt flag is high then this causes the value of the
output INT pin high and in this way 8259 responds to the request made by other
microprocessor.
d) Interrupt request register (IRR) – It stores all the interrupt level which are
requesting for Interrupt services.
e) Interrupt service register (ISR) – It stores the interrupt level which are
currently being executed.
f) Interrupt mask register (IMR) – It stores the interrupt level which have to be
masked by storing the masking bits of the interrupt level.
g) Priority resolver – It examines all the three registers and set the priority of
interrupts and according to the priority of the interrupts, interrupt with highest
priority is set in ISR register. Also, it reset the interrupt level which is already
been serviced in IRR.
h) Cascade buffer – To increase the Interrupt handling capability, we can further
cascade more number of pins by using cascade buffer. So, during increment of
interrupt capability, CSA lines are used to control multiple interrupt structure.
SP/EN (Slave program/Enable buffer) pin is when set to high, works in master mode
else in slave mode. In Non Buffered mode, SP/EN pin is used to specify whether
8259 work as master or slave and in Buffered mode, SP/EN pin is used as an output
to enable data bus.

Advantages:
 Interrupt Management: The 8259 PIC is designed to handle interrupts
efficiently and effectively, allowing for faster and more reliable processing of
interrupts in a system.
 Flexibility: The 8259 PIC is programmable, meaning that it can be
customized to suit the specific needs of a given system, including the
number and type of interrupts that need to be managed.
 Compatibility: The 8259 PIC is compatible with a wide range of
microprocessors, making it a popular choice for managing interrupts in many
different systems.
 Multiple Interrupt Inputs: The 8259 PIC can manage up to 8 interrupt
inputs, allowing for the management of complex systems with multiple
devices.
 Ease of Use: The 8259 PIC includes simple interface pins and registers,
making it relatively easy to use and program.

Disadvantages:
 Cost: While the 8259 PIC is relatively affordable, it does add cost to a
system, particularly if multiple PICs are required.
 Limited Number of Interrupts: The 8259 PIC can manage up to 8 interrupt
inputs, which may be insufficient for some applications.
 Complex Programming: Although the interface pins and registers of the
8259 PIC are relatively simple, programming the 8259 can be complex,
requiring careful attention to interrupt prioritization and other parameters.
 Limited Functionality: While the 8259 PIC is a useful peripheral for
interrupt management, it does not include more advanced features, such as
DMA (direct memory access) or advanced error correction.

5. With neat block diagram, explain the description and function of 8251.

 8251 universal synchronous asynchronous receiver transmitter (USART) acts


as a mediator between microprocessor and peripheral to transmit serial data
into parallel form and vice versa.
1. It takes data serially from peripheral (outside devices) and converts into
parallel data.
2. After converting the data into parallel form, it transmits it to the CPU.
3. Similarly, it receives parallel data from microprocessor and converts it
into serial form.
4. After converting data into serial form, it transmits it to outside device
(peripheral).

Block Diagram of 8251 USART


It contains the following blocks:
a) Data bus buffer – This block helps in interfacing the internal data bus of
8251 to the system data bus. The data transmission is possible between
8251 and CPU by the data bus buffer block.
b) Read/Write control logic – It is a control block for overall device. It controls
the overall working by selecting the operation to be done. The operation
selection depends upon input signals as:

c) In this way, this unit selects one of the three registers- data buffer register,
control register, status register.
d) Modem control (modulator/demodulator) – A device converts analog
signals to digital signals and vice-versa and helps the computers to
communicate over telephone lines or cable wires. The following are active-
low pins of Modem.
 DSR: Data Set Ready signal is an input signal.
 DTR: Data terminal Ready is an output signal.
 CTS: It is an input signal which controls the data transmit circuit.
 RTS: It is an output signal which is used to set the status RTS.
e) Transmit buffer – This block is used for parallel to serial converter that
receives a parallel byte for conversion into serial signal and further
transmission onto the common channel.
 TXD: It is an output signal, if its value is one, means transmitter will
transmit the data.
f) Transmit control – This block is used to control the data transmission with
the help of following pins:
 TXRDY: It means transmitter is ready to transmit data character.
 TXEMPTY: An output signal which indicates that TXEMPTY pin has
transmitted all the data characters and transmitter is empty now.
 TXC: An active-low input pin which controls the data transmission rate of
transmitted data.
g) Receive buffer – This block acts as a buffer for the received data.
 RXD: An input signal which receives the data.
h) Receive control – This block controls the receiving data.
 RXRDY: An input signal indicates that it is ready to receive the data.
 RXC: An active-low input signal which controls the data transmission rate of
received data.
 SYNDET/BD: An input or output terminal. External synchronous mode-input
terminal and asynchronous mode-output terminal.

Advantages:

 Versatility: The 8251 USART can be used for both synchronous and
asynchronous communication, making it a versatile peripheral.
 Error detection: The USART includes built-in error detection features, such
as parity checking, which help to ensure the accuracy of transmitted data.
 Flow control: The USART includes flow control features, which allow for
the regulation of data transmission and reception, preventing data loss and
overloading.
 Compatibility: The 8251 USART is compatible with a wide range of
microprocessors, making it a popular choice for serial communication in
many different systems.
 Ease of use: The USART includes simple interface pins and registers,
making it relatively easy to use and program.

Disadvantages:
 Limited speed: The 8251 USART has a relatively low maximum data
transfer rate of 115.2 kbps, which may be insufficient for some applications.
 Limited buffer size: The USART has a small internal buffer size, which
may result in data loss if data is not read from the buffer in a timely
manner.
 Complex programming: Although the interface pins and registers of the
USART are relatively simple, programming the USART can be complex,
requiring careful attention to timing and other parameters.
 Cost: While the 8251 USART is relatively affordable, it does add cost to a
system, particularly if multiple USARTs are required.
 Limited functionality: While the 8251 USART is a useful peripheral for
serial communication, it does not include more advanced features, such as
DMA (direct memory access) or advanced error correction.

6. Draw and describe the interfacing of A/D and D/A converter with 8085
microprocessor.

Interfacing ADC with 8085 Microprocessor:


 The Analog to Digital Conversion(ADC) is a quantizing process. Here the
analog signal is represented by equivalent binary states. The A/D converters
can be classified into two groups based on their conversion techniques.
 In the first technique it compares given analog signal with the initially
generated equivalent signal. In this technique, it includes successive
approximation, counter and flash type converters.
 In another technique it determines the changing of analog signals into time or
frequency. This process includes integrator-converters and voltage-to-
frequency converters.
 The first process is faster but less accurate, the second one is more accurate.
As the first process uses flash type, so it is expensive and difficult to design for
high accuracy.

ADC 0808/0809 Chip


 The ADC 0808/0809 is an 8-bit analog to digital converter. It has 8 channel
multiplexer to interface with the microprocessor. This chip is popular and
widely used ADC.
 ADC 0808/0809 is a monolithic CMOS device. This device uses successive
approximation technique to convert analog signal to digital form. One of the
main advantage of this chip is that it does not require any external zero and
full scale adjustment, only +5V DC supply is sufficient.
 Let us see some good features of ADC 0808/0809
a) The conversion speed is much higher
b) The accuracy is also high
c) It has minimal temperature dependence
d) Excellent long term accuracy and repeatability
e) Less power consumption
Block diagram of 0808/0809 chip

 To interface the ADC with 8085, we need 8255 Programmable Peripheral


Interface chip with it. Let us see the circuit diagram of connecting 8085, 8255
and the ADC converter.
 The Port A of 8255 chip is used as the input port. The PC 7 pin of Port Cupper is
connected to the End of Conversion (EOC) Pin of the analog to digital
converter. This port is also used as input port.
 The Clower port is used as output port. The PC 2-0 lines are connected to three
address pins of this chip to select input channels. The PC 3 pin is connected to
the Start of Conversion (SOC) pin and ALE pin of ADC 0808/0809.
Program:
MVI A, 98H Set Port A and Cupper as input, CLower as output
OUT 03H Write control word 8255-I to control Word
Register
XRA A Clear the accumulator
OUT 02H Send the content of Acc to Port Clower to select IN0
MVI A, 08H Load the accumulator with 08H
OUT 02H ALE and SOC will be 0
XRA A Clear the accumulator
OUT 02H ALE and SOC will be low.
READ: IN 02H Read from EOC (PC7)
RAL Rotate left to check C7 is 1
JNC READ If C7 is not 1, go to READ
IN 00H Read digital output of ADC
STA 8000H Save result at 8000H
HLT Stop the program

Interfacing DAC with 8085 Microprocessor:


 In many applications, the microprocessor has to produce analog signals for
controlling certain analog devices. Basically the microprocessor system can
produce only digital signals. In order to convert the digital signal to analog signal
a Digital-to-Analog Converter, (DAC) has to be employed.
 The DAC require a reference analog voltage (Vref) or current (Iref) source.
 The smallest possible analog value that can be represented by the n-bit binary
code is called resolution. The resolution of DAC with n-bit binary input is 1/2n of
reference analog value.
 Every analog output will be a multiple of the resolution. In some converters the
input reference analog signal will be multiplied or divided by a constant to get
full scale value. Now the resolution will be 1/2n of full scale value.
 For example,
Consider an 8-bit DAC with reference analog voltage of 5 volts. Now the
resolution of the DAC is (1/2 8) x 5 volts. The 8-bit digital input can take, 2 8 = 256
different values. The analog values for all possible digital input are as shown in
table below.
 The maximum input digital signal will have an analog value which is equal to
reference analog value minus resolution.
 The digital-to-analog converters can be broadly classified into three categories,
and they are
a. Current output
b. Voltage output
c. Multiplying type
 The current output DAC provides an analog current as output signal. In voltage
output DAC, the analog current signal is internally converted to voltage signal.
Typical DAC circuit:
 The basic components of a DAC are resistive network with appropriate values,
switches, a reference source and a current to voltage converter as shown in
figure below.

 The switches in the circuit of figure above can be transistors which connects the
resistance either to ground or V ref. The resistors are connected in such a way
that for any number of inputs, the total current is in binary proportion. The
operational amplifier converts the current to a voltage signal V0, which can be
calculated from the following equation.
 The circuit of figure shown above can be modified as 8-bit DAC, by increasing
the number of R/2R ladder. For an 8-bit DAC the output voltage is given by
 The time required for converting the digital signal to analog signal is called
conversion time. It depends on the response time of the switching transistors
and the output amplifier.
 If the DAC is interfaced to microprocessor then the digital data (Signal) should
remain at the input of DAC, until the conversion is complete. Hence to hold the
data a latch is provided at the input of DAC.

 The Digital-to-Analog converters compatible to microprocessors are available


with or without internal latch and I to V converting amplifier. The AD558 of
Analog Devices is an example of 8-bit DAC with an internal latch and I to V
converting amplifiers. The output of AD558 is an analog voltage signal.
 The AD558 can be directly interfaced to 8085 microprocessor bus and it requires
only two control signals: Chip Select (CS) and Chip Enable (CE). [No handshake
signals are necessary for interfacing a DAC. The time between loading two
digital data to DAC is controlled by software time delay].
 The DAC0808 of National Semiconductor Corporation is an example of 8-bit DAC
without internal latch and I to V converting amplifier. The internal block diagram
and the pin configuration of DAC0808 are shown in figure below.

Block diagram of DAC0808 Pin diagram of DAC0808


 The DAC0800 can be interfaced to 8085 systems through an 8-bit latch as
shown in figure below. The chip select (CS) signal from the decoder of the
microprocessor system is delayed and inverted to clock the latch. If the DAC is
memory mapped, then the CS is from memory decoder. If the DAC is I/O
mapped, then CS is from I/O decoder.
Interfacing DAC0808 to 8085 microprocessor system

 The processor sends an address, which is decoded by decoder in the


microprocessor system to produce chip select signal. Then the processor sends a
digital data to latch.
 The buffer and inverter will produce sufficient delay for CS signal so that, the
latch is clocked only after the data is arrived at the input lines of the latch. When
the latch is clocked the digital data is send to DAC.
 The DAC will produce a corresponding current signal, which is converted to
voltage signal by the op-amp 741. The typical settling time of DAC0800 is
150nsec. Therefore, the processor need not wait for loading next data.

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