Peripheral Interfacing
Peripheral Interfacing
PERIPHERAL INTERFACING
1. With neat block diagram, explain the description and function of 8254.
Intel 8254 is a programmable interval timer designed by intel is a
programmable external timer device built with an aim to resolve the time
control issues that occur in between various processes occurring within the
microprocessor. In order to communicate with the processor, it has a total of 8
data lines.
There are overall 24 pin signals in which it operates and the power supply
provided to it is +5V.
Programming of 8254
At the time of programming the timer it is necessary that each individual
counter of 8254 is to be programmed separately using control word and count
value. The figure below shows the format of the control word:
The control word format, B 0 selects the BCD or binary count while B 1, B2, and
B3 are used to select one of the modes of operation for the counter which bits
B6 and B7 specify.
For the operation to take place, the control word is needed to be sent for each
separate counter at the same control address register. The identification of
the control word of the particular counter is done using bits B 6 and B7 of the
control word format.
The read/ write operations are performed using bits B 4 and B5. Through these
bits, the 16-bit count value is read and written in an orderly sequence. Also,
each time the read operation will take place the count value is to be read by
stopping the counter. Here basically the count value is latched to an internal
latch present at the output of each counter before the read operation.
It includes a data bus buffer, read/write logic, control word register and
counters.
(a) Data Bus Buffer:
It is tristate, bidirectional 8-bit data bus buffer.
It is used to interface 8254 data bus with system data bus.
It is internally connected to internal data bus and its outer pins D0-D7 are
connected to system data bus. The direction of data buffer is decided by read
and write control signals.
A1 A0 Selection
0 0 Counter 0
0 1 Counter 1
1 0 Counter 2
1 1 Control Word Register
(d) Counters:
There are three independent, 16-bit down counters.
They can be programmed separately through control word register to decide
mode of counter.
Each counter is having 2 inputs viz. CLK and GATE.
CLK is used as an input to counter and GATE is used to control the counter.
The counters give output on OUT pin.
The loaded count value in counter will be decremented by counter at each
clock input pulse. The programmer can read counter without disturbing
counter operation.
2. Sketch the block diagram of the 8279 Keyboard Display Interface and
explain the functions of Keyboard and Display section.
Intel’s 8279 is a dedicated controller designed by Intel that offers simultaneous
keyboard and display operations. It provides interfacing for 64-contact keys
that are arranged in 8*8 matrix format. Also, through 8279 multiplexed
interfacing can be obtained for 7-segment LEDs as well as other popular
display devices.
Methods of Interfacing Keyboard with CPU
Mainly there are two ways by which the keyboard can be interfaced with the
CPU, these are as follows:
(a) Interrupt Mode: In this mode of operation, the CPU continues to
perform its original task until and unless any request is generated to that a
key is pressed and is required to be serviced.
(b) Polled Mode: In the polled mode of operation the CPU itself checks for
any pressed key in a periodic manner by reading the flags of 8279. So, in
this case whenever the CPU gets a signal that shows the pressed key then
the requested service is served.
Block diagram:
CS A A Selection Addres
’ 1 0 s
0 0 0 PORT A 80 H
0 0 1 PORT B 81 H
0 1 0 PORT C 82 H
0 1 1 Control 83 H
Register
1 X X No Seletion X
Operating modes:
a) Bit set reset (BSR) mode – If MSB of control word (D7) is 0, PPI works in
BSR mode. In this mode only port C bits are used for set or reset.
(i) Mode 0 –In this mode all the three ports (port A, B, C) can work as simple
input function or simple output function. In this mode there is no interrupt
handling capacity.
(ii) Mode 1 – Handshake I/O mode or strobed I/O mode. In this mode either port
A or port B can work as simple input port or simple output port, and port C
bits are used for handshake signals before actual data transmission. It has
interrupt handling capacity and input and output are latched. Example: A
CPU wants to transfer data to a printer. In this case since speed of processor
is very fast as compared to relatively slow printer, so before actual data
transfer it will send handshake signals to the printer for synchronization of
the speed of the CPU and the peripherals.
(iii) Mode 2 – Bi-directional data bus mode. In this mode only port A works, and
port B can work either in mode 0 or mode 1. 6 bits’ port C are used as
handshake signals. It also has interrupt handling capacity.
Advantages:
a) Flexibility: A microprocessor with an 8255 PPI allows for flexible
input/output (I/O) operations. The PPI can be programmed to operate in a
variety of modes, and the microprocessor can handle the data transfer
between the PPI and other devices.
b) Improved system performance: The use of a microprocessor with an 8255
PPI can improve system performance by offloading I/O operations from the
CPU. This allows the CPU to focus on other tasks while the PPI handles the
data transfer.
c) Easy to interface with other devices: The 8255 PPI can be easily
programmed and interfaced with other devices, which makes it easy to use in
a variety of applications.
d) Low cost: The 8255 PPI is a relatively low-cost component, which makes it
an affordable option for many different applications.
Disadvantages:
a) Complexity: Using a microprocessor with an 8255 PPI can add complexity to
a system, particularly for novice programmers. The PPI requires
programming, and the microprocessor must be programmed to handle the
data transfer between the PPI and other devices.
b) Limited functionality: While the 8255 PPI is versatile, it has limited
functionality compared to newer I/O interface components. It is not capable
of high-speed data transfer and has limited memory capacity.
c) Limited number of ports: The 8255 PPI provides only three 8-bit ports,
which may not be sufficient for some applications that require more I/O ports.
d) Obsolete technology: While the 8255 PPI is still used in some applications,
it is considered an older technology and is being replaced by newer, more
advanced I/O interface components.
a) Data bus buffer – This Block is used as a mediator between 8259 and
8085/8086 microprocessor by acting as a buffer. It takes the control word from
the 8085 (let say) microprocessor and transfer it to the control logic of 8259
microprocessor. After selection of Interrupt by 8259 microprocessors (based on
priority of the interrupt), it transfers the opcode of the selected Interrupt and
address of the Interrupt service sub routine to the other connected
microprocessor. The data bus buffer consists of 8 bits represented as D0-D7 in
the block diagram. Thus, shows that a maximum of 8 bits data can be
transferred at a time.
b) Read/Write logic – This block works only when the value of pin CS is low (as
this pin is active low). This block is responsible for the flow of data depending
upon the inputs of RD and WR. These two pins are active low pins used for read
and write operations.
c) Control logic – It is the center of the PIC and controls the functioning of every
block. It has pin INTR which is connected with other microprocessor for taking
interrupt request and pin INT for giving the output. If 8259 is enabled, and the
other microprocessor Interrupt flag is high then this causes the value of the
output INT pin high and in this way 8259 responds to the request made by other
microprocessor.
d) Interrupt request register (IRR) – It stores all the interrupt level which are
requesting for Interrupt services.
e) Interrupt service register (ISR) – It stores the interrupt level which are
currently being executed.
f) Interrupt mask register (IMR) – It stores the interrupt level which have to be
masked by storing the masking bits of the interrupt level.
g) Priority resolver – It examines all the three registers and set the priority of
interrupts and according to the priority of the interrupts, interrupt with highest
priority is set in ISR register. Also, it reset the interrupt level which is already
been serviced in IRR.
h) Cascade buffer – To increase the Interrupt handling capability, we can further
cascade more number of pins by using cascade buffer. So, during increment of
interrupt capability, CSA lines are used to control multiple interrupt structure.
SP/EN (Slave program/Enable buffer) pin is when set to high, works in master mode
else in slave mode. In Non Buffered mode, SP/EN pin is used to specify whether
8259 work as master or slave and in Buffered mode, SP/EN pin is used as an output
to enable data bus.
Advantages:
Interrupt Management: The 8259 PIC is designed to handle interrupts
efficiently and effectively, allowing for faster and more reliable processing of
interrupts in a system.
Flexibility: The 8259 PIC is programmable, meaning that it can be
customized to suit the specific needs of a given system, including the
number and type of interrupts that need to be managed.
Compatibility: The 8259 PIC is compatible with a wide range of
microprocessors, making it a popular choice for managing interrupts in many
different systems.
Multiple Interrupt Inputs: The 8259 PIC can manage up to 8 interrupt
inputs, allowing for the management of complex systems with multiple
devices.
Ease of Use: The 8259 PIC includes simple interface pins and registers,
making it relatively easy to use and program.
Disadvantages:
Cost: While the 8259 PIC is relatively affordable, it does add cost to a
system, particularly if multiple PICs are required.
Limited Number of Interrupts: The 8259 PIC can manage up to 8 interrupt
inputs, which may be insufficient for some applications.
Complex Programming: Although the interface pins and registers of the
8259 PIC are relatively simple, programming the 8259 can be complex,
requiring careful attention to interrupt prioritization and other parameters.
Limited Functionality: While the 8259 PIC is a useful peripheral for
interrupt management, it does not include more advanced features, such as
DMA (direct memory access) or advanced error correction.
5. With neat block diagram, explain the description and function of 8251.
c) In this way, this unit selects one of the three registers- data buffer register,
control register, status register.
d) Modem control (modulator/demodulator) – A device converts analog
signals to digital signals and vice-versa and helps the computers to
communicate over telephone lines or cable wires. The following are active-
low pins of Modem.
DSR: Data Set Ready signal is an input signal.
DTR: Data terminal Ready is an output signal.
CTS: It is an input signal which controls the data transmit circuit.
RTS: It is an output signal which is used to set the status RTS.
e) Transmit buffer – This block is used for parallel to serial converter that
receives a parallel byte for conversion into serial signal and further
transmission onto the common channel.
TXD: It is an output signal, if its value is one, means transmitter will
transmit the data.
f) Transmit control – This block is used to control the data transmission with
the help of following pins:
TXRDY: It means transmitter is ready to transmit data character.
TXEMPTY: An output signal which indicates that TXEMPTY pin has
transmitted all the data characters and transmitter is empty now.
TXC: An active-low input pin which controls the data transmission rate of
transmitted data.
g) Receive buffer – This block acts as a buffer for the received data.
RXD: An input signal which receives the data.
h) Receive control – This block controls the receiving data.
RXRDY: An input signal indicates that it is ready to receive the data.
RXC: An active-low input signal which controls the data transmission rate of
received data.
SYNDET/BD: An input or output terminal. External synchronous mode-input
terminal and asynchronous mode-output terminal.
Advantages:
Versatility: The 8251 USART can be used for both synchronous and
asynchronous communication, making it a versatile peripheral.
Error detection: The USART includes built-in error detection features, such
as parity checking, which help to ensure the accuracy of transmitted data.
Flow control: The USART includes flow control features, which allow for
the regulation of data transmission and reception, preventing data loss and
overloading.
Compatibility: The 8251 USART is compatible with a wide range of
microprocessors, making it a popular choice for serial communication in
many different systems.
Ease of use: The USART includes simple interface pins and registers,
making it relatively easy to use and program.
Disadvantages:
Limited speed: The 8251 USART has a relatively low maximum data
transfer rate of 115.2 kbps, which may be insufficient for some applications.
Limited buffer size: The USART has a small internal buffer size, which
may result in data loss if data is not read from the buffer in a timely
manner.
Complex programming: Although the interface pins and registers of the
USART are relatively simple, programming the USART can be complex,
requiring careful attention to timing and other parameters.
Cost: While the 8251 USART is relatively affordable, it does add cost to a
system, particularly if multiple USARTs are required.
Limited functionality: While the 8251 USART is a useful peripheral for
serial communication, it does not include more advanced features, such as
DMA (direct memory access) or advanced error correction.
6. Draw and describe the interfacing of A/D and D/A converter with 8085
microprocessor.
The switches in the circuit of figure above can be transistors which connects the
resistance either to ground or V ref. The resistors are connected in such a way
that for any number of inputs, the total current is in binary proportion. The
operational amplifier converts the current to a voltage signal V0, which can be
calculated from the following equation.
The circuit of figure shown above can be modified as 8-bit DAC, by increasing
the number of R/2R ladder. For an 8-bit DAC the output voltage is given by
The time required for converting the digital signal to analog signal is called
conversion time. It depends on the response time of the switching transistors
and the output amplifier.
If the DAC is interfaced to microprocessor then the digital data (Signal) should
remain at the input of DAC, until the conversion is complete. Hence to hold the
data a latch is provided at the input of DAC.