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DMA Controller - 8257/8237

The document discusses direct memory access (DMA) and the Intel 8257/8237 DMA controller chip. It explains that DMA allows peripheral devices to directly access main memory without involving the CPU. The 8257/8237 is a 4-channel DMA controller that interfaces with peripherals to arbitrate DMA requests and provide address/control signals for data transfers between peripherals and memory. It has registers like current address, mode and status registers that are programmed to configure the DMA transfers.

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49 views

DMA Controller - 8257/8237

The document discusses direct memory access (DMA) and the Intel 8257/8237 DMA controller chip. It explains that DMA allows peripheral devices to directly access main memory without involving the CPU. The 8257/8237 is a 4-channel DMA controller that interfaces with peripherals to arbitrate DMA requests and provide address/control signals for data transfers between peripherals and memory. It has registers like current address, mode and status registers that are programmed to configure the DMA transfers.

Uploaded by

infinity Infinity
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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DMA Controller – 8257/8237

Direct memory access


• Direct memory access (DMA) is a process in which an
external device takes over the control of system bus from
the CPU.

• DMA is for high-speed data transfer from/to mass storage


peripherals, e.g. harddisk drive, magnetic tape, CD-ROM,
and sometimes video controllers.

• The basic idea of DMA is to transfer blocks of data


directly between memory and peripherals.

• The data don’t go through the microprocessor but the


data bus is occupied.
2
Basic process of DMA – Minimum Mode

• The HOLD and HLDA pins are used to receive and


acknowledge the hold request respectively.

• Normally the CPU has full control of the system


bus.

• In a DMA operation, the peripheral takes over bus


control temporarily.

3
Basic process of DMA – Maximum Mode
• The RQ/GT1 and RQ/GT0 pins are used to issue DMA
request and receive acknowledge signals.
• Sequence of events of a typical DMA process:
1. Peripheral asserts one of the request pins, e.g. RQ/GT1 or
RQ/GT0 (RQ/GT0 has higher priority)
2. 8086 completes its current bus cycle and enters into a HOLD
state.
3. 8086 grants the right of bus control by asserting a grant signal
via the same pin as the request signal.
4. DMA operation starts.
5. Upon completion of the DMA operation, the peripheral asserts
the request/grant pin again to relinquish bus control.

4
DMA controller
• A DMA controller interfaces with several peripherals that may
request DMA.

• The controller decides the priority of simultaneous DMA


requests communicates with the peripheral and the CPU, and
provides memory addresses for data transfer.

• DMA controller commonly used with 8086 is the 8257/8237


programmable device.

• The 8257/8237 is a 4-channel device.

• Each channel is dedicated to a specific peripheral device and


capable of addressing 64 K bytes section of memory.
5
8237 - DMA Controller

6
8237 Registers
1. Current word register
2. Command register
3. Mode register
4. Request register
5. Mask register
6. Status register
7. Temporary register
8. Current address register
8
8237 Registers
1.Current address register
• One 16-bit register for each channel
• Holds address for the current DMA transfer

2.Current word register


• Keeps the byte count
• Generates terminal count (TC) signal when the count goes
from zero to FFFFH

3.Command register
• Used to program 8257

9
8237 Registers
4.Mode register
• Each channel can be programmed to
– Read or write
– Autoincrement or autodecrement the address
– Autoinitialize the channel

5.Request register
• For software-initiated DMA
6.Mask register
• Used to disable a specific channel
7.Status register
8.Temporary register
• Used for memory-to-memory transfers
10
Types of data transfer
• 8237 supports four types of data transfer
1. Single cycle transfer
• Only single transfer takes place
• Useful for slow devices
2. Block transfer mode
• Transfers data until TC is generated or external EOP signal is
received
3. Demand transfer mode
• Similar to the block transfer mode
• In addition to TC and EOP, transfer can be terminated by
deactivating DREQ signal
4. Cascade mode
• Useful to expand the number channels beyond four
11
Command
Register

12
Mode
Register

13
Request Register

14
Mask
Register

15
Status
Register

16

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