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DMA Is Implemented Using A DMA Controller

DMA allows transfer of data between memory and I/O devices without continuous CPU intervention by using a DMA controller. The DMA controller contains registers like the address and count registers that are loaded by the CPU before initiating a transfer. It then handles the data transfer process, freeing up the CPU. Common modes are fly-by and memory-to-memory. DMA improves system performance by freeing the CPU while transferring data in the background.

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372 views

DMA Is Implemented Using A DMA Controller

DMA allows transfer of data between memory and I/O devices without continuous CPU intervention by using a DMA controller. The DMA controller contains registers like the address and count registers that are loaded by the CPU before initiating a transfer. It then handles the data transfer process, freeing up the CPU. Common modes are fly-by and memory-to-memory. DMA improves system performance by freeing the CPU while transferring data in the background.

Uploaded by

parveshtext
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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OVERVIEW

Introduction Implementing DMA in a computer system Data transfer using DMA controller Internal configuration of a DMA controller Process of DMA transfer DMA transfer modes Modification of the CPU to work with DMA Summary

What is DMA?
Direct Memory Access Assists the movement of data between external memory and internal peripherals with minimal CPU intervention An internal peripheral is assigned to one or more DMA channels. Each channel moves data one direction. It either receives incoming data or transmits outgoing data.

Direct Memory Access (DMA)


To transfer large blocks of data at high speed, an alternative approach is used. Blocks of data are transferred between an external device and the main memory, without continuous intervention by the processor.

Direct Memory Access (DMA) Summary


10 Channels total
8 channels wired into NET+ARM modules
Ethernet, Serial, Parallel / ENI

2 Channels available for external Memory moves


Handshaking signals muxed into GPIO lines

Can move data while ARM executes from Cache Simple Implementation
Good for repetitive data movement

DMA is implemented using a DMA controller DMA controller Acts as slave to processor Receives instructions from processor

Steps in a DMA operation


Processor initiates the DMA controller
Gives device number, memory buffer pointer, Called channel initialization
Gives device number

Once initialized, it is ready for data transfer

I/O device number processor DMA controller

When ready, I/O device informs the DMA controller


DMA controller starts the data transfer process Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read, loops back to repeat the process

I/O device number microprocessor Data bus DMA controller

Modes of Operation
Fly-by
Data is directly transferred between memory and the peripheral

Memory to Memory
Data is not directly transferred, but buffered in between transfers Data is copied from the source location into a temporary area in the DMA channel, and then written into the destination location.

External DMA Fly By


Net+ARM
DMA Controller

DMA Request
Peripheral

Add

DMA Grant

Memory

DATA

External DMA Mem To Mem


Net+ARM
DMA Controller
Holding FIFO

DMA Request DMA Grant


ADD

Peripheral

DATA

Memory

DATA

ADD

Implementing DMA in a Computer System


A DMA controller implements direct memory access in a computer system. It connects directly to the I/O device at one end and to the system buses at the other end. It also interacts with the CPU, both via the system buses and two new direct connections. It is sometimes referred to as a channel. In an alternate configuration, the DMA controller may be incorporated directly into the I/O device.

Data Transfer using DMA Controller


To transfer data from an I/O device to memory, the DMA controller first sends a Bus Request to the CPU by setting BR to 1. When it is ready to grant this request, the CPU sets its Bus grant signal, BG to 1. The CPU also tri-states its address,data, and control lines thus truly granting control of the system buses to the DMA controller. The CPU will continue to tri-state its outputs as long as BR is asserted. cont

Process of DMA Transfer


To initiate a DMA transfer, the CPU loads the address of the first memory location of the memory block (to be read or written from) into the DMA address register. It does his via an I/O output instruction, such as the OTPT instruction for the relatively simple CPU. It then writes the no. of bytes to be transferred into the DMA count register in the sane manner. Finally, it writes one or more commands to the DMA control register.

Internal Configuration

The DMA controller includes several registers :The DMA Address Register contains the memory address to be used in the data transfer. The CPU treats this signal as one or more output ports. The DMA Count Register, also called Word Count Register, contains the no. of bytes of data to be transferred. Like the DMA address register, it too is treated as an O/P port (with a diff. Address) by the CPU. The DMA Control Register accepts commands from the CPU. It is also treated as an O/P port by the CPU.

Operating Sequence of a DMA Transfer


To perform a DMA transfer the CPU:
allocates a memory block and assigns it to the DMAC; writes the transfer mode and the address of the peripheral device to the DMAC registers; waits for DMA request from the peripheral after configuring the DMAC.

If a peripheral device receives data from outside it asserts the request signal to the DMAC. The DMAC transfers the received data from the peripheral device controller to the memory and asserts the acknowledge signal to the peripheral device. When the transfer is completed a flag in the status register of the DMAC will be set and/or the DMA controller sends an interrupt to the CPU.

Main Features of the DMA Controller (I)


The DMAC will be designed for an AMBA AHB 2.0 bus with a bigendian data format. The DMAC is configurable for each valid AHB data bus width from 32 bits up to 1024 bits. The DMAC has several independent DMA channels. The number of these channels is configurable from 1 up to 31. The DMAC executes only dual-access transfers using an internal memory organised as FIFO. The DMAC supports single transfers as well as a block transfer.
Single transfer consists of a read burst and a subsequent write burst. A block transfer consists of several successive single transfers.

The burst length as well as the number of transfers is programmable.

Main Features of the DMA Controller (II)


The data width of a transfer is programmable from 8 bits up to the data bus width in steps of powers to the base of two (8 bits, 16 bits, , 1024 bits). The controller supports all four possible kinds of transfer
Peripheral Memory Memory Peripheral Peripheral Peripheral Memory Memory

A transfer can be triggered by sending a software command from the CPU or by asserting of a request signal DREQ. The controller asserts an acknowledge signal DACK as a response on a hardware request.

Transfer Rate of the DMA Controller


Transfer Rate in units of Mbits/sec
400 350 300 250 200 150 100 50 0 1 Burst Length 32

This chart shows the theoretical (top curve) and measured transfer rate of the DMAC. These transfer rates apply to a 25 MHz system clock. The measured transfer rate is lower than the theoretical transfer rate due to the used memory configuration.

Advantages of DMA
Fast memory transfer of data CPU and DMA run concurrently under cache mode DMA can trigger an interrupt, which frees the CPU from polling the channel

Buffers and Arbitration


Most DMACs have a data storage buffer network interfaces receive data from main memory at bus speed, send data onto network at network speed. Bus Arbitration is needed to resolve conflicts with more than one device (2 DMACs or DMA and processor, etc..) try to use the bus to access main memory.

Advantages of DMA

Summary

Computer system performance is improved by direct transfer of data between memory and I/O devices, bypassing the CPU. CPU is free to perform operations that do not use system buses.

Disadvantages of DMA
In case of Burst Mode data transfer, the CPU is rendered inactive for relatively long periods of time.

Minimal System with a DMA Controller


CPU Interrupt Bus Arbiter On-Chip-Bus Memory

DMA Controller

Request Acknowledge

Peripheral Device

Conclusions
A DMA controller specification for a SoC has been conceived supporting a list of typical and application-specific features. A sophisticated DMA controller has been designed. The DMA controller has been implemented successfully as a VHDL IP core. The DMA Controller has been integrated together with the LEON-2 IP core in a Xilinx Virtex-II FPGA. The functionality of DMA controller has been tested extensively. The DMAC is suitable for use with High-bandwidth Peripherals. The following CAD tools have been used:
Mentor ModelSim Synplicity Synplify XILINX Foundation ISE 5.1

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