DEPARTMENT OF

COMPUTER SCIENCE
Nutan College Of Engineering&Research, & ENGINEERING
TalegaonDabhade, Pune- 410507
Computer Architecture And Organization
Unit II: Instruction Set

I. Characteristics
1. Elements of a Machine Instruction
2. Instruction Representation
3. Instruction Types
4. Number of Addresses
5. Instruction Set Design
II. Types of Operands
1. Numbers
2. Characters
3. Logical Data
III. Types of Operations
1. Data Transfer
2. Arithmetic
3. Logical
4. Conversion
5. Input/ Output
6. System Control
7. Transfer of Control
IV. Assembly language
V. Types of Addressing Mode
1. Immediate Addressing
2. Direct Addressing
3. Indirect Addressing
4. Register Addressing
5. Register Indirect Addressing
6. Index Addressing Mode
7. Base Index Addressing Mode
VI. Instruction Formats
VII. Types of Instruction
1. Zero address/ stack based
2. One address/ Accumulator based
3. Multiple address/ general purpose register based
VIII. Instruction execution
IX. Structure of Program
X. Introduction to RISC & CISC Architecture
1. Comparison RISC &CISC
2. RISC architecture
3. RISC characteristics
4. RISC advantages
5. RISC Disadvantages
6. CISC architecture
7. CISC characteristics
8. CISC advantages
9. CISC Disadvantages

Introduction

The Instruction Set, also called ISA (instruction set architecture), is part of a computer that
pertains to programming, which is basically machine language. The instruction set provides
commands to the processor, to tell it what it needs to do. The instruction set consists of addressing
modes, instructions, native data types, registers, memory architecture, interrupt, and exception
handling, and external I/O.
An example of an instruction set is the x86 instruction set, which is common to find on computers
today. Different computer processors can use almost the same instruction set while still having very
different internal design. Both the Intel Pentium and AMD Athlon processors use nearly the same
x86 instruction set. An instruction set can be built into the hardware of the processor, or it can be
emulated in software, using an interpreter. The hardware design is more efficient and faster for
running programs than the emulated software version.

I. Characteristics
The operation of the processor is determined by the instructions it executes, referred
to as machine instructions or computer instructions. The collection of different
instructions that the processor can execute is referred to as the processor’s instruction
set.

1. Elements of a Machine Instruction

Each instruction must contain the information required by the processor for
execution.
Operation code: Specifies the operation to be performed (e.g., ADD, I/O).
The operation is specified by a binary code, known as the operation code, or
opcode.
Source operand reference: The operation may involve one or more source
operands, that is, operands that are inputs for the operation.
Result operand reference: The operation may produce a result.
Next instruction reference: This tells the processor where to fetch the next
instruction after the execution of this instruction is complete.
2. Instruction Representation
Within the computer, each instruction is represented by a sequence of bits. The
instruction is divided into fields, corresponding to the constituent elements of the
instruction. A simple example of an instruction format is shown in Figure 10.2.
During instruction execution, an instruction is read into an instruction register (IR) in the
processor. The processor must be able to extract the data from the various instruction
fields to perform the required operation.
It is difficult for both the programmer and the reader of textbooks to deal with binary
representations of machine instructions. Thus, it has become common practice to use a
symbolic representation of machine instructions.
Opcodes are represented by abbreviations, called mnemonics, that indicate the operation.
Common examples include
ADD Add
SUB Subtract
MUL Multiply
DIV Divide
LOAD Load data from memory
STOR Store data to memory

Operands are also represented symbolically. For example, the instruction may mean add
the value contained in data location Y to the contents of register R. In this example, Y
refers to the address of a location in memory, and R refers to a particular register.

3. Instruction Types
Categorize instruction types as follows:
Data processing: Arithmetic and logic instructions
Data storage: Movement of data into or out of register and or memory
locations
Data movement: I/O instructions
Control: Test and branch instructions

Arithmetic instructions provide computational capabilities for processing numeric data.

Logic (Boolean) instructions operate on the bits of a word as bits rather than as numbers.
thus, they provide capabilities for processing any other type of data the user may
wish to employ. These operations are performed primarily on data in processor
registers. Therefore, there must be memory instructions for moving data between
memory and the registers. I/O instructions are needed to transfer programs and data into
memory and the results of computations back out to the user. Test instructions are used to
test the value of a data word or the status of a computation. Branch instructions are then
used to branch to a different set of instructions depending on the decision made.
4. Number of Addresses
Three-address instruction formats are not common because they require a relatively
long instruction format to hold the three address references. With two address
instructions, and for binary operations, one address must do double duty as both an
operand and a result. Thus, the instruction SUB Y, B carries out the calculation Y - B and
stores the result in Y. The two-address format reduces the space requirement but also
introduces some awkwardness. To avoid altering the value of an operand, a MOVE
instruction is used to move one of the values to a result or temporary location before
performing the operation. Our sample program expands to six instructions.
Simpler yet is the one-address instruction. For this to work, a second address must be
implicit. This was common in earlier machines, with the implied address being a
processor register known as the accumulator (AC). The accumulator contains one of the
operands and is used to store the result. In our example, eight instructions are needed to
accomplish the task.
It is, in fact, possible to make do with zero addresses for some instructions. Zero- address
instructions are applicable to a special memory organization, called a stack. A stack is a last-
in-first-out set of locations. The stack is in a known location and, often, at least the top two
elements are in processor registers. Thus, zero-address instructions would reference the top
two Stack Elements.
.

5. Instruction Set Design

One of the most interesting and most analyzed, aspects of computer design is instruction set
design. The design of an instruction set is very complex, because it affects so many aspects of the
computer system. The instruction set defines many of the functions performed by the CPU and
thus has a significant effect on the implementation of the CPU. The instruction set is the
programmer's means of controlling the CPU. Thus, programmer requirements must be considered
in designing the instruction set. The most important design issues include the following:

These fundamental design issues include the following:

Operation repertoire: How many and which operations to provide, and how
complex operations should be
Data types: The various types of data upon which operations are performed
Instruction format: Instruction length (in bits), number of addresses, size of
various fields, and soon
Registers: Number of processor registers that can be referenced by instructions,
and their use
Addressing: The mode or modes by which the address of an operand is specified

II. Types of Operands

1. Numbers
All machine languages include numeric data types. Even in nonnumeric data processing,
there is a need for numbers to act as counters, field widths, and so forth.
Three types of numerical data are common in computers:
Binary integer or binary fixed point
Binary floating - point
Decimal
Although all internal computer operations are binary in nature, the human users of
the system deal with decimal numbers. Thus, there is a necessity to convert from
decimal to binary on input and from binary to decimal on output. The most common
representation for this purpose is packed decimal. With packed decimal, each decimal
digit is represented by a 4-bit code, in the obvious way, with two digits stored per
byte. Thus, 0 = 0000, 1 = 0001, … , 8= 1000, and 9 =1001.

2. Characters
A common form of data is text or character strings. While textual data are most
convenient for human beings, they cannot, in character form, be easily stored or
transmitted by data processing and communications systems. Such systems are
designed for binary data.
Today, the most commonly used character code in the International Reference
Alphabet (IRA), referred to in the United States as the American Standard Code for
Information Interchange (ASCII; see Appendix F). Each character in this code is
represented by a unique 7-bit pattern; thus, 128 different characters can be
represented.

3. Logical Data
Normally, each word or other addressable unit (byte, half word, and so on) is treated
as a single unit of data. It is sometimes useful, however, to consider an n-bit unit as
consisting of n 1-bit items of data, each item having the value 0 or 1. When data are
viewed this way, they are considered to be logical data. There are two advantages to
the bit-oriented view.
First, we may sometimes wish to store an array of Boolean or binary data items, in
which each item can take on only the values 1 (true) and 0 (false). With logical data,
memory can be used most efficiently for this storage. Second, there are occasions
when we wish to manipulate the bits of a data item.

III. Types of Operations

Data Transfer
The most fundamental type of machine instruction is the data transfer instruction. The
data transfer instruction must specify several things. First, the location of the source
and destination operands must be specified. Each location could be memory, a
register, or the top of the stack. Second, the length of data to be transferred must be
indicated. Third, as with all instructions with operands, the mode of addressing for
each operand must be specified.

Arithmetic
Most machines provide the basic arithmetic operations of add, subtract, multiply, and
divide. These are invariably provided for signed integer (fixed-point) numbers. Often
they are also provided for floating-point and packed decimal numbers. Other possible
operations include a variety of single-operand instructions; for
example,

Absolute: Take the absolute value of the operand.

Negate: Negate the operand.
Increment: Add 1 to the operand.
Decrement: Subtract 1 from the operand.

Logical

Most machines also provide a variety of operations for manipulating individual bits of a word or other
addressable units, often referred to as “bit twiddling.” These logical operations can be applied bitwise to n-
bit logical data units. Thus, if two registers contain the data
(R1) = 10100101
(R2) = 00001111 Then (R1)
AND (R2) = 00000101

Conversion
Conversion instructions are those that change the format or operate on the format of data. An example is
converting from decimal to binary or Shift and Rotate Operations.

Input/ Output
There are a variety of approaches taken, including isolated programmed I/O, memory- mapped
programmed I/O, DMA, and the use of an I/O processor. Many implementations provide only a few I/O
instructions, with the specific actions specified by parameters, codes, or command words.

System Control
System control instructions are those that can be executed only while the processor is in a certain
privileged state or is executing a program in a special privileged area of memory. Typically, these
instructions are reserved for the use of the operating system. Some examples of system control operations
are as follows. A system control instruction may read or alter a control register.

Transfer of Control
For all of the operation types discussed so far, the next instruction to be performed is the one that
immediately follows, in memory, the current instruction. However, a significant fraction of the
instructions in any program have as their function changing the sequence of instruction execution. For
these instructions, the operation performed by the processor is to update the program counter to contain
the address of some instruction in memory.
There are a number of reasons why transfer-of-control operations are required. Among the most
important are the following:

In the practical use of computers

Virtually all programs involve some decision making.
To compose correctly a large or even medium-size computer program is an exceedingly
difficult task.

IV. Assembly language

What is Assembly Language?

Each personal computer has a microprocessor that manages the computer's arithmetical, logical, and control
activities. Each family of processors has its own set of instructions for handling various operations such as getting
input from keyboard, displaying information on screen and performing various other jobs. These set of instructions
are called 'machine language instructions'.
A processor understands only machine language instructions, which are strings of 1's and 0's. However, machine
language is too obscure and complex for using in software development. So, the low-level assembly language is
designed for a specific family of processors that represents various instructions in symbolic code and a more
understandable form.
Advantages of Assembly Language
Having an understanding of assembly language makes one aware of −

 How programs interface with OS, processor, and BIOS;

 How data is represented in memory and other external devices;
 How the processor accesses and executes instruction;
 How instructions access and process data;
 How a program accesses external devices.
Other advantages of using assembly language are −
 It requires less memory and execution time;
 It allows hardware-specific complex jobs in an easier way;
 It is suitable for time-critical jobs;
 It is most suitable for writing interrupt service routines and other memory resident programs.

V. Types of Addressing Mode

Addressing Modes–
The term addressing modes refers to the way in which the operand of an instruction is specified. The addressing
mode specifies a rule for interpreting or modifying the address field of the instruction before the operand is actually
executed.
Addressing modes for 8086 instructions are divided into two categories:
1) Addressing modes for data
2) Addressing modes for branch
The 8086 memory addressing modes provide flexible access to memory, allowing you to easily access variables,
arrays, records, pointers, and other complex data types. The key to good assembly language programming is the
proper use of memory addressing modes.
An assembly language program instruction consists of two parts

IMPORTANT TERMS
 Starting address of memory segment.
 Effective address or Offset: An offset is determined by adding any combination of three address
elements: displacement, base and index.
 Displacement: It is an 8 bit or 16 bit immediate value given in the instruction.
 Base: Contents of base register, BX or BP.
 Index: Content of index register SI or DI.
According to different ways of specifying an operand by 8086 microprocessor, different addressing modes are used by
8086.
Addressing modes used by 8086 microprocessor are discussed below:

1. Immediate Addressing
In this mode data is present in address field of instruction .Designed like one address instruction format.
Note: Limitation in the immediate mode is that the range of constants are restricted by size of address
field.

Example: MOV AL, 35H (move the data 35H into AL register)

2. Direct Addressing
The operand’s offset is given in the instruction as an 8 bit or 16 bit displacement element. In
this addressing mode the 16 bit effective address of the data is the part of the instruction.
Here only one memory reference operation is required to access the data.

Example:ADD AL,[0301] //add the contents of offset address 0301 to AL

3. Indirect Addressing

Is a scheme in which the address specifies which memory word or register contains not the operand but the address
of the operand. For example: 1) LOAD R1, @100 Load the content of memory address stored at memory address
100 to the register R1.
In this mode address field of instruction contains the address of effective address.Here two references are required.
1st reference to get effective address.
2nd reference to access the data.
Based on the availability of Effective address, Indirect mode is of two kind:
1. Register Indirect: In this mode effective address is in the register, and corresponding register name will be
maintained in the address field of an instruction.
Here one register reference, one memory reference is required to access the data.
2. Memory Indirect: In this mode effective address is in the memory, and corresponding memory address will be
maintained in the address field of an instruction.
Here two memory reference is required to access the data.

4. Register Addressing

In register addressing the operand is placed in one of 8 bit or 16 bit general purpose registers.
The data is in the register that is specified by the instruction.
Here one register reference is required to access the data.

Example: MOV AX,CX (move the contents of CX register to AX register)

5. Register Indirect Addressing

In this addressing the operand’s offset is placed in any one of the registers BX,BP,SI,DI as specified in the
instruction. The effective address of the data is in the base register or an index register that is specified by the
instruction.
Here two register reference is required to access the data.

The 8086 CPUs let you access memory indirectly through a register using the register indirect addressing modes.

MOV AX, [BX](move the contents of memory location s

addressed by the register BX to the register AX)

6. Indexed addressing mode:

The operand’s offset is the sum of the content of an index register SI or DI and an 8 bit or 16 bit displacement.

Example:MOV AX, [SI +05]

7. Based Indexed Addressing:
The operand’s offset is sum of the content of a base register BX or BP and an index register SI or DI.

Example: ADD AX, [BX+SI]

VI .Instruction Formats
The physical and logical structure of computers is normally described in reference manuals provided with
the system. Such manuals explain the internal construction of the CPU, including the processor registers
available and their logical capabilities. They list all hardware-implemented instructions, specify their binary
code format, and provide a precise definition of each instruction. A computer will usually have a variety of
instruction code formats. It is the function of the control unit within the CPU to interpret each instruction
code and provide the necessary control functions needed to process the instruction.

The format of an instruction is usually depicted in a rectangular box symbolizing the bits of the instruction
as they appear in memory words or in a control register. The bits of the instruction are divided into groups
called fields.
The most common fields found in instruction formats are:
1 An operation code field that specifies the operation to be performed.
2. An address field that designates a memory address or a processor registers.
3. A mode field that specifies the way the operand or the effective address is determined.

Other special fields are sometimes employed under certain circumstances, as for example a field that gives
the number of shifts in a shift-type instruction.
The operation code field of an instruction is a group of bits that define various processor operations, such as
add, subtract, complement, and shift. The bits that define the e mode field of an instruction code specify a
variety of alternatives for choosing the operands from the given address.
Operations specified by computer instructions are executed on some data stored in memory or processor
registers, Operands residing in processor registers are specified with a register address. A register address is a
binary number of k bits that defines one of 2k registers in the CPU. Thus a CPU with 16 processor registers
R0 through R15 will have a register address field of four bits. The binary number 0101, for example, will
designate register R5.
Computers may have instructions of several different lengths containing varying number of addresses. The
number of address fields in the instruction format of a computer depends on the internal organization of its
registers. Most computers fall into one of three types of CPU organizations:

1 Single accumulator organization.

2 General register organization.
3 Stack organization

An example of an accumulator-type organization is the basic computer presented in Chap. 5. All operations
are performed with an implied accumulator register. The instruction format in this type of computer uses one
address field. For example, the instruction that specifies an arithmetic addition is defined by an assembly
language instruction as ADD.
Where X is the address of the operand. The ADD instruction in this case results in the operation AC ← AC +
M[X]. AC is the accumulator register and M[X] symbolizes the memory word located at address X.
An example of a general register type of organization was presented in Fig. 7.1. The instruction format in this
type of computer needs three register address fields. Thus the instruction for an arithmetic addition may be
written in an assembly language as
ADD R1, R2, R3
To denote the operation R1 ← R2 + R3. The number of address fields in the instruction can be reduced from
three to two if the destination register is the same as one of the source registers. Thus the instruction
ADD R1, R2
Would denote the operation R1 ← R1 + R2. Only register addresses for R1 and R2 need be specified in this
instruction.
Computers with multiple processor registers use the move instruction with a mnemonic MOV to symbolize a
transfer instruction. Thus the instruction
MOV R1, R2
Denotes the transfer R1 ← R2 (or R2 ← R1, depending on the particular computer). Thus transfer-type
instructions need two address fields to specify the source and the destination.
General register-type computers employ two or three address fields in their instruction format. Each address
field may specify a processor register or a memory word. An instruction symbolized by ADD R1, X
Would specify the operation R1 ← R + M [X]. It has two address fields, one for register R1 and the other for
the memory address X.
The stack-organized CPU was presented in Fig. 8-4. Computers with stack organization would have PUSH
and POP instructions which require an address field. Thus the instruction
PUSH X
Will push the word at address X to the top of the stack. The stack pointer is updated automatically.
Operation-type instructions do not need an address field in stack-organized computers. This is because the
operation is performed on the two items that are on top of the stack. The instruction
ADD
In a stack computer consists of an operation code only with no address field. This operation has the effect of
popping the two top numbers from the stack, adding the numbers, and pushing the sum into the stack. There
is no need to specify operands with an address field since all operands are implied to be in the stack.
Most computers fall into one of the three types of organizations that have just been described. Some
computers combine features from more than one organization structure. For example, the Intel 808-
microprocessor has seven CPU registers, one of which is an accumulator register As a consequence; the
processor has some of the characteristics of a general register type and some of the characteristics of a
accumulator type. All arithmetic and logic instruction, as well as the load and store instructions, use the
accumulator register, so these instructions have only one address field. On the other hand, instructions that
transfer data among the seven processor registers have a format that contains two register address fields.
Moreover, the Intel 8080 processor has a stack pointer and instructions to push and pop from a memory stack.
The processor, however, does not have the zero-address-type instructions which are characteristic of a stack-
organized CPU.
To illustrate the influence of the number of addresses on computer programs, we will evaluate the
arithmetic statement X = (A + B) ∗ (C + D)

VII. Types of Instruction

Using zero, one, two, or three address instruction. We will use the symbols ADD, SUB, MUL, and DIV
for the four arithmetic operations; MOV for the transfer-type operation; and LOAD and STORE for
transfers to and from memory and AC register. We will assume that the operands are in memory addresses
A, B, C, and D, and the result must be stored in memory at address X.

A. ZERO-ADDRESS INSTRUCTIONS / STCK BASED

A stack-organized computer does not use an address field for the instructions ADD and MUL. The PUSH
and POP instructions, however, need an address field to specify the operand that communicates with the
stack. The following program shows how
X = (A + B) ∗ (C + D) will be written for a stack organized computer.
(TOS stands for top of stack)
PUSH A TOS ← A
PUSH B TOS ← B
ADD TOS ← (A + B)
PUSH C TOS ← C
PUSH D TOS ← D
ADD TOS ← (C + D)
MUL TOS ← (C + D) ∗ (A + B)
POP X M [X] ← TOS
To evaluate arithmetic expressions in a stack computer, it is necessary to convert the expression into
reverse Polish notation. The name “zero-address” is given to this type of computer because of the absence
of an address field in the computational instructions

B. ONE-ADDRESS INSTRUCTIONS / ACCUMULATOR BASED

One-address instructions use an implied accumulator (AC) register for all data manipulation. For
multiplication and division there is a need for a second register. However, here we will neglect the second and
assume that the AC contains the result of tall operations.
The program to evaluate X = (A + B) ∗ (C + D) is
LOAD A AC ← M [A]
ADD B AC ← A [C] + M [B]
STORE T M [T] ← AC
LOAD C AC ← M [C]
ADD D AC ← AC + M [D]
MUL T AC ← AC ∗ M [T]
STORE X M [X] ← AC
All operations are done between the AC register and a memory operand. T is the address of a temporary
memory location required for storing the intermediate result.

C. TWO-ADDRESS INSTRUCTIONS
Two address instructions are the most common in commercial computers. Here again each address field can
specify either a processor register or a memory word.
The program to evaluate X = (A + B) ∗ (C + D) is as follows:
MOV R1, A R1 ← M [A]
ADD R1, B R1 ← R1 + M [B]
MOV R2, C R2 ← M [C]
ADD R2, D R2 ← R2 + M [D]
MUL R1, R2 R1 ← R1∗R2
MOV X, R1 M [X] ← R1
The MOV instruction moves or transfers the operands to and from memory and processor registers. The first
symbol listed in an instruction is assumed to be both a source and the destination where the result of the operation
is transferred.

D.THREE-ADDRESS INSTRUCTIONS
Computers with three-address instruction formats can use each address field to specify either a
processor register or a memory operand.
The program in assembly language that evaluates X = (A + B) ∗ (C + D) is shown below, together with
comments that explain the register transfer operation of each instruction.

ADD R1, A, B R1 ← M [A] + M [B]

ADD R2, C, D R2 ← M [C] + M [D]
MUL X, R1, R2 M [X] ← R1 ∗ R2
It is assumed that the computer has two processor registers, R1 and R2. The symbol M [A] denotes the
operand at memory address symbolized by A.
The advantage of the three-address format is that it results in short programs when evaluating arithmetic
expressions. The disadvantage is that the binary-coded instructions require too many bits to specify three
addresses. An example of a commercial computer that uses three-address instructions is the Cyber 170. The
instruction formats in the Cyber computer are restricted to either three register address fields or two register
address fields and one memory address field.

VIII .Instruction Execution

The basic function performed by a computer is execution of a program, which

consists of a set of instructions stored in memory. The processor does the
actual work by executing instructions specified in the program
Instruction processing consists of two steps: The processor reads (fetches) instructions
from memory one at a time and executes each instruction. Program execution consists
of repeating the process of instruction fetch and instruction execution.
Basic Instruction Cycle:
i. Fetch Cycle
ii. Execution Cycle

Fig.1.2 Basic Instruction Cycle

 At the beginning of each instruction cycle, the processor fetches an instruction from
memory. In a typical processor, a register called the program counter(PC) holds the
address of the instruction to be fetched next. The processor always increments the PC
after each instruction fetch so that it will fetch the next instruction in sequence.
 The fetched instruction is loaded into a register in the processor known as the
instruction register (IR). The instruction contains bits that specify the action the
processor is to take. The processor interprets the instruction and performs
the required action. In general, these actions fall into four categories

1. Processor-memory: Data may be transferred from processor to memory or from

memory to processor.
2. Processor-I/O: Data may be transferred to or from a peripheral device by
transferring between the processor and an I/O module.
3. Data processing: The processor may perform some arithmetic or logic operation on
data.
4. Control: An instruction may specify that the sequence of execution be altered. For
example, the processor may fetch an instruction from location 149, which specifies that the
next instruction be from location 182. The processor will remember this fact by setting the
program counter to 182.Thus, on the next fetch cycle, the instruction will be fetched from
location 182 rather than 150
Consider a simple example using a hypothetical machine that includes the characteristics
listed in Figure 3.4. The processor contains a single data register, called an accumulator
(AC).

Fig 2.3 Example of Program Execution

Three instructions, which can be described as three fetch and three execute cycles, are
required:
The PC contains 300, the address of the first instruction. This instruction (the value 1940 in
hexadecimal) is loaded into the instruction register IR and the PC is incremented. Note that this
process involves the use of a memory address register
(MAR) and a memory buffer register (MBR). For simplicity, these intermediate registers are
ignored.
The first 4 bits (first hexadecimal digit) in the IR indicate that the AC is to be loaded. The
remaining 12 bits (three hexadecimal digits) specify the address (940) from which data are to be
loaded.
i. The next instruction (5941) is fetched from location 301 and the PC is incremented.
ii. The old contents of the AC and the contents of location 941 are added and the result
is stored in the AC.
iii. The next instruction (2941) is fetched from location 302 and the PC is incremented.

The contents of the AC are stored in location941

 A single instruction cycle with the following steps occurs:

i. Fetch the ADD instruction.
ii. Read the contents of memory location A into the processor.
iii. Read the contents of memory location B into the processor. In order that the
iv. contents of A are not lost, the processor must have at least two registers for
v. Storing memory values, rather than a single accumulator.
vi. Add the two values.
vii. Write the result from the processor to memory location A.

 The Instruction Cycle State Diagram states can be described as follows:

i. Instruction fetch (if): Read instruction from its memory location into the processor.
ii. Instruction operation decoding (I o d): Analyze instruction to determine
type of operation to be performed and operand(s) to be used.
iii. Operand address calculation (oac): If the operation involves reference to an
operand in memory or available via I/O, then determine the address of the
operand.
iv. Operand fetch (of): Fetch the operand from memory or read it in from I/O.
v. Data operation (do): Perform the operation indicated in the instruction.
vi. Operand store (on): Write the result into memory or out to I/O.
Instruction address calculation (iac): Determine the address of the next I
instruction to be executed. Usually, this involves adding a fixed number to the
address of the previous instruction. For example, if each instruction is 16 bits
long and memory is organized into 16-bit words, then add 1 to the previous
address. If, instead, memory is organized as individually addressable 8-bit bytes,
then add 2 to the previous address
Fig.2.4 Instruction Cycle State Diagram

 States in the upper part of Figure 3.6 involve an exchange between the processor and
either memory or an I/O module. States in the lower part of the diagram involveonly
internal processor operations.
 The oac state appears twice, because an instruction may involve a read, a write, orboth.
 Also note that the diagram allows for multiple operands and multiple results, because
some instructions on some machines require this. following sequence of states: iac, if,
iod, oac, of, oac, of, do, oac,os.

IX. Structure of Program

An assembly language program is a series of statements, which are either assembly language
instructions such as ADD and MOV, or statements called directives.
An instruction tells the CPU what to do, while a directive (also called pseudo-instructions) gives
instruction to the assembler. For example, ADD and MOV instructions are commands which the CPU
runs, while ORG and END are assembler directives. The assembler places the opcode to the memory
location 0 when the ORG directive is used, while END indicates to the end of the source code. A
program language instruction consists of the following four fields −
[ label: ] mnemonics [ operands ] [;comment ]
A square bracket ( [ ] ) indicates that the field is optional.
 The label field allows the program to refer to a line of code by name. The label fields cannot
exceed a certain number of characters.
 The mnemonics and operands fields together perform the real work of the program and
accomplish the tasks. Statements like ADD A , C & MOV C, #68 where ADD and MOV are the
mnemonics, which produce opcodes ; "A, C" and "C, #68" are operands. These two fields could
contain directives. Directives do not generate machine code and are used only by the assembler,
whereas instructions are translated into machine code for the CPU to execute.

1.0000 ORG 0H ; start (origin) at location 0

2 0000 7D25 MOV R5,#25H ;load 25H into R5
3.0002 7F34 MOV R7,#34H ;load 34H into R7
4.0004 7400 MOV A,#0 ;load 0 into A
5.0006 2D ADD A,R5 ;add contents of R5 to A
6.0007 2F ADD A,R7 ;add contents of R7 to A
7.0008 2412 ADD A,#12H ;add to A value 12 H
8.000A 80FE HERE: SJMP HERE ;stay in this loop
9.000C END ;end of asm source file
 The comment field begins with a semicolon which is a comment indicator.
 Notice the Label "HERE" in the program. Any label which refers to an instruction should be
followed by a colon.

X. Introduction to RISC & CISC Architecture

 RISC Vs CISC(Difference)

1. RISC Architecture
RISC (Reduced Instruction Set Computer) is used in portable devices due to its
power efficiency. For Example, Apple iPod and Nintendo DS. RISC is a type of
microprocessor architecture that uses highly-optimized set of instructions. RISC does
the opposite, reducing the cycles per instruction at the cost of the number of
instructions per program Pipelining is one of the unique feature of RISC. It is
performed by overlapping the execution of several instructions in a pipeline fashion.
It has a high performance advantage over CISC.
RISC processors take simple instructions and are executed within a clock cycle

2. RISC Characteristics(Properties)
Simple Instructions are used in RISC architecture.
RISC helps and supports few simple data types and synthesizes complex data types.
RISC utilizes simple addressing modes and fixed length instructions for pipelining.
RISC permits any register to use in any context.
One Cycle Execution Time
The amount of work that a computer can perform is reduced by separating “LOAD”
and “STORE” instructions.
RISC contains Large Number of Registers in order to prevent various
numbers of interactions with memory.
In RISC, Pipelining is easy as the execution of all instructions will be done in a
uniform interval of time i.e. one click.
In RISC, more RAM is required to store assembly level instructions.
Reduced instructions need a less number of transistors in RISC.
RISC uses Harvard memory model means it is Harvard Architecture.
A compiler is used to perform the conversion operation means to convert a high-
level language statement into the code of its form.

3. The Advantages of RISC Architecture

RISC architecture has a set of instructions ,so high-level language compilers can produce
more efficient code
It allows freedom of using the space on microprocessors because of its simplicity.
Many RISC processors use the registers for passing arguments and holding the local
variables.
RISC functions use only a few parameters, and the RISC processors cannot use the
call instructions, and therefore, use a fixed length instruction which is easy to pipeline.
The speed of the operation can be maximized and the execution time can be minimized.
Very less number of instructional formats, a few numbers of instructions and a few
addressing modes are needed.

4. The Disadvantages of RISC architecture

Mostly, the performance of the RISC processors depends on the programmer or

compiler as the knowledge of the compiler plays a vital role while changing the CISC
code to a RISC code
While rearranging the CISC code to a RISC code, termed as a code expansion, will
increase the size. And, the quality of this code expansion will again depend on the
compiler, and also on the machine’s instruction set.
The first level cache of the RISC processors is also a disadvantage of the RISC, in
which these processors have large memory caches on the chip itself. For feeding the
instructions, they require very fast memory systems.

5. CISC Architecture
The CISC approach attempts to minimize the number of instructions per program,
sacrificing the number of cycles per instruction. Computers based on the CISC
architecture are designed to decrease the memory cost. Because, the large programs need
more storage, thus increasing the memory cost and large memory becomes more
expensive. To solve these problems, the number of instructions per program can be
reduced by embedding the number of operations in a single instruction, thereby making
the instructions more complex.
Example:-IBM 370/168 , Intel 80486
6. CISC Characteristics(Properties)
Instruction-decoding logic will be Complex.
One instruction is required to support multiple addressing modes.
Less chip space is enough for general purpose registers for the instructions that are
0 operated directly on memory.
Various CISC designs are set up two special registers for the stack pointer,
handling interrupts , etc.
MUL is referred to as a “complex instruction” and requires the programmer for storing
functions.

7. Advantages of CISC architecture

Microprogramming is easy assembly language to implement, and less expensive than
hard wiring a control unit.
The ease of micro coding new instructions allowed designers to make CISC
machines upwardly compatible:
As each instruction became more accomplished, fewer instructions could be used to
implement a given task.
8. Disadvantages of CISC architecture

The performance of the machine slows down due to the amount of clock time taken by
different instructions will be dissimilar
Only 20% of the existing instructions is used in a typical programming event, even
though there are various specialized instructions in reality which are not even used
frequently.
The conditional codes are set by the CISC instructions as a side effect of each instruction
which takes time for this setting – and, as the subsequent instruction changes the
condition code bits – so, the compiler has to examine the condition code bits before this
happens.

References:
I. Computer Organization and Architecture author- WillamStallings
II. http://www.edgefxkits.com/blog/what-is-risc-and-cisc-architecture/

Ms. Shital Shinde

(Subject Co-ordinator)