OUTLINE

 3.1 Introduction
 What is an Instruction Set ?
 3.2 Machine Instruction Characteristics
 Elements of Machine Instruction
 Operand Locations
 Instruction Representation
CHAPTER 3  Instruction Types
THE CENTRAL PROCESSING UNIT  3.3 Instruction Set Design
Types of Operands
(CPU) 
 Types of Operations
 Addressing Mode
 Instruction Format
 3.4 Instruction Cycle Revisited
 3.5 Instruction Cycle Data Flow
1
 3.6 Processor Structure and Function
 Processor Organization
 Register Organization
2
 3.7 Reading Assignment

3.1 INTRODUCTION INTRODUCTION…

 Much of the computer architecture/organization is  Instruction set is a boundary where
hidden from a high level language programmer  Computer designer and computer programmer can view
the same machine
 Shouldn’t care what the underlying architecture really is

 From Designer’s Point of view

 What is an instruction set?  It provides the functional requirements for the CPU.
 the collection of different instructions that are understood Implementing the CPU is a task that in large part involves
by a CPU or that the CPU can execute implementing the machine instruction set.

 Machine Code  From Assembly Language Programmer’s Point of

 encoded in binary – for machines to work with view
 It enables to be aware of the register and memory
structure,
 For people: represent by assembly codes 3
 the types of data directly supported by the machine and 4
 text – for people to work with  the functioning of the ALU
3.2 MACHINE INSTRUCTION CHARACTERISTICS ELEMENTS OF A MACHINE INSTRUCTION
 The operation of the CPU is determined by the  Each instruction must contain all the information
instructions it executes required by the CPU for execution

 We will investigate  These elements are :

 the design of the instruction set  Operation code (Op code)
 The impact of the set on the design of the overall  Specifies the operation to be performed
computer system  Do this operation

 Source Operand(s) reference(s)

 Specifies a register or memory location of operand data
 With this/these operands
 An operation may involve one or more source operands
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 Inputs for the operation specified

ELEMENTS OF A MACHINE INSTRUCTION… OPERAND LOCATIONS

 Result Operand reference  Where Can Operands Be?
 Where the result of the operation should be placed ?  Source and result operands can be in one of the four
 Put the answer here
areas:
 Main memory
 Next Instruction reference  Memory address must be supplied

 From where to fetch the next instruction  CPU register

 When you have done that, do this...  Implicitly referenced, if only one register exist

 In most cases not explicitly stated in the instruction  Explicitly using its unique number, if more than one

 Implicitly the next instruction, the one that logically register exists
follows the current one in the program  Immediate

 Operand contained in the instruction being executed

 I/O device

 Specify the I/O device for the operation

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INSTRUCTION REPRESENTATION SIMPLE INSTRUCTION FORMAT
 With in a computer, each instruction is
represented by sequence of bits
 Each instruction has a unique bit pattern

 Instruction divided into fields

 Corresponding to the constituent elements of the
instruction
 E.g. A simple instruction format

 With most instruction set, more than one format is used

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INSTRUCTION REPRESENTATION… INSTRUCTION TYPES

 Difficult for the programmers to deal with binary  An instruction set must be functionally complete
representation of machine instruction
 Sufficient enough to express any of the instructions
from a high level language
 Hence, it is common to use a symbolic representation of
machine instruction
 Opcodes  Categories of instruction types
 Represented by abbreviations called mnemonics --- that indicate the
operation  Data processing
 Operands  Arithmetic and logic instructions
Also represented symbolically
Data storage


 Example
 Memory instructions
 ADD R, Y
 Data movement
 It is possible to write a machine language program in  I/O instructions
symbolic form  Control
 A simple program accepts this symbolic input ,convert opcode  Test and branch instructions
and operand references to binary form and construct binary 11 12
machine instruction  Program flow and control
3.3 INSTRUCTION SET DESIGN INSTRUCTION SET DESIGN …
 One of the most interesting and analyzed aspects  Most important issues related to the design of
of computer design instruction set includes:
 Operation repertoire
 A very complex task  How many ops?
 Because it affects so many aspects of the computer  What can they do?
system  How complex are they?
 Data Types
 Instruction set  Built-In Data types supported
 Boundary where computer designer and  Instruction formats
Computer programmer can view the same  How to encode as binary values
machine  Length of op code field
 Number of addresses
 Programmer’s means of controlling the CPU
 Registers
 Programmers requirement must be considered in designing  Number of CPU registers available
the instruction set Which operations can be performed on which registers?
13  14
 Addressing modes

TYPES OF OPERAND TYPES OF OPERATIONS

 Machine instructions operate on data  Different machines support different opcodes:
 Categories of data
 Numbers  Data Transfer
 Signed Integer / Unsigned Integer / Floating Point  Arithmetic
 Characters
 ASCII, Unicode etc.
 Logical
 Logical Data  Conversion
 Bits or flags
 A group of bit where each bit has information
 I/O
 Addresses  System Control
 Addresses are, in fact, a form of data

 In many cases, some calculation must be performed on the

 Transfer of Control
operand reference in an instruction to determine the
memory address
 In this context, addresses can be considered to be unsigned
integers

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 Note: The “type” of a unit of data is determined by the operation
being performed on it
DATA TRANSFER ARITHMETIC
 Most fundamental type of instructions  Performed by ALU
 Must specify the following things  Basic arithmetic operations provided by most
 Location of source and destination operands machines are:
 memory, register …  Add, Subtract, Multiply, Divide
 Length of data to be transferred  Signed Integer
 Full word, half word …  Floating point
 Addressing mode of each operand  May include
 E.g.  Increment
 Move, Store, Load, Push, Pop  Decrement
 In terms of CPU action  Negate
 data transfer operations are the simplest type  Absolute
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SHIFT AND ROTATE OPERATIONS

LOGICAL 0

logical
 Operations that manipulate individual bits of a word shift
 Bitwise operations
 AND, OR, exclusive-OR (XOR)
shift in 0
 NOT (one’s complement)
 In addition a variety of shifting and rotating functions
 Logical shift arithmetic
 Shifts bits of word either to the left or right
 On one end the bit shifted out is lost
shift
 Arithmetic shift keep sign !
 Treats the data as a signed integer and does not shift the sign
bit
 Rotate/Cyclic shift
 Preserves all of the bits being operated on rotate
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CONVERSION INPUT/OUTPUT
 Change the format of data or operate on the  Transfer data
format of data  from the computer to peripheral devices
 Binary to Decimal  From peripheral devices to the computer system
 ASCII to EBCDIC
 To be seen in detail in another chapter
 E.g. Binary to BCD
 binary 00001111 (1510)
 packed BCD 0001 0101
1 5

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SYSTEM CONTROL TRANSFER OF CONTROL

 Reserved for use by the operating system  Alter the flow of program
 Instructions executed while the processor is in
 i.e. change the sequence of instruction execution
certain privileged mode  Update the PC to a specific address
 Privileged instructions  Most common such type of operations are:

 CPU needs to be in specific state  Branch, Skip, Procedure call

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TRANSFER OF CONTROL… TRANSFER OF CONTROL…
 Branch Branch Instructions
 Also called jump instruction
 Its operand is the address of the next instruction to be fetched
and executed
 Two types of branches
 Conditional and Unconditional

 Conditional Branch
 A branch is made if certain condition is met
 E.g.
 BRP X
 Branch to instruction at location X if result is positive
 BRZ X
 Branch to instruction at location X if result is zero
 BRE R1,R2,X
 Branch to X if contents of R1 is equal to contents of R2

 Unconditional branch
 E.g. 25 26
 BR X
 Branch to instruction at location X

TRANSFER OF CONTROL … TRANSFER OF CONTROL …

 Skip
 Implies that the next instruction be skipped
 Contains an implied address
 Can be of two types:
 Unconditional
 Skip (i.e. unconditionally increment PC to skip the next
instruction)
 Conditional

 Test some condition and skip if met/satisfied

 E.g. Increment and skip next instruction if result is zero

ISZ R1  increment & skip if zero

Branch X  skip this if result was zero
ADD A
 Procedure call
 [Reading Assignment] 27 28
TRANSFER OF CONTROL … TRANSFER OF CONTROL …

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TRANSFER OF CONTROL … ADDRESSING MODES

 The manner in which each address field specify operand
location

 Notations:
 A = Contents of an address field in the instruction
 R = Contents of an address field in the instruction that refers to a register
 (X) = Contents of memory location X or register X
 EA =Effective address of the location containing the referenced operand

 Note:
 Virtually all computer architectures provide more than one
type addressing modes
 The processor can used different approaches to determine
which addressing mode is being used in a particular
instruction
 Different opcodes will use different addressing modes
31  One or more bits in the instruction format can be used as a mode field 32
 Determines which addressing mode is to be used
ADDRESSING MODES… IMMEDIATE ADDRESSING
 Types of addressing modes  The instruction itself contains the operands value
 Immediate  Operand is part of instruction
 Direct  Operand = A
 Indirect  E.g. ADD 5
 Register  Add 5 to contents of accumulator
 Register Indirect  5 is operand
 Displacement  No additional memory reference required after
 Stack the fetch of the instruction itself
 The value that can be specified is limited
 Size/value of the operand is limited/limited range

33
 Fast 34

IMMEDIATE ADDRESSING DIAGRAM DIRECT ADDRESSING

 Address field contains address of operand
 Effective address EA = A
 Operand = (A)
 E.g. ADD A
Opcode Operand  Add contents of memory location A to accumulator
 One more memory access needed to fetch the operand
 No additional calculations required to work out effective
address
 Number of memory locations that can be referenced,
limited, due to limited width of the field
 Limited address space
 Common on earlier generation of computers
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DIRECT ADDRESSING DIAGRAM INDIRECT ADDRESSING
Opcode A  A (the address field) refers to a memory location
Memory which contains the address of operand
 Multiple (two) memory accesses to find operand
 Fetch EA
 Fetch operand
 Access the memory twice, hence slower
 EA = (A)
Operand  Operand = ((A))
 E.g. ADD (A)
 Look in A, find address (A) and look there for operand
 Range of EA increased
 Large address space
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 2n ,where n = word length

INDIRECT ADDRESSING DIAGRAM REGISTER ADDRESSING

 Similar to direct addressing
Opcode A  The address field refers to a register than a main memory address
Memory  EA = R
 Operand = (R )
 Very small address field needed
 Shorter instructions
 Faster instruction fetch
Operand
 No memory access required
 Very fast execution
 Very limited address space
 Small number of registers can be referenced
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REGISTER ADDRESSING DIAGRAM REGISTER INDIRECT ADDRESSING
 Similar to indirect addressing mode
Opcode R  Operand is in memory pointed to by contents of
Registers
register R
 EA = (R)

 Operand =((R ))

 Large address space (2n)

Operand  Where n is the width of the register

 Address space limitation overcome
 Uses one less memory access than indirect
addressing
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REGISTER INDIRECT ADDRESSING

DIAGRAM DISPLACEMENT ADDRESSING

Opcode R  Very powerful addressing mode

Memory  Combines
 direct addressing and
Registers  Register indirect addressing
 Instruction needs to have two address fields
 At least one of which is explicit
Operand  EA = A + (R)
 Address field hold two values
 A = base value
 R = register that holds displacement
43  or vice versa 44
DISPLACEMENT ADDRESSING DIAGRAM RELATIVE ADDRESSING
 A version of displacement addressing mode
Instruction  Implicitly references the PC register
Opcode R A  R = Program counter, PC
Memory  EA = A + (PC)

Registers  Saves bits

+ Operand

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BASE-REGISTER ADDRESSING INDEXED ADDRESSING

 Referenced register contains memory address  Address field contains memory address
 R holds pointer to base address  A = base
 The referenced register contains a displacement
 Address field contains the displacement from from that address
that address  R = displacement
 A holds displacement  EA = A + ( R )
 Good for accessing arrays and performing
 Exploits locality of memory references iterative operations
 Auto indexing
 increment and decrement

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INDEXED ADDRESSING… STACK ADDRESSING
 Combinations  A stack
 Indirect addressing with indexing  The stack mode of addressing is a form of implied
addressing
 The machine instructions need not include a memory
 Post indexing reference but implicitly operate on the top of the
 The indexing performed after the indirection stack
 EA = (A) + (R)
 Good to access a block of data of a fixed format

 Pre indexing
 The indexing performed before the indirection
 EA = (A+(R))
 Used to construct a multiway branch table 49 50

ADDRESSING MODES SUMMARY INSTRUCTION FORMAT

 It defines the layout of the bits of an instruction,
in terms of its constituent parts

 More that one format used in a given instruction

set

 What are the factors affecting the instruction

format ?
 READING ASSIGNMENT!!!

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3.4 INSTRUCTION CYCLE REVISITED INSTRUCTION CYCLE ,REVISED …
 Instruction cycle so far consists of the following  Indirect addressing
sub cycles:  May require memory access to fetch operands
 Fetch  Indirect addressing requires more memory accesses
 Execute  Can be thought of as additional instruction subcycle
 Interrupt

 Additional sub cycle to be added:

 Indirect cycle

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3.5 INSTRUCTION CYCLE DATA FLOW DATA FLOW (INSTRUCTION FETCH)

 The exact sequence of events during an  Fetch
instruction cycle depends on the design of the  PC contains address of next instruction
CPU  Address moved to MAR
 Address placed on address bus
 In general terms, assuming a CPU that employs  Control unit requests memory read
the following registers  Result placed on data bus, copied to MBR, then to IR
 MAR  Meanwhile PC incremented by 1
 MBR
 PC
 IR

 The possible Data Flow is indicated next

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DATA FLOW (FETCH DIAGRAM) DATA FLOW (DATA FETCH)
 IR is examined
 If indirect addressing, indirect cycle is performed
 Right most N bits of MBR transferred to MAR
 Control unit requests memory read
 Result (address of operand) moved to MBR

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DATA FLOW (INDIRECT DIAGRAM) DATA FLOW (EXECUTE)

 May take many forms
 Depends on instruction being executed

 May include
 Memory read/write
 Input/Output
 Register transfers
 ALU operations

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DATA FLOW (INTERRUPT) DATA FLOW (INTERRUPT DIAGRAM)
 Simple and Predictable
 Current PC saved to allow resumption after
interrupt
 Contents of PC copied to MBR
 Special memory location (e.g. stack pointer)
loaded to MAR
 MBR written to memory
 PC loaded with address of interrupt handling
routine
 Next instruction (first of interrupt handler) can
be fetched
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3.6 PROCESSOR STRUCTURE AND

FUNCTION PROCESSOR ORGANIZATION…
 Processor Organization  Simplified view of a CPU
 To understand the organization of the CPU, recall  Indicates its connection to the system via the system
the requirements placed on the CPU: bus
 Fetch instruction
 Interpret instruction
 Fetch data

 Process data

 Write data

 To do all these things

 Processor needs to store data temporarily
 Temporary data storage locations --- Registers --- are

needed 63 64
PROCESSOR ORGANIZATION… REGISTER ORGANIZATION
 Detailed view of a CPU  Registers
 Indicates  CPU must have some working space
 Data transfer and logic control paths  Temporary storage
 Internal processor bus  Top level of memory hierarchy
 Used to transfer data b/n the ALU and various registers
 Number and function vary between processor designs
 One of the major design decisions

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REGISTER ORGANIZATION… USER VISIBLE REGISTERS

 Registers classified into two groups:  Can be categorized as follows:
 User visible registers:  General purpose registers
 Can be referenced by assembly language instructions  Data registers
 Address registers
 Control and status registers:  Condition codes
 Used by control unit to control the operation of the CPU

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USER VISIBLE REGISTERS… USER VISIBLE REGISTERS…
 General Purpose Registers  Address registers
 Can be assigned variety of function by the  Hold addresses
programmer  Can be
 May be true general purpose  General purpose or
 May be restricted  Devoted to particular addressing mode
 Index registers, stack pointer, segment register
 May be used for data or addressing

 Data Registers
 Used only to hold data
 Accumulator

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CONDITION CODES CONTROL & STATUS REGISTERS

 Sets of individual bits , also called flags  Refers to different registers employed to control
 Each bit set by CPU hardware as the result of the operation of the CPU
operations:  Most not visible to the user
 E.g. Arithmetic operation results could be
Positive, negative, zero, overflow
Register essential during instruction cycle are


 Can be read (implicitly) by programs  Program Counter (PC)
 e.g. Jump if zero  Instruction Register (IR)
 Can not (usually) be set by programs  Memory Address Register (MAR)
 Memory Buffer Register (MBR)

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CONTROL & STATUS REGISTERS…
 Program Status Word (PSW)
 A register that contain status information
 Usually contains
 Condition codes
 Status information
END of Chapter 3
 Common fields or flags include
 Sign, zero, carry, equal, overflow, supervisor, interrupt
enable/disable

 Note that CPU design and Operating system

design are closely linked
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