Syllabus:

Basic interfacing concept, interfacing I/O devices like keyboard, LED display; 8085
interrupt, D/A and A-D converters, 8255A programmable peripheral interface, 8253
programmable interval timer, basic concept of serial I/O, software-controlled
asynchronous serial I/O, SID, SOD, hardware -controlled serial I/O using
Programmable chips.

Microprocessor - I/O Interfacing Overview

In this chapter, we will discuss Memory Interfacing and IO Interfacing with 8085.

Interface is the path for communication between two components. Interfacing is of two
types, memory interfacing and I/O interfacing.

Memory Interfacing
When we are executing any instruction, we need the microprocessor to access the memory
for reading instruction codes and the data stored in the memory. For this, both the memory
and the microprocessor requires some signals to read from and write to registers.

The interfacing process includes some key factors to match with the memory requirements
and microprocessor signals. The interfacing circuit therefore should be designed in such a
way that it matches the memory signal requirements with the signals of the microprocessor.

IO Interfacing
There are various communication devices like the keyboard, mouse, printer, etc. So, we
need to interface the keyboard and other devices with the microprocessor by using latches
and buffers. This type of interfacing is known as I/O interfacing.

Block Diagram of Memory and I/O Interfacing

8085 Interfacing Pins
Following is the list of 8085 pins used for interfacing with other devices −

 A15 - A8 (Higher Address Bus)

 AD7 - AD0(Lower Address/Data Bus)
 ALE
 RD
 WR
 READY

Ways of Communication − Microprocessor with the Outside

World?
There are two ways of communication in which the microprocessor can connect with the
outside world.

 Serial Communication Interface

 Parallel Communication interface

Serial Communication Interface − In this type of communication, the interface gets a

single byte of data from the microprocessor and sends it bit by bit to the other system
serially and vice-a-versa.

Parallel Communication Interface − In this type of communication, the interface gets a

byte of data from the microprocessor and sends it bit by bit to the other systems in
simultaneous (or) parallel fashion and vice-a-versa.
Interrupts in 8085
Interrupt Service Routine (ISR)

There are five interrupt signals in the 8085 microprocessors:

1. TRAP: The TRAP interrupt is a non-maskable interrupt that is generated by an

external device, such as a power failure or a hardware malfunction. The TRAP
interrupt has the highest priority and cannot be disabled.
2. RST 7.5: The RST 7.5 interrupt is a maskable interrupt that is generated by a software
instruction. It has the second highest priority.
3. RST 6.5: The RST 6.5 interrupt is a maskable interrupt that is generated by a software
instruction. It has the third highest priority.
4. RST 5.5: The RST 5.5 interrupt is a maskable interrupt that is generated by a software
instruction. It has the fourth highest priority.
5. INTR: The INTR interrupt is a maskable interrupt that is generated by an external
device, such as a keyboard or a mouse. It has the lowest priority and can be disabled.

Interrupt are classified into following groups based on their parameter −

 Vector interrupt − In this type of interrupt, the interrupt address is known to the
processor. For example: RST7.5, RST6.5, RST5.5, TRAP.
 Non-Vector interrupt − In this type of interrupt, the interrupt address is not known
to the processor so, the interrupt address needs to be sent externally by the device
to perform interrupts. For example: INTR.
 Maskable interrupt − In this type of interrupt, we can disable the interrupt by
writing some instructions into the program. For example: RST7.5, RST6.5, RST5.5.
 Non-Maskable interrupt − In this type of interrupt, we cannot disable the interrupt
by writing some instructions into the program. For example: TRAP.
 Software interrupt − In this type of interrupt, the programmer has to add the
instructions into the program to execute the interrupt. There are 8 software
interrupts in 8085, i.e. RST0, RST1, RST2, RST3, RST4, RST5, RST6, and RST7.
 Hardware interrupt − There are 5 interrupt pins in 8085 used as hardware
interrupts, i.e. TRAP, RST7.5, RST6.5, RST5.5, INTA.

8255A - Programmable Peripheral

Interface
The 8255A is a general purpose programmable I/O device designed to
transfer the data from I/O to interrupt I/O under certain conditions as
required. It can be used with almost any microprocessor.
It consists of three 8-bit bidirectional I/O ports (24I/O lines) which can be
configured as per the requirement.

Ports of 8255A
8255A has three ports, i.e., PORT A, PORT B, and PORT C.

 Port A contains one 8-bit output latch/buffer and one 8-bit input buffer.
 Port B is similar to PORT A.
 Port C can be split into two parts, i.e. PORT C lower (PC0-PC3) and PORT C upper
(PC7-PC4) by the control word.

These three ports are further divided into two groups, i.e. Group A includes PORT A and
upper PORT C. Group B includes PORT B and lower PORT C. These two groups can be
programmed in three different modes, i.e. the first mode is named as mode 0, the second
mode is named as Mode 1 and the third mode is named as Mode 2.

Operating Modes
8255A has three different operating modes −

 Mode 0 − In this mode, Port A and B is used as two 8-bit ports and Port C as two 4-
bit ports. Each port can be programmed in either input mode or output mode where
outputs are latched and inputs are not latched. Ports do not have interrupt
capability.
 Mode 1 − In this mode, Port A and B is used as 8-bit I/O ports. They can be
configured as either input or output ports. Each port uses three lines from port C as
handshake signals. Inputs and outputs are latched.
 Mode 2 − In this mode, Port A can be configured as the bidirectional port and Port B
either in Mode 0 or Mode 1. Port A uses five signals from Port C as handshake signals
for data transfer. The remaining three signals from Port C can be used either as
simple I/O or as handshake for port B.

Features of 8255A
The prominent features of 8255A are as follows −

 It consists of 3 8-bit IO ports i.e. PA, PB, and PC.

 Address/data bus must be externally demux'd.
 It is TTL compatible.

It has improved DC driving capability.

Intel 8253 - Programmable Interval Timer
The Intel 8253 and 8254 are Programmable Interval Timers (PTIs) designed for
microprocessors to perform timing and counting functions using three 16-bit registers. Each
counter has 2 input pins, i.e. Clock & Gate, and 1 pin for “OUT” output. To operate a
counter, a 16-bit count is loaded in its register. On command, it begins to decrement the
count until it reaches 0, then it generates a pulse that can be used to interrupt the CPU.

Difference between 8253 and 8254

The following table differentiates the features of 8253 and 8254 −

8253 8254

Its operating frequency is 0 - 10

Its operating frequency is 0 - 2.6 MHz
MHz

It uses N-MOS technology It uses H-MOS technology

Read-Back command is not available Read-Back command is available

Reads and writes of the same counter Reads and writes of the same
cannot be interleaved. counter can be interleaved.

Features of 8253 / 54

The most prominent features of 8253/54 are as follows −

 It has three independent 16-bit down counters.

 It can handle inputs from DC to 10 MHz.
 These three counters can be programmed for either binary or BCD count.
 It is compatible with almost all microprocessors.
 8254 has a powerful command called READ BACK command, which allows the user
to check the count value, the programmed mode, the current mode, and the current
status of the counter.

8255 Architecture
The following figure shows the architecture of 8255A −
Basic concept of serial I/O
Serial I/O (Input/Output) refers to the process of sending and receiving data one bit at a
time over a single wire or communication channel. There are two main types of serial
communication: asynchronous and synchronous. Additionally, there are software-controlled
and hardware-controlled approaches. Let's explore these concepts in the context of
microprocessor or microcontroller systems.
Asynchronous Serial I/O:
1. Overview:
 Asynchronous serial communication does not rely on a shared clock signal
between the sender and receiver. Instead, it uses start and stop bits to frame
each data byte.
2. Components:
 Transmitter:
 The transmitter sends a start bit, followed by the data bits (usually 8
bits), an optional parity bit for error checking, and stop bit(s).
 Receiver:
 The receiver looks for the start bit, samples the data bits, checks for
parity (if used), and waits for the stop bit(s).
Software-Controlled Asynchronous Serial I/O:
1. Software Handling:
 In software-controlled serial I/O, the microprocessor's software manages the
timing and control of data transmission and reception without relying on
specialized hardware.
2. Start and Stop Bit Timing:
 The software must carefully time the transmission and reception of each bit,
including the start and stop bits.
3. Serial Input Data (SID) and Serial Output Data (SOD):
 SID: Serial Input Data is the data line where the microprocessor receives serial
data.
 SOD: Serial Output Data is the data line where the microprocessor sends
serial data.
Hardware-Controlled Serial I/O Using Programmable Chips:
1. Overview:
 Hardware-controlled serial I/O involves the use of specialized chips or
modules to handle the timing and control aspects of serial communication.
2. 8251 USART (Universal Synchronous/Asynchronous Receiver Transmitter):
 The 8251 is a programmable chip commonly used for serial communication in
microprocessor systems.
 It can operate in both synchronous and asynchronous modes.
 The 8251 handles the generation of start and stop bits, allowing the
microprocessor to focus on other tasks.
3. Control Registers:
 The microprocessor communicates with the 8251 through control registers to
set parameters such as data format, baud rate, and enable/disable
transmission or reception.
4. Serial Input Data (SID) and Serial Output Data (SOD):
 SID: Serial Input Data is the data line where the microprocessor receives serial
data.
 SOD: Serial Output Data is the data line where the microprocessor sends
serial data.
Advantages of Hardware-Controlled Serial I/O:
1. Offloading Processor Burden:
 Hardware-controlled serial I/O offloads the microprocessor by handling the
timing and control aspects of communication, allowing the processor to focus
on other tasks.
2. Increased Reliability:
 Hardware-controlled communication is often more reliable and less prone to
timing errors compared to software-controlled methods.
3. Higher Speeds:
 Dedicated hardware can often achieve higher communication speeds
compared to software-controlled methods.