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DV Sujit

This document is a resume for Hema Sai Kumar Malla. It details his career objective, professional experience as a VLSI design and verification trainee, education background, skills in Verilog, SystemVerilog and UVM, and projects including developing a UVC for AXI 3.0 and designing an interrupt controller.

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11 views

DV Sujit

This document is a resume for Hema Sai Kumar Malla. It details his career objective, professional experience as a VLSI design and verification trainee, education background, skills in Verilog, SystemVerilog and UVM, and projects including developing a UVC for AXI 3.0 and designing an interrupt controller.

Uploaded by

5191421030
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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HEMA SAI KUMAR MALLA

Design and verification


[email protected] 8309306531

www.linkedin.com/in/hema-sai-kumar-malla18 Bengaluru

CAREER OBJECTIVE
To seek to obtain Design and verification engineer position in an esteemed organization that will allow to
showcase my developed skills, technology and contribute to the company's growth.

Professional Experience

VLSI Design and verification Trainee in VLSIGURU 06/2023 – 02/2024


Apprenticeship Bengaluru
This training provided me with a strong foundation in Verilog , System Verilog
and UVM and has equipped me with hands-on experience in various aspects.
including:
Developing verification plans and test benches
Writing test cases and assertions
Using simulation tools such as Questa Sim and Model Sim
Debugging and analyzing simulation results

Education

Bachelor of Technology (B. Tech) in ECE 08/2019 – 04/2023


Gayatri Vidya Parishad College for Degree and PG Courses Visakhapatnam
CGPA 6.01

Intermediate 06/2017 – 04/2019


Sri chaitanya jr college Visakhapatnam
CGPA 9.63

Secondary School Certificate (SSC) 06/2016 – 04/2017


A P Model school Anakapalli
CGPA 8.3

Skills
Verilog (HDL) System Verilog (HVL) UVM (TB Methodology) GVim (Editor)
Questa-sim, model-sim, EDA Playground (EDA Tools) AXI, APB (Basic Protocol Knowledge)
Digital Design, Debug (Other skills) C-Language (Basic programing language)
Projects

UVC Development for AXI 3.0 using UVM


AXI3.0 is an AMBA protocol used for high performance applications. It Support various features like out if
order transactions, overlapping transactions, burst transfer and few among various feature supports.
Responsibilities:
Read and understand specifications.
Develop UVC Architecture to be compatible with both master and slave behavior.
Develop AXI UVC component.
List down AXI features and develop test Plan.
Integrate AXI Master UVC with Slave UVC.

Design and verification of Interrupt controller


Interrupt controller is a design used to collect interrupts from various peripheral controllers and forwards
the interrupts to processor on priority basis. This continues till all interrupts are serviced by processor, it
interfaces with processor on one side using APB interface and another side with peripheral controller.
Responsibilities:
Understand how the interrupt logic works in processor and peripheral communication.
Develop RTL code
Develop Testbench and check design behavior

Design and verification of Synchronous FIFO and Asyn. FIFO using Verilog
FIFO (First In First Out) is used for data transfers which act as buffer. In Synchronous FIFO, write to FIFO
and read from FIFO will happen in same frequency. But in Asynchronous FIFO, write to FIFO and read
from FIFO will work on different frequencies. I have implemented both FIFO using Verilog coding and
verified.
Responsibilities:
Listing down design
features Develop RTL code
Setting up test bench and test Test plan development
Test case coding

Design and Verification of Memory with Front Door and Back Door Access
Memory is developed using DEPTH, WIDTH and SIZE parameters to implement a configurable memory.
The design and Test bench developed in Verilog language with multiple testcases.
Responsibilities
Develop memory Verilog code with different parameters.
Develop TB Architecture using front door and back door access tasks
Learn the concept of task usage in configurable test bench setup
Learn the concept of testcases in design verification
Develop functional tests and debug the same

Declaration
I solemnly declare that the information in this resume is true to the best of my knowledge and belief.
Hema sai kumar malla
24-04-2024

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