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Lalit Sam Cv

Lalit Mohan Joshi is an ASIC/IP/CPU Verification engineer with 7 years of experience, currently working as a Staff Engineer at Samsung focusing on GPU verification. He has a strong background in ARM architecture, various bus protocols, and verification methodologies using UVM/OVM. His educational qualifications include an M.Tech from the Indian Institute of Science and a B.Tech in Instrumentation & Control, along with notable academic achievements.

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5 views

Lalit Sam Cv

Lalit Mohan Joshi is an ASIC/IP/CPU Verification engineer with 7 years of experience, currently working as a Staff Engineer at Samsung focusing on GPU verification. He has a strong background in ARM architecture, various bus protocols, and verification methodologies using UVM/OVM. His educational qualifications include an M.Tech from the Indian Institute of Science and a B.Tech in Instrumentation & Control, along with notable academic achievements.

Uploaded by

himani
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Lalit Mohan Joshi

Contact:[email protected]
Mob: 09611520962

Profile


ASIC/IP/CPU Verification engineer with 7 years post graduate (M.Tech) experience .
Experience in testbench development with UVM/OVM using system verilog.

Experience in developing test plan ,coding and debugging test cases.

Experience in coding checkers ,transactors, functional coverage,DUT model and
assertions.

Strong understanding of ARMV7, V8(64 bit) architecture CPU .

Strong understanding of ARM V8 (CA53,CA57,CA72) CPU Subsystem.

Strong understanding of AXI ,ACE, APB , I2C protocols .

Strong understanding of System Verilog, Verilog ,VHDL .

Current status


Working as STAFF ENGINEER with Samsung research institute Bangalore for GPU verification Aug’17

Working on CROP (Color Rasterization operation) unit verification with UVM

a) Developing Testplan

b) Developing test cases

c) Code coverage analysis.


Worked asIC-Design ENGG-3 at BROADCOMPvt. Ltd.Bangalore since may 2015.
ARM 946 CPU Subsystem Verification .

Integarting AXI3 UVM VIP in TB.

Developing test plan .

Developing & debugging test cases

Coverage closure .

Zero –Delay GLS .




Formal Verification for ARM Coresight subsystem tie-offs using Zeroin.

Running Arm Dhrystone test on 0-Delay Netlist (ARM CA72 integration layer).

ARM SMMU 500 (System Memory Management Unit) Verification at Subsystem level.

Developing UVM RAL and Adapter for SMMU 500 .



 Hooking up the RAL and Adapter into Env .
Develpoing basic sequences and tests for register read/write.

ARM CCN502(Cache coherent Network) Verification at Subsystem level.

Developing UVM RAL and Adapter for CCN502.



 Hooking up the RAL and Adapter into Env .
 Develpoing basic sequences and tests for register read/write.
 


GIC (general interrupt controller) verification for CA53 CPU Sub-system.

Developing test plan .



Coding and debugging test cases.

Timer interrupt verification for CA53 CPU Sub-system.

Developing test plan



Coding and debugging test cases.



Address map verification for entire CA53 CPU sub-system.

Developing test plan

Coding and debugging test cases.

ARM CCN502(Cache coherent Network) Verification at Subsystem level.

Developing UVM RAL and Adapter for CCN502.



 Hooking up the RAL and Adapter into Env .
Develpoing basic sequences and tests for register read/write.


GIC (general interrupt controller) verification for CA53 CPU Sub-system.

Developing test plan .



Coding and debugging test cases.

Timer interrupt verification for CA53 CPU Sub-system.

Developing test plan



Coding and debugging test cases.



Address map verification for entire CA53 CPU sub-system.

Developing test plan

Coding and debugging test cases.


Worked as as a ASIC engineer atNVIDIAPvt. Ltd. Bangalore (May`12-May`15)

Unit level verification for DMU (DMA management unit ) with UVM .

Writing sequences for ACE LITE (AXI COHERENCY EXTENSION) transactions.

Integrating ACE VIP into test bench.

Developing and hooking up the transactors for the above RTL block.

Coding assertion for the interfaces.

Developing testplan .

Coding and integrating checkers .

Coding stimulus coverage.

Unit level verification for ACI (ARM CLUSTER INTERFACE ) with UVM .

.Writing sequences for ACE (AXI COHERENCY EXTENSION) transactions.

Integrating ACE VIP into test bench.

Developing and hooking up the transactors for the above RTL block.

Coding assertion for the interfaces.



Coding and integrating checkers




Unit level verification for ATB (Address translation block) with OVM .

Developing verification environment with monitor ,Referencefunction ,scoreboard.

Developing testplan and coding testcases.



64 bit ARM architecture CPU core verification

Individual contributor for debugging RTL failures.

Individual contributor for debugging Architecture failures.

Owner for all the RTL regressions at core level .

Functional coverage at core level.

Worked as a Design Verification engineer atQualcommIndia Pvt. Ltd. Bangalore. Jan’11.

Low power verification for Cortex A5 processor subsystem.




Writing assertion test plan .

Writing assertion codes.

Debugging test cases.
 Implementation of power down sequences

Test bench development for APB Slave verification



Coding Driver , Generator , interface , Monitor.

Coding and integrating assertions .
Hardware languages

VHDL ,Verilog ,System verilog .

Bus Protocols Known

ACE , AXI , APB ,I2C

Education

2008 to 2010
M.Tech(Instrument Technology) from Indian Institute of Science, Bangalore.
CGPA 6.0/8.0.

2003 to 2007
B.Tech (Instrumentation & Control ) from Bhartiya Vidya Peeths College of
Engineering Delhi with an aggregate of 70%.

2001 12th Standard from C.B.S.E with an aggregate of 72%.


1999 10th Standard from C.B.S.E with an aggregate of 78%.

Academic achievements

Secured All India Rank 09 in GATE examination 2008.



Got certificate of merit in National Mathematics Olympiad in class Xth.

Languages
Proficient in the following Languages:
English Hindi
Personal Details

Name : Lalit Joshi

Father's Name : S.P.Joshi.

Date of Birth : 16 /12/83

Sex : Male.

Marital status : Single.

Permanent address : 810 Timarpur double storey Delhi -110054


Declaration : I here by declare that the above mentioned information is correct up to my knowledge
and I bear the responsibility for the correctness of the above mentioned particulars.

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