PMAS Arid Agriculture University, Rawalpindi

University Institute of Information Technology

CSC-111 Digital Logic Design

Credit Hours: 3(2-3) Prerequisites:
Teacher: Dr. Rubina
Ghazal

Course Contents:
Introduction to concept and definitions used in digital logic design. Difference between analog and
digital system along with TTL and CMOS logics. Number systems, Boolean algebra and logic gates.
Analysis of gate level minimization with 2-level networks and Karnaugh maps. Combinational logic
systems that includes encoders, decoders, multiplexers, demultiplexers. Sequential logic systems are
gated latch and flip-flop i.e. SR, JK, D and T. Design of sequential modules consist of registers, shift
registers and universal registers along with counters i.e. synchronous and asynchronous counters.
Programmable devices: microcontroller, ROM and programmable arrays.
Course Objective:
The aim of this course is to introduce the students with the electronics components of modern digital
world that includes the combinational and sequential logic circuits analysis and design. Digital circuits
are merger of logic gates, encoder, decoder, multiplexers, registers, counters and programmable logic
arrays.
Teaching Methodology:
Lectures, Assignments, labs, Projects, Presentations, etc. Major component of the course should be
covered using conventional lectures. Practical contact hours are compulsory.
Courses Assessment:
Exams, Assignments, Quizzes, Project, Presentations. Course will be assessed using a combination of
written examinations and project(s). Practical evaluation, using rubrics, is encouraged and suggested
to make up around 20% of the course.
Reference Materials:
 Digital Design by Morris Mano (Book).
 Digital Fundamentals by Thomas Floyd (Book).
 DLD Lab Manual
 Software tools: Logisim or Lattice diamond software.

Course Learning Outcomes (CLOs):

At the end of the course the students will be able to: Domain BT Level* PLO
1. Acquire knowledge related to the concepts, tools
and techniques for the design of digital electronic C 1 1
circuits
2. Demonstrate the skills to design and analyze both
combinational and sequential circuits using a C 3 3
variety of techniques
3. Apply the acquired knowledge to simulate and
C 3 3
implement small-scale digital circuits
* BT= Bloom’s Taxonomy, C=Cognitive domain, P=Psychomotor domain, A= Affective domain
PMAS Arid Agriculture University, Rawalpindi
University Institute of Information Technology

Week/Lecture # Theory
Lecture-I Introduction to analog and digital systems.
Lecture-II Number system conversions. Conversion and compliments.
Introduction to Digital Experiments:
The objective of this lab is to introduce fundamental digital concepts.
The students are taught the idea of TTL Logic and TTL IC’s, Pin
Week 1 Practical-I Configurations and HEX inverters are introduced and tested. A
simple logic probe is required to be made from 7404 inverter IC,
which is then used with an oscilloscope to measure and test logic
levels.
Practical-II Contd.
Practical-III Contd.
Lecture-I Binary, octal & Hexa addition/subtraction.
Lecture-II Logic level. BCD addition. Even odd parity bits. ASCII codes.
Number Systems:
The objective of this lab is to introduce different number systems and
Week 2 Practical-I their conversions. Binary, Octal, Hex and BCD systems are
introduced and students are required to construct a circuit to convert
BCD to decimal using a 7447 decoder IC and seven segment display.
Practical-II Contd.
Practical-III Contd.
Lecture-I Logic gates, types, symbol & truth table.
Introduction to Boolean algebra & analysis, Identities of Boolean
Lecture-II
algebra & simplification.
Logic Gates:
The Objective of this lab is to introduce basic logic gates, their IC’s
and determination of their truth tables. The students are required to
Week 3
Practical-I formulate basic logic gates using NAND & NOR gates and
demonstrate the equivalency between NAND/negative OR and
NOR/negative AND. This lab also included Observing pulse wave
forms and calculating propagation delay.
Practical-II Contd.
Practical-III Contd.
Standard forms min-terms, max-terms, sum of product (SOP) and
Lecture-I
product of sum (POS).
Logic operations. Introduction to Karnaugh-map. Two, three & four
Lecture-II
variable k-map simplification.
TTL Specifications:
The objective of this lab is to introduce TTL Specifications and
Week 4
describe the static and electrical specifications for TTL logic,
Practical-I
including input and output voltage, input and output current, and noise
margin. The students are also required to measure the transfer curve
for an inverter IC
Practical-I Contd.
Practical-III Contd.
PMAS Arid Agriculture University, Rawalpindi
University Institute of Information Technology

Lecture-I Two, three & four variable k-map manipulation.

Two level implementation and selection of prime implicates and
Lecture-II
Don’t care conditions (two, three & four variable k- map).
Boolean Laws & DeMorgan’s Theorem:
The Objective of this lab is to introduce and use CMOS logic to verify
Week 5 experimentally several rules of boolean algebra. Also to
Practical-I
Experimentally determine the truth table for circuit with 3 input
variables and using De-morgan’s theorem to prove algebraically the
equivalency of circuits
Practical-II Contd.
Practical-III Contd.
Lecture-I NAND & NOR as Universal gates.
AND, OR, NOT implementation using NAND & NOR gates.
Lecture-II
Combinational logic implementation using gates.
Combinational Logic Circuits:
The Objective of this lab is to introduce the concept of combinational
logic circuits and ways of simplifying using different methods which
Week 6
Practical-I includes Karnaugh Maps and boolean algebra. The students are
required to develop truth tables for combinational logic problems,
reading SOP expressions and plotting karnaugh maps and eventually
building and testing the circuits.
Practical-II Contd.
Practical-III Contd.
Lecture-I Asynchronous and Synchronous circuits
Lecture-II Combinational Logic Design
Combinational Logic Using Multiplexers and De-Multiplexers:
The objective of this lab is to introduce Multiplexers and De-
Week 7 Practical-I multiplexers and their IC Equivalents. The students are required to
implement and complete circuits for a parity generator using a data
selector and a traffic light decoder using a De-multiplexer
Practical-II Contd.
Practical-III Contd.
Lecture-I Combinational Logic Design
Lecture-II Combinational Functions & Circuits
Week 8 Practical-I 4 way traffic light system using demultiplexer
Practical-II Contd.
Practical-III Contd.
MidTerm Exam
Lecture-I Design procedure for multilevel circuits.
Lecture-II Design procedure for multilevel circuits.
Week 9 Practical-I Implementation of half adder
Practical-II Contd.
Practical-III Contd.
Week 10 Lecture-I Half, full and parallel adder.
PMAS Arid Agriculture University, Rawalpindi
University Institute of Information Technology

Lecture-II Half and full subtractor.

Practical-I Implementation of full adder and subtractor
Practical-II Contd.
Practical-III Contd.
Lecture-I Encoder, decoder and magnitude comparator.
Lecture-II Multiplexer, demultiplexer and ROM.
Week 11 Practical-I Implementation of encoder and decoder.
Practical-II Contd.
Practical-III Contd.
Lecture-I Sequential logic circuits implementation.
Lecture-II Sequential logic circuits implementation.
The D Latch and D Flip Flop:
The objective of this lab is to introduce Latches and Flip flops and
their IC equivalents. The students are required to demonstrate how a
Week 12 Practical-I
latch can debounce and SPDT switch. Also they are instructed to
construct and test D-latch and D Flip flops and investigate several
application circuits for both like a Serial Parity Tester
Practical-II Contd.
Practical-III Contd.
Lecture-I Flip Flop and their types. Clock.
Lecture-II Triggering of Flip Flops.
The J-K Flip flop:
The objective of this lab is to introduce the concept of edge triggered
and pulse triggered flip flops and test various configurations for a J-K
Week 13 Practical-I
flip flop, including the asynchronous and synchronous inputs. The
students are required to implement a ripple counter by wiring a J-K
Flip Flop and measure the propagation delay of a flip flop.
Practical-II Contd.
Practical-III Contd.
Lecture-I Conversion of Flip Flops.
Lecture-II Registers and their types. Serial addition and shift registers.
Week 14 Practical-I Simulation of design of half and full adder
Practical-II Contd.
Practical-III Contd.
Lecture-I Uni and bi-directional registers.
Lecture-II Universal shift registers.
Week 15 Practical-I Simulation of flip flops
Practical-II Contd.
Practical-III Contd.
Lecture-I Introduction to counters. Ripple counter.
Lecture-II Synchronous and asynchronous counters.
Week 16 Practical-I Simulation of counters
Practical-II Project demo.
Practical-III Project demo.
PMAS Arid Agriculture University, Rawalpindi
University Institute of Information Technology

Final term Exam