Syllabus for Digital Logic Design
Syllabus for Digital Logic Design
ECTS 5
Contact Hours (per Lecture Tutorial Practice or Laboratory Home study
week) 2 1 2 5
Target Groups: 4th year Section: 1 & 2 Semester: I Academic Year: 2024 G.C
Convert between decimal, binary, octal, and hexadecimal
number systems.
Differentiate different Codes in digital system.
Perform two-level logic minimization using Boolean algebra
and Karnaugh maps minimization method.
Analyze the properties and realization of the various logic
gates.
Perform binary addition and subtraction.
Implement the Boolean Functions using NAND and NOR
Course Objectives
gates.
Incorporate medium scale integrated circuits, like
decoders, encoders, multiplexers, etc., into circuit design.
Differentiate and Design Combinational and Sequential
circuits.
Design and analyze clocked sequential circuits.
Use various types of latches and flip-flops to build binary
memory and counters.
Perform asynchronous and synchronous sequential logic
1
analysis
2
4.3. Implementing Combinational logic Universal property
of NAND and NOR gates
4.4. Adders, decoders, encoders, multiplexers and de
multiplexers
Chapter Five: Sequential Circuit
5.1.Flip flops
5.1.1 Latches
5.1.2 Edge triggered flip flops
5.1.3 Master slave flip flops
5.1.4 Applications
5.2 Counters
Week
15Hrs 5.2.1 Synchronous counters
12,13,14
5.2.2 Asynchronous counters
5.2.3 Up/down counters
5.2.4 Design of synchronous counters
5.3 Shift registers
5.3.1 Basic shift registers
5.3.2 Serial in serial out registers
5.3.3 Serial in parallel out Registers
Pre-requisites ECEg3073-Applied Electronics II
Year/Semester III/II
Status of Course Compulsory
Teaching & Learning Lectures, laboratories, group discussions, Exercises and
Methods Assignments
Continuous Assessment (Quiz’s, Test Assignments/Project
Assessment Methods Laboratory report)........................................................50%
Final exam.................................................................... 50%
All students are expected to abide by the code of conduct of
students throughout this course.
Academic dishonesty, including cheating, fabrication, and
Course policies
plagiarism will not be tolerated.
Class activities will vary day to day, ranging from lectures to
discussions.
3
Students will be active participants in the course.
Students are required to submit and present the assignments
provided according to the time table indicated.
100% of class attendance is mandatory!
Every student should be on time for the session. Students are
not allowed to enter if they are late more than five minutes.
Active participation in the lab is essential.
Cell phones MUST be turned off before entering the lab.
[1] Morris M. Mano: Digital Design (3rd Edition)