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UNIT-II
Arithmetic
The digital computers manipulate data to produce results necessary for the solution
of arithmetic computational problems. These instructions perform arithmetic calculations
and processing data in a computer. The four basic arithmetic operations are
1. addition
2. subtraction
3. multiplication
4. division
o An arithmetic processor is the part of a processor unit that executes arithmetic
operations.
o An arithmetic instruction may specify binary or decimal data.
o Each case the data may be in (ixed-point or (loating-point form.
o Fixed- point numbers may represent integers or fractions.
o Negative numbers may be in signed- magnitude or signed-complement representation.

 Addition and Subtraction

There are three ways of representing negative (ixed-point binary numbers:
1. signed-magnitude
2. signed-l's complement, or
3. signed-2's complement.
Most computers use the signed-2's complement representation when performing
arithmetic operations with integers. For (loating- point operations, most computers use the
signed-magnitude representation for the mantissa.

Addition and Subtraction with Signed-Magnitude Data

The procedure for adding or subtracting two signed binary numbers with paper and
pencil is simple and straight-forward. We designate the magnitude of the two numbers by
A and B. When the signed numbers are added or subtracted, we (ind that there are eight
different conditions to consider, depending on the sign of the numbers and the operation
performed.
o These conditions are listed in the (irst column of Table.
o The other columns in the table show the actual operation to be performed
with the magnitude of the numbers.
o The last column is needed to prevent a negative zero. In other words, when
two equal numbers are subtracted, the result should be +0 not –0.

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when the signs of A and B are identical (different), add the two magnitudes and
attach the sign of A to the result. When the signs of A and B are different (identical),
compare the magnitudes and subtract the smaller number from the larger. Choose the sign
of the result to be the same as A if A > B or the complement of the sign of A if A < B. If the
two magnitudes are equal, subtract B from A and make the sign of the result positive. The
two algorithms are similar except for the sign comparison
Addition Algorithm
The addition algorithm speci(ies that:

o If the signs of A and B are the same, add both the magnitudes and put the sign of A
to the result, as shown in the table.
o Compare both the magnitudes and subtract the small number from the greater
number when the signs of A and B disagree.
o In cases where A > B, the output signs must be equal to P, or the complement of A's
sign in cases where A < B.
o Subtract B from A and change the sign of the output to positive when the two
magnitudes are equal.

Subtraction Algorithm
The subtraction algorithm states that:

o When the signs of A and B differ, the subtraction method says to add both the
magnitudes and put the sign of A to the result.
o Compare both the magnitudes and subtract the smaller number from the greater
number when the signs of A and B are the same.
o In cases where A > B, the output signs must be equal to P, or the complement of A's
sign in cases where A < B.
o Subtract B from A and change the sign of the output to positive when the two
magnitudes are equal.
Hardware Algorithm
The (lowchart for the hardware algorithm is presented in Figure.
o The two signs As, and Bs are compared by an exclusive-OR gate. If the
output of the gate is 0, the signs are identical; if it is 1, the signs are
different for an add operation, identical signs dictate that the magnitudes
be added.

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o For a subtract operation, different signs dictate that the magnitudes be added. The
magnitudes are added
o with a micro-operation EA<- A + B where EA is a register that combines E and A. The
carry in E after the addition constitutes an over(low if it is equal to 1 and it is
transferred into the add-over(low (lip-(lop AVF.
o The two magnitudes are subtracted if the signs are different for an add operation or
identical for a subtract operation.
o The magnitudes are subtracted by adding A to the 2's complement of B. No over(low
can occur if the numbers are subtracted.
o A 1 in E indicates that A ≥ B and the number in A is the correct result. If this number
is zero, the sign As must be made positive to avoid a –0. A 0 in E indicates that A < B.
For this case it is necessary to take the 2's complement of the value in A.
o This operation can be done with one micro-operation A<-A’ + 1. In other paths of the
(lowchart, the sign of the result is the same as the sign of A, so no change in As is
required.
o However, when A < B, the sign of the result is the complement of the original sign of
A. It is then necessary to complement As to obtain the correct sign.
o The (inal result is found in register A and its sign in As. The value in AVF provides an
over(low indication. The (inal value of E is immaterial.

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Hardware Implementation
It consists of registers A and B and sign (lip-(lops As and Bs. Subtraction is done by adding
A to the 2's complement of B. The output carry is transferred to (lip-(lop E, where it can be
checked to determine the relative magnitudes of the two numbers. The add-over(low (lip-
(lop AVF holds the over(low bit when A and B are added. The A register provides other
micro-operations that may be needed when we specify the sequence of steps in the
algorithm. 3 The addition of A plus B is done through the parallel adder. The S(sum) output
of the adder is applied to the input of the A register. The complementer provides an output
of B or the complement of B depending on the state of the mode control M. The
complementer consists of exclusive-OR gates and the parallel adder consists of full-adder
circuits. The M signal is also applied to the input carry of the adder. When M = 0, the output
of B is transferred to the adder, the input carry is 0, and the output of the adder is equal to
the sum A+B. When M = 1, the 2’s complement of B is applied to the adder the input carry
is 1, and output S = A + B’ — 1. This is equal to A plus the 2's complement of B, which is
equivalent to the subtraction A — B.

 De inition of Adder
• Component of a computer processor that adds two numbers sent from the
processing in
• structions.
• An adder is a circuit that sums the amplitudes of two input signals. A half-adder is
a group of connected logic gates that create a logic circuit, incapable of handling
addition for two numbers. A full-adder is a circuit that adds two binary numbers.
1. Half Adder : Half Adder is a combinational logic circuit which is designed by
connecting one EX-OR gate and one AND gate. The half adder circuit has two inputs: A and
B, which add two input digits and generates a carry and a sum.

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The output obtained from the EX-OR gate is the sum of the two numbers while that
obtained by AND gate is the carry. There will be no forwarding of carry addition because
there is no logic gate to process that. Thus, this is called the Half Adder circuit.
Logical Expression:
Sum = A XOR B
Carry = A AND B
Truth Table :

2. Full Adder: Full Adder is the circuit that consists of two EX-OR gates, two AND gates,
and one OR gate. Full Adder is the adder that adds three inputs and produces two outputs
which consist of two EX-OR gates, two AND gates, and one OR gate. The (irst two inputs
are A and B and the third input is an input carry as C-IN. The output carry is designated as
C-OUT and the normal output is designated as S which is SUM.

The equation obtained by the EX-OR gate is the sum of the binary digits. While the output
obtained by AND gate is the carry obtained by addition.

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Logical Expression:
SUM = (A XOR B) XOR Cin = (A ⊕ B) ⊕ Cin
CARRY-OUT = A AND B OR Cin(A XOR B) = A.B + Cin(A ⊕ B)

 Design of Fast adders

Fast adders are fundamental building blocks in digital circuits and are essential for
performing addition operations in computer processors and other digital systems. There
are several types of fast adders: Ripple Carry Adder (RCA), Carry Look-Ahead Adder (CLA),
and Carry Select Adder (CSA).

Ripple Carry Adder (RCA):

Ripple Carry Adder is the most basic form of an adder. In this adder, each bit's sum is
computed sequentially, and the carry from one bit is propagated to the next. While simple
to design, RCA is relatively slow due to the propagation delay of the carry signal.

Working of 4-bit Ripple Carry Adder

o Let’s take an example of two input sequences 0101 and 1010. These are
representing the A4 A3 A2 A1 and B4 B3 B2 B1.
o As per this adder concept, input carry is 0.
o When Ao & Bo are applied at 1st full adder along with input carry 0.
o Here A1 =1 ; B1=0 ; Cin=0
o Sum (S1) and carry (C1) will be generated as per the Sum and Carry equations of
this adder. As per its theory, the output equation for the Sum = A1⊕B1⊕Cin and
Carry = A1B1⊕B1Cin⊕CinA1
o As per this equation, for 1st full adder S1 =1 and Carry output i.e., C1=0.
o Same like for next input bits A2 and B2, output S2 = 1 and C2 = 0. Here the
important point is the second stage full adder gets input carry i.e., C1 which is the
output carry of initial stage full adder.
o Like this will get the (inal output sequence (S4 S3 S2 S1) = (1 1 1 1) and Output
carry C4 = 0
o This is the addition process for 4-bit input sequences when it’s applied to this
carry adder.

Carry Look-Ahead Adder (CLA):

Carry Look-Ahead Adder improves the speed of addition by generating carry signals for
each bit in parallel. It precomputes the carry for each bit based on a group of bits, reducing
the carry propagation delay. The carry look-ahead logic computes the carries
independently of the data bits.

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The Figure shows the full adder circuit used to add the operand bits in the ith column;
namely Ai & Bi and the carry bit coming from the previous column (Ci ).

In this circuit, the 2 internal signals Pi and Gi are given by:

Pi = Ai ⊕ Bi
Gi = Ai Bi
The output sum and carry can be de(ined as :
S i = P i ⊕ Ci
Ci+1 = Gi + Pi Ci

o Gi is known as the carry Generate signal since a carry (Ci+1) is generated whenever Gi =1,
regardless of the input carry (Ci).
o Pi is known as the carry propagate signal since whenever Pi =1, the input carry is propagated to
the output carry, i.e., Ci+1. = Ci (note that whenever Pi =1, Gi =0).
o Computing the values of Pi and Gi only depend on the input operand bits (Ai & Bi) as clear from
the Figure and equations.
o Computed values of all the Pi’s are valid one XOR-gate delay after the operands A and B
are made valid.
o Computed values of all the Gi’s are valid one AND-gate delay after the operands A and
B are made valid.
o The Boolean expression of the carry outputs of various stages can be written as follows:

Ci+1 = Gi + Pi Ci
Where i = 0 then
C1 = G0 + P0C0
Where i = 1 then
C2 = G1 + P1C1 = G1 + P1 (G0 + P0C0)
= G1 + P1G0 + P1P0C0
Where i = 2 then
C3 = G2 + P2C2
= G2 + P2G1 + P2P1G0 + P2P1P0C0
Where i = 3 then
C4 = G3 + P3C3
= G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0C0

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The 4-bit carry look-ahead (CLA) adder consists of 3 levels of logic:

o First level: Generates all the P & G signals. Four sets of P & G logic (each consists of
an XOR gate and an AND gate). Output signals of this level (P’s & G’s).

P Signals G Signals
P0 = A0 ⊕ B0 G0 = A0 B0
P1 = A1 ⊕ B1 G1 = A1 B1
P2 = A2 ⊕ B2 G2 = A2 B2
P3 = A3 ⊕ B3 G3 = A3 B3

o Second level: The Carry Look-Ahead (CLA) logic block which consists of four 2-level
implementation logic circuits. It generates the carry signals (C1, C2, C3, and C4) as
de(ined by the above expressions.

C1 = G0 + P0C0
C2 = G1 + P1G0 + P1P0C0
C3 = G2 + P2G1 + P2P1G0 + P2P1P0C0
C4 = G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0C0

o Third level: Four XOR gates which generate the sum signals (Si) (Si = Pi ⊕ Ci).
Output signals of this level (S0, S1, S2, and S3).
S0 = A0 ⊕ B0 +C0
S1 = A1 ⊕ B1 +C1
S2 = A2 ⊕ B2 +C2
S3 = A3 ⊕ B3 +C3

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Carry Select Adder (CSA):

Carry Select Adder further optimizes addition speed by splitting the adder into two
separate paths. The input numbers are divided into two groups, and two parallel adders
work simultaneously, each assuming a different carry-in (0 and 1). The (inal sum and carry-
out are then selected based on the actual carry-in value.

Carry Select Adder can be Constructed by implementing 2 stage Ripple Carry Adder and
multiplexer circuit. Carry Select Adder select the sum and carry output from stage 1 ripple
carry adder when carry input ‘0’ and select Sum and carry output from stage 2 ripple carry
adder, when carry input ‘1’.

 Multiplication of Positive Numbers

Multiplication of two (ixed-point binary numbers in signed-magnitude representation
is done with paper and pencil by a process of successive shift and add operations. This
process is best illustrated with a numerical example.

The process consists of looking at successive bits of the multiplier, least signi(icant
bit (irst. If the multiplier bit is a 1, the multiplicand is copied down; otherwise, zeros are
copied down. The numbers copied down in successive lines are shifted one position to the
left from the previous number. Finally, the numbers are added and their sum forms the
product.

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Hardware Algorithm
A (lowchart of the hardware multiply algorithm. Initially, the multiplicand is in B and
the multiplier in Q. Their corresponding signs are in Bs, and Qs, respectively. The signs are
compared, and both A and Q are set to correspond to the sign of the product since a double-
length product will be stored in registers A and Q. Registers A and E are cleared and the
sequence counter SC is set to a number equal to the number of bits of the multiplier.

Hardware Implementation for Signed-Magnitude Data

• The hardware for multiplication consists of the multiplicand is in register B
and the multiplier in Q.
• The sum of A and B forms a partial product which is transferred to the EA
register.
• Both partial product and multiplier are shifted to the right. This shift will be
denoted by the statement shr EAQ to designate the right shift.
• After the initialization, the low-order bit of the multiplier in Q, is tested.
If it is a 1, the multiplicand in B is added to the present partial product in A.
• If it is a 0, nothing is done. Register EAQ i s then shifted once to the right to
form the new partial product The sequence counter is decremented by 1
and its new value checked. If it is not equal to zero, the process is repeated
and a new partial product is formed. The process stops when SC = 0.

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 Booth’s algorithm
Booth's algorithm is a multiplication algorithm used for signed integer
multiplication, particularly in binary arithmetic. It's an ef(icient algorithm that reduces the
number of additions required for the multiplication process. The algorithm uses a
technique involving shifting and addition to perform binary multiplication.

Here are the steps of Booth's algorithm for multiplying two binary numbers (BR and Q):

1. Initialize:
• BR is the multiplicand (usually in 2's complement form).
• Q is the multiplier (in binary).
• Q(-1) is initialized to 0 for sign extension.
2. Repeat for n bits (where n is the number of bits in the multiplier):
• Check the least signi(icant bit (LSB) of Q and Q(-1).
• If the last two bits of Q are "01," perform A = A + BR (BR is the multiplicand).
If "10," perform A = A - BR.
3. Arithmetic Right Shift:
• Shift AQ right by one bit, preserving the sign bit.
4. Repeat steps 2 and 3 for n iterations.
5. Result:
The (inal product is in AQ, with A containing the most signi(icant bits and Q containing the
least signi(icant bits.

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 Integer division
Integer division in computer organization refers to the process of dividing one integer
by another to obtain a quotient and possibly a remainder. This operation is fundamental
in computer arithmetic and is typically implemented in hardware to ensure ef(icient and
accurate computation.

There are various approaches to implementing integer division in computer hardware,

including:

Shift and Subtract (or "restoring division"):

This method uses bit shifting and subtraction to (ind the quotient and remainder. It
involves shifting the divisor leftward until it is greater than or equal to the dividend. Then,
subtract the shifted divisor from the dividend, and repeat the process until the result is less
than the divisor.

Here, register Q is used to contain the quotient, and register A is used to contain the
remainder. Here, the divisor will be loaded into the register M, and n-bit divided will be
loaded into the register Q. 0 is the starting value of a register. The values of these types of
registers are restored at the time of iteration. That's why it is known as restoring.

1. The corresponding value will be initialized to the registers, i.e., register A will
contain value 0, register M will contain Divisor, register Q will contain Dividend, and
N is used to specify the number of bits in dividend.
2. register A and register Q will be treated as a single unit, and the value of both the
registers will be shifted left.
3. After that, the value of register M will be subtracted from register A. The result of
subtraction will be stored in register A.
4. Check the most signi(icant bit of register A.
a. If this bit of register A is 0, then the least signi(icant bit of register Q will be
set with a value 1.
b. If the most signi(icant bit of A is 1, then the least signi(icant bit of register Q
will be set to with value 0, and restore the value of A that means it will restore
the value of register A before subtraction with M.
5. After that, the value of N will be decremented. Here n is used as a counter.
6. if the value of N is 0, we will break the loop. Otherwise, we have to again go to step
2.
7. This is the last step. In this step, the quotient is contained in the register Q, and the
remainder is contained in register A.

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Non-Restoring Division:
This technique is similar to restoring division but uses a non-restoring approach, meaning
the divisor is subtracted and restored based on whether the result is positive or negative.
This approach can reduce the number of operations needed.
Now we will learn steps of the non-restoring division algorithm, which are described as
follows:

1. In this step, the corresponding value will be initialized to the registers, i.e., register
A will contain value 0, register M will contain Divisor, register Q will contain
Dividend, and N is used to specify the number of bits in dividend.
2. In this step, we will check the sign bit of A.
3. If this bit of register A is 1, then shift the value of AQ through left, and perform A =
A + M. If this bit is 0, then shift the value of AQ into left and perform A = A - M. That

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means in case of 0, the 2's complement of M is added into register A, and the result
is stored into A.
4. Now, we will check the sign bit of A again.
5. If this bit of register A is 1, then Q[0] will become 0. If this bit is 0, then Q[0] will
become 1. Here Q[0] indicates the least signi(icant bit of Q.
6. After that, the value of N will be decremented. Here N is used as a counter.
7. If the value of N = 0, then we will go to the next step. Otherwise, we have to again go
to step 2.
8. We will perform A = A + M if the sign bit of register A is 1.
9. This is the last step. In this step, register A contains the remainder, and register Q
contains the quotient.

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 Floating-Point Numbers and Operations

Floating-point numbers and operations play a crucial role in computer organization, as
they are essential for representing and performing arithmetic on real numbers in a digital
computer.

1. Floating-Point Representation:
Floating-point numbers are a way to represent real numbers in a binary format. They are
characterized by three essential components:

o Sign bit (S): This bit determines the sign of the number, with 0 representing positive
and 1 representing negative.
o Exponent (E): This part represents the power of 2 to which the signi(icant
(mantissa or fraction) is raised. It can be positive or negative.
o Signi icant (Mantissa or Fraction): This component contains the signi(icant digits
of the number, which are multiplied by 2 raised to the exponent.
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Floating-point numbers are typically represented in either single-precision (32 bits) or

double-precision (64 bits), which determine the range and precision of numbers that can
be represented.

2. Floating-Point Operations:
Common operations performed on (loating-point numbers in computer organization
include:

a. Addition and Subtraction: Adding or subtracting two (loating-point numbers

involves aligning their exponents, performing the operation on the mantissas, and
then normalizing the result. Normalization adjusts the exponent and mantissa to
the proper format.
b. Multiplication: Multiplying two (loating-point numbers requires multiplying their
signi(icands and adding their exponents. Afterward, the result is normalized to
obtain the (inal representation.
c. Division: Division involves dividing the signi(icands and subtracting the
exponents. Like multiplication, the result is then normalized.

Floating point addition and subtractions

Floating-point addition and subtraction operations involve aligning the exponents of the
numbers and performing the addition or subtraction on their signi(icands (mantissas).
Here's a step-by-step explanation of how these operations are typically performed:

Floating-Point Addition:

o Aligning Exponents: The (irst step in (loating-point addition is to align the

exponents of the numbers being added. This alignment ensures that the exponents
are the same, making it possible to add the signi(icands. To align the exponents, you
must shift one or both signi(icands as needed, changing the signi(icands' values but
maintaining the overall value of the number.
o Adding Signi icands: Once the exponents are aligned, you can add the signi(icands.
This is just regular binary addition, taking into account the sign bit. Over(low and
under(low may occur during this step, and it needs to be properly handled to avoid
loss of information.
o Normalization: After adding the signi(icands, the result is normalized.
Normalization involves adjusting the exponent and the signi(icand so that the result
follows the (loating-point format. This may require shifting the signi(icand and
adjusting the exponent accordingly.

0.5372400 X 103
0.1580000 x 10-1
It is necessary that the two exponents be equal before the mantissas can be added.
We can either shift the (irst number three positions to the left, or shift the second number
three positions to the right. When the mantissas are stored in registers, shifting to the left
causes a loss of most signi(icant digits. Shifting to the right causes a loss of least signi(icant
digits.

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0.5372400 X 102
0.0001580 X 102
0.5373980 X 102

Floating-Point Subtraction:

Floating-point subtraction is very similar to addition but with one key difference:

o Aligning Exponents: Just as in addition, the (irst step in (loating-point subtraction

is to align the exponents of the numbers being subtracted.
o Subtracting Signi icands: Once the exponents are aligned, you can subtract the
signi(icands. This is also binary subtraction, taking into account the sign bit. As with
addition, you need to handle over(low and under(low.
o Normalization: After subtracting the signi(icands, the result is normalized,
adjusting the exponent and signi(icand as needed.

0.56780 X 105
0.56430 X 105
0.00350 X 105

To normalize a number that contains an under(low, it is necessary to shift the

mantissa to the left and decrement the exponent until a nonzero digit appears in the (irst
position. In the example above, it is necessary to shift left twice to obtain 0.35000 X 103.

 Basic Processing Unit

The basic processing unit in computer organization is known as the Central Processing Unit
(CPU). The CPU is often considered the "brain" of the computer because it is responsible
for executing instructions and performing calculations.

The CPU performs a wide range of tasks, including:

1. Instruction Fetch: It fetches instructions from the computer's memory, typically

from RAM (Random Access Memory).
2. Instruction Decoding: It decodes the instructions to understand what operation
needs to be performed.
3. Execution: It executes the decoded instructions, which can involve arithmetic and
logic operations, data movement, and control (low instructions.
4. Arithmetic and Logic Unit (ALU): The ALU is a part of the CPU that performs
mathematical calculations and logical operations, such as addition, subtraction,
multiplication, division, AND, OR, NOT, etc.
5. Control Unit: The control unit manages the (low of instructions and data within the
CPU and coordinates the execution of instructions.
6. Register File: The CPU contains registers, which are small, high-speed storage
locations used to hold data, addresses, and intermediate results during processing.

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7. Memory Interface: The CPU interfaces with the computer's memory system,
enabling it to read and write data to and from RAM.
8. Clock: The CPU operates based on a clock signal, which controls the timing of its
operations and synchronizes them with other parts of the computer.

 Fundamental Concepts
1. The processor fetches one instruction at a time and performs the operation
speci(ied.
2. Instructions are fetched from successive memory locations until a branch or a jump
instruction is encountered.
3. The processor keeps track of the address of the memory location containing the next
instruction to be fetched using Program Counter (PC).
4. Instruction Register (IR).

 Execution of a Complete Instruction

The execution of a complete instruction within a CPU involves several stages, typically
following a sequence of fetch, decode, execute, and write back. Here's a step-by-step
overview of how a typical instruction is processed within a CPU:

1. Instruction Fetch (IF):

a. The control unit fetches the next instruction from memory. It uses the
program counter (PC) to determine the address of the instruction in memory.
b. The fetched instruction is stored in a special register called the Instruction
Register (IR).
2. Instruction Decode (ID):
a. The control unit decodes the instruction stored in the IR to determine the
operation to be performed and the operands involved.
b. It identi(ies the source and destination registers and memory locations, as
well as any immediate data (constants) needed for the operation.
3. Data Fetch (also known as Operand Fetch) (OF):
a. If the instruction involves reading data from memory or registers, the
required data is fetched from the speci(ied source location. This step may
involve accessing registers, cache, or main memory, depending on the
instruction and the CPU's design.
b. The fetched data is usually stored in temporary registers or the ALU
(Arithmetic and Logic Unit) for subsequent processing.
4. Execution (EX):
a. The ALU performs the operation speci(ied by the instruction. This stage
involves arithmetic or logical calculations, such as addition, subtraction,
bitwise operations, etc.
b. The results of the operation are generated and temporarily held within the
CPU's registers.
5. Memory Access (MEM) (if required):
a. If the instruction involves memory access, such as a load or store operation,
the CPU reads from or writes to memory as necessary. This stage also
includes operations like cache access if applicable.
b. The result of memory access, if any, is stored in temporary registers.
6. Write Back (WB):

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a. The (inal result of the instruction is written back to the speci(ied destination
register or memory location.
b. The control unit updates registers or memory locations as necessary.
7. Update Program Counter (PC):
a. The program counter is updated to point to the address of the next
instruction to be executed. This is typically done at the end of the instruction
cycle.
b. The update may involve incrementing the program counter to point to the
next sequential instruction, or it could be based on conditional branching
decisions, where the program counter is set to a different address.

 Multiple-Bus Organization
In single bus organization, only one data item can be transferred over the bus in a
clock cycle. To reduce the number of steps needed, most commercial processors provide
multiple internal paths that enable several transfers to take place in parallel.
Multiple bus organization in computer architecture is a design that allows multiple
devices to work simultaneously. This reduces the time spent waiting and improves the
computer's speed. The main advantage of multiple bus organization is the reduction in the
number of cycles required for execution.
In a multiple bus structure, one bus is used to fetch instructions and the other is
used to fetch data. The same bus is shared by three units: memory, processor, and I/O units.
In a multiple bus system, each processor-memory pair is linked by various
redundant paths. This means that the failure of one or more paths can be tolerated, but it
will degrade system performance. The main reason for having multiple buses in a computer
design is to improve performance.
Other advantages include:
a. Better connectivity
b. An increase in the size of the registers There are three types of bus lines: data
bus, address bus, and control bus. Communication over each bus line is
performed in cooperation with another.
Three bus organization of data path
In single bus organization, only one data item can be transferred over the bus in a clock
cycle. To reduce the number of steps needed, most commercial processors provide multiple
internal paths that enable several transfers to take place in parallel.

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A three-bus structure used to connect the registers and the ALU of a processor. All
general-purpose registers are combined into a single block called the register (ile. The
register (ile in Figure is said to have three ports. There are two outputs, allowing the
contents of two different registers to be accessed simultaneously and have their contents

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placed on buses A and B. The third port allows the data on bus C to be loaded into a third
register during the same clock cycle.

Buses A and B are used to transfer the source operands to the A and B inputs of the ALU,
where an arithmetic or logic operation may be performed. The result is transferred to the
destination over bus C. If needed, the ALU may simply pass one of its two input operands
unmodi(ied to bus C. We will call the ALU control signals for such an operation R=A or R=B.
A second feature in Figure is the introduction of the Incrementor unit, which is used to
increment the PC by 4. Using the Incrementor eliminates the need to add 4 to the PC using
the main ALD, as was done in single bus organization. The source for the constant 4 at the
ALU input multiplexer is still useful.

It can be used to increment other addresses, such as the memory addresses in Load
Multiple and Store Multiple instructions.

Consider the three-operand instruction Add R4,R5,R6: The control sequence for executing
this instruction is given in Figure.

In step 1, the contents of the PC are passed through the ALU, using the R=B control signal,
and loaded into the MAR to start a memory read operation. At the same time the PC is
incremented by 4. Note that the value loaded into MAR is the original contents of the PC.
The incremented value is loaded into the PC at the end of the clock cycle and will not affect
the contents of MAR.

In step 2, the processor waits for MFC and loads the data received into MDR, then transfers
them to IR in step 3. Finally, the execution phase of the instruction requires only one control
step to complete, step 4. By providing more paths for data transfer a signi(icant reduction
in the number of clock cycles needed to execute an instruction is achieved.

Design of Control Unit

The Control Unit is classi(ied into two major categories:

a. Hardwired Control
b. Microprogrammed Control
Hardwired Control
The Hardwired Control organization involves the control logic to be implemented with
gates, (lip-(lops, decoders, and other digital circuits.

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The following image shows the block diagram of a Hardwired Control organization.

a. A Hard-wired Control consists of two decoders, a sequence counter, and a

number of logic gates.
b. An instruction fetched from the memory unit is placed in the instruction
register (IR).
c. The component of an instruction register includes; I bit, the operation code,
and bits 0 through 11.
d. The operation code in bits 12 through 14 are coded with a 3 x 8 decoder.
e. The outputs of the decoder are designated by the symbols D0 through D7.
f. The operation code at bit 15 is transferred to a (lip-(lop designated by the
symbol I.
g. The operation codes from Bits 0 through 11 are applied to the control logic
gates.
h. The Sequence counter (SC) can count in binary from 0 through 15.

Micro-programmed Control
The Microprogrammed Control organization is implemented by using the programming
approach.
In Microprogrammed Control, the micro-operations are performed by executing a program
consisting of micro-instructions.

The following image shows the block diagram of a Microprogrammed Control organization.

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a. The Control memory address register speci(ies the address of the micro-instruction.
b. The Control memory is assumed to be a ROM, within which all control information
is permanently stored.
c. The control register holds the microinstruction fetched from the memory.
d. The micro-instruction contains a control word that speci(ies one or more micro-
operations for the data processor.
e. While the micro-operations are being executed, the next address is computed in the
next address generator circuit and then transferred into the control address register
to read the next microinstruction.
f. The next address generator is often referred to as a micro-program sequencer, as it
determines the address sequence that is read from control memory.

Short Questions
1. Explain half adder
2. Explain full adders.
3. Explain Ripple carry address (RCA) with neat diagram.
4. Explain Carry Select Adder (CSA) with neat diagram.
5. Explain (loating point representation
6. Explain advantages of multi bus organization.
7. De(ine hardwired control unit.
8. De(ine multi programmed control.
Long Questions
1. Write addition algorithm with signed magnitude
2. Write subtraction algorithm with signed magnitude
3. Explain fast adders.
4. Explain Carry Look-Ahead Adder (CLA) with neat diagram.
5. Explain booths multiplication algorithm.
6. Explain integer division restoring method.
7. Explain (loating point operations.
8. Explain activities of processing unit.
9. De(ine instruction execution steps.
10. De(ine multi bus organisation

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II-Assignment Questions
Short Questions
1. Explain full adders.
2. Explain Ripple carry address (RCA) with neat diagram.
3. Explain (loating point representation
4. Explain advantages of multi bus organization.
5. De(ine multi programmed control.

Long Questions
1. Write addition algorithm with signed magnitude
2. Explain Carry Look-Ahead Adder (CLA) with neat diagram.
3. Explain booths multiplication algorithm.
4. Explain integer division restoring method.
5. De(ine instruction execution steps.

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