Scribd
Upload
6 views

DMA

Uploaded by

vijaykrishna2k24
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
6 views

DMA

Uploaded by

vijaykrishna2k24
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 4

DMA

A direct memory access (DMA) is an operation in which data is copied (transported) from
one resource to another resource in a computer system without the involvement of the CPU. Direct
Memory Access is a capability provided by some computer bus architectures that allows data to be
sent directly from an attached device (such as a disk drive) to the memory on the computer's
motherboard. The microprocessor is freed from involvement with the data transfer, thus speeding
up overall computer operation.

DMA Controller

The DMA controller needs the usual circuits of an interface to communicate with the CPU
and 110 device. Inaddition, it needs an address register, a word count register, and a set of address
lines The address register andaddress are used for direct communication with the memory

The CPU may be placed in an idle state in a variety of ways. One common method
extensively used inmicroprocessors is to disable the buses through special control signals. Figure 1
shows two control signals inthe CPU that bus request facilitate the DMA transfer. The bus request
(BR) input is used by the DMA controller to request the CPU to relinquish control of the buses. When
this input is active, the CPU terminates the execution of the currentinstruction and places the
address bus, the data bus, and the read and write lines into a high-impedance state. Thehigh-
impedance state behaves like an open circuit, which means that the output is disconnected and does
nothave a logic significance .

Bus grant

CPU activates the bus grant (BC) output to inform the external DMA that the buses are in the
high-impedancestate. The DMA that originated the bus request can now take control of the buses to
conduct memory transferswithout processor intervention. When the DMA terminates the transfer, it
disables the bus request line. The CPUdisables the bus grant, takes control of the buses, and returns
to its normal operation.
The position of the DMA controller among the other components in a computer system is
illustrated in Fig. 1 The CPU communicates with the DMA through the address and data buses as
with any interface unit. The DMA has its own address, which activates the DS and R$ lines, The CPU
Initializes the DMA through the data bus, Once the DMA receives the start control commend, it can
start the transfer between the peripheral device and the memory. When the peripheral device
sends a DMA request, the DMA controller activates the BR line, Informing the CPU to relinquish the
buses, The CPU responds with Its BG line, informing the DMA that its buses are disabled. The DMA
then puts the current value of Its address register into the address bus, Initiates the RD or WR signal
and sends a DMA acknowledge to the peripheral device, Note that the RD and WR lines In the DMA
controller are bidirectional. The direction of transfer depends on the status of the BG line. When BG
= 0 the RD and WR are Input lines allowing the CPU to communicate with the internal DMA registers
When GB = 1. the RD and WR are output lines from the DMA controller to the random-access
memory to specify the read or write operation for the data. When the peripheral device receives a
DMA acknowledge. it puts a ward in the data bus (for write) or receives a word from the data bus
(for read). Thus the PMA controls the read or write operations and supplies the address for the
memory The peripheral unit can then communicate with memory through the data bus for direct
transfer between the two units while the CPU is momentarily disabled.

Unit – V

Pipelining
The term Pipelining refers to a technique of decomposing a sequential process into sub-operations,
with each sub-operation being executed in a dedicated segment that operates concurrently with all
other segments.

The most important characteristic of a pipeline technique is that several computations can be in
progress in distinct segments at the same time. The overlapping of computation is made possible by
associating a register with each segment in the pipeline. The registers provide isolation between each
segment so that each can operate on distinct data simultaneously.

The structure of a pipeline organization can be represented simply by including an input register for
each segment followed by a combinational circuit.

Let us consider an example of combined multiplication and addition operation to get a better
understanding of the pipeline organization.

You might also like