DEPARTMENT OF INFORMATION SCIENCE & ENGINEERING

Course Name: COMPUTER ORGANIZATION AND

ARCHITECTURE
Course Code:PCC22IS42
Credits: 3:0:0
Faculty:
Dr. Radhika T V
Assistant Professor
Module 1

Basic Structure of Computers:

Functional Units, Basic Operational Concepts, Performance –
Basic Performance Equation, Clock Rate, Performance
Measurement.

Machine Instructions and Programs: Numbers, Arithmetic

Operations and Characters, Memory Location and Addresses.
Basics

• Types of computer
• Personal/ Desktop Computer
• Portable Notebook computer
• Workstations
• Enterprise Systems, Servers
• Supercomputers
Functional Units

Arithmetic
Input and
logic

Memory

Output Control

I/O Processor

Figure 1.1. Basic functional units of a computer.

Information Handled by a Computer

• Over all functions of the computer

• Instructions/machine instructions are commands
Govern the transfer of information within a computer as well as between the
computer and its I/O devices
Specify the arithmetic and logic operations to be performed
Program
• Data
Used as operands by the instructions
Source program
• Encoded in binary code – 0 and 1
BCD, ASCII, EBCDIC
Input Unit

• Computer accepts coded information through input unit.

• Most popular input unit is keyboard.
• Many other input devices are joystick, trackballs, mouse, microphone
etc.
Memory Unit
• Store programs and data
• Two classes of storage
Primary storage
Fast
Programs must be stored in memory while they are being executed
Large number of semiconductor storage cells
Processed in words
Address
Word length-No. of bits in each word(16-64 bits)
RAM and memory access time(ranges from few ns to 100 ns for modern RAM units)
Memory hierarchy – cache, main memory
Secondary storage – larger and cheaper
Example: Magnetic disk, tape, CD-ROMS
Arithmetic and Logic Unit (ALU)

• Most computer operations are executed in ALU of the processor.

• Load the operands into memory – bring them to the processor –
perform operation in ALU – store the result back to memory or retain
in the processor.
• Registers (Access time is faster than cache unit)
• Fast control of ALU
Output Unit

• It is the counter part of input unit.

• Function is to send processed results to outside world.
• Printer is most common output device.
• Graphic displays provide I/O functions.
Control Unit
• All computer operations are controlled by the control unit.
• Effectively serves as nerve center.
• The timing signals that govern the I/O transfers are also generated by
the control unit.
• Timing signals determines when a given action is to take place.
• Control unit is usually distributed throughout the machine instead of
standing alone.
• Operations of a computer:
Accept information in the form of programs and data through an
input unit and store it in the memory
Fetch the information stored in the memory, under program control,
into an ALU, where the information is processed
Output the processed information through an output unit
Control all activities inside the machine through a control unit
Basic Operational
Concepts
• Activity in a computer is governed by instructions.

• To perform a task, an appropriate program consisting of a list of instructions is

stored in the memory.

• Individual instructions are brought from the memory into the processor, which
executes the specified operations.

• Data to be used as operands are also stored in the memory.

A Typical Instruction

• Add LOCA, R0
• Add the operand at memory location LOCA to the operand in a register R0
in the processor.
• Place the sum into register R0.
• The original contents of LOCA are preserved.
• The original contents of R0 is overwritten.
• Instruction is fetched from the memory into the processor – the operand at
LOCA is fetched and added to the contents of R0 – the resulting sum is
stored in register R0.
• It combines Memory Access and ALU operation
Separate Memory Access and ALU
Operation
• Load LOCA, R1
• Add R1, R0
• Whose contents will be overwritten?
Connection Between the Processor
and the Memory
Memo ry

MAR MDR
Co n t ro l

PC R0

R1
Pro ces s o r
IR

ALU
Rn - 1

n g en eral p u rp o s e
reg i s t ers

Figure 1.2. Connections between the processor and the memory.

Registers in Processor

• Instruction Register(IR): It holds the Instruction code that is currently

being executed.
• Program Counter(PC): It holds the address of next Instruction.
• N general purpose registers
• Two special Purpose registers are
• MAR
• MDR
Typical Operating Steps

Programs reside in the memory through input devices

PC is set to point to the first instruction
The contents of PC are transferred to MAR
A Read signal is sent to the memory
The first instruction is read out and loaded into MDR
The contents of MDR are transferred to IR
Decode and execute the instruction
Typical Operating Steps (Cont’)

• Get operands for ALU

General-purpose register
Memory (address to MAR – Read – MDR to ALU)
• Perform operation in ALU
• Store the result back
To general-purpose register
To memory (address to MAR, result to MDR – Write)
• During the execution, PC is incremented to the next
instruction
Typical Operating Steps (Cont’)

• Normal execution of program may be preempted if device requires

urgent servicing
• Device generates interrupt signal.
• Processor provides requested service by executing Interrupt Service
Routine.
Bus Structures
• There are many ways to connect different parts inside a computer
together.
• A group of lines that serves as a connecting path for several devices is
called a bus.
• Single bus- only two units are actively use the bus at any given time.
• Low cost and flexibility for attaching peripheral devices
• Address/data/control
Bus Structure

Single-bus

Input Output Memory Processor

Figure 1.3. Single-bus structure.

Speed Issue

• Different devices have different transfer/operate speed.

• If the speed of bus is bounded by the slowest device connected to it,
the efficiency will be very low.
• How to solve this?
• A common approach – use buffers ( holds the information during
transfer) Ex: printer buffer
Performance
Performance

• The most important measure of a computer is how quickly it can

execute programs.
• Three factors affect performance:
Hardware design
Instruction set
Compiler
• Total elapsed time , Processor time
Performance
• Processor time to execute a program depends on the hardware involved in the execution of
individual machine instructions.

Main Cache
memory memory Processor

Bus

Figure 1.5. The processor cache.

Performance

• The processor and a relatively small cache memory can be fabricated

on a single integrated circuit chip.
• Speed
• Cost
• Memory management
Processor Clock

• Timing signal -Clock

• Regular time interval -Clock cycle
• The execution of each instruction is divided into several steps, each of which
completes in one clock cycle.
• Length P of clock cycle is an important parameter
• R=1/P, Clock rate
• Hertz – cycles per second
• Million-Mega
• Billion-Giga
Basic Performance Equation
 T – processor time required to execute a program that has
been prepared in high-level language

 N – number of actual machine language instructions needed

to complete the execution (note: loop)

 S – average number of basic steps needed to execute one

machine instruction. Each step completes in one clock cycle

 R – clock rate (cycles per second)

 Note: these are not independent to each other

N S
T  How to improve T?

R
Pipeline and Superscalar Operation

• Instructions are not necessarily executed one after another.

• The value of S doesn’t have to be the number of clock cycles to execute
one instruction.
• Pipelining – overlapping the execution of successive instructions.
• Add R1, R2, R3
• Superscalar operation – multiple instruction pipelines are implemented in
the processor.
• Goal – reduce S (could become <1!)
Clock Rate

• Increase clock rate

Improve the integrated-circuit (IC) technology to make the circuits faster
Reduce the amount of processing done in one basic step (however, this may
increase the number of basic steps needed)
• Increases in R that are entirely caused by improvements in IC
technology affect all aspects of the processor’s operation equally
except the time to access the main memory.
CISC and RISC

Tradeoff between N and S

A key consideration is the use of pipelining
 S is close to 1 even though the number of basic steps per instruction may be
considerably larger
 It is much easier to implement efficient pipelining in processor with simple
instruction sets
Reduced Instruction Set Computers (RISC)
Complex Instruction Set Computers (CISC)
Compiler

• A compiler translates a high-level language program into a sequence of

machine instructions.
• To reduce N, we need a suitable machine instruction set and a compiler
that makes good use of it.
• Goal – reduce N×S
• A compiler may not be designed for a specific processor; however, a high-
quality compiler is usually designed for, and with, a specific processor.
Performance Measurement
• T is difficult to compute.
• Measure computer performance using benchmark programs.
• System Performance Evaluation Corporation (SPEC) selects and publishes
representative application programs for different application domains, together with
test results for many commercially available computers.
• Compile and run (no simulation)
• Reference computer

Running time on the reference computer

SPEC rating 
Running time on the computer under test
n 1
SPEC rating ( SPECi ) n

i 1
Chapter 2. Machine Instructions
and Programs
Objectives

• Machine instructions and program execution, including branching and

subroutine call and return operations.
• Number representation and addition/subtraction in the 2’s-complement
system.
• Addressing methods for accessing register and memory operands.
• Assembly language for representing machine instructions, data, and programs.
• Program-controlled Input/Output operations.
Number, Arithmetic Operations, and
Characters
Number Representation
Consider n bit vector

We need to represent both positive and negative numbers. Three systems used for representing
such numbers are
Signed Integer

• 3 major representations:
Sign and magnitude
One’s complement
Two’s complement
• Assumptions:
4-bit machine word
16 different values can be represented
Roughly half are positive, half are negative
Binary, Signed-Integer
Representations
B alues
V represented

Sign and
b 3 b 2b 1b 0 magnitude 1's complement 2's complement

0 1 1 1 + 7 + 7 + 7
0 1 1 0 + 6 + 6 + 6
0 1 0 1 + 5 + 5 + 5
0 1 0 0 + 4 + 4 + 4
0 0 1 1 + 3 + 3 + 3
0 0 1 0 + 2 + 2 + 2
0 0 0 1 + 1 + 1 + 1
0 0 0 0 + 0 + 0 + 0
1 0 0 0 - 0 - 7 - 8
1 0 0 1 - 1 - 6 - 7
1 0 1 0 - 2 - 5 - 6
1 0 1 1 - 3 - 4 - 5
1 1 0 0 - 4 - 3 - 4
1 1 0 1 - 5 - 2 - 3
1 1 1 0 - 6 - 1 - 2
1 1 1 1 - 7 - 0 - 1

Figure 2.1. Binary, signed-integer representations.

1111
0111 (+7)
1 0 0 0 (-7)
1
1 0 01

2n-1= 15= 1 1 1 1

2’s compliment= 2n= 16=

10000 (16)
0111 (7
010 0 1 (-7)
Addition of Positive Numbers
Sign and Magnitude Representation

-7 +0
-6 1111 0000 +1
1110 0001
-5 +2 +
1101 0010
-4 1100 0011 +3 0 100 = + 4

-3 1011 0100 +4 1 100 = - 4

1010 0101
-2 +5 -
1001 0110
-1 1000 0111 +6
-0 +7
High order bit is sign: 0 = positive (or zero), 1 = negative
Three low order bits is the magnitude: 0 (000) thru 7 (111)
Number range for n bits = +/-2n-1 -1
Two representations for 0
One’s Complement Representation

-0 +0
-1 1111 0000 +1
1110 0001
-2 +2 +
1101 0010
-3 1100 0011 +3 0 100 = + 4

-4 1011 0100 +4 1 011 = - 4

1010 0101
-5 +5 -
1001 0110
-6 1000 0111 +6
-7 +7
• Subtraction implemented by addition & 1's complement
• Still two representations of 0! This causes some problems
• Some complexities in addition
Two’s Complement Representation

like 1's comp

except shifted -1 +0
one position -2 1111 0000 +1
Clockwise 1110 0001
-3 +2 +
1101 0010
-4 1100 0011 +3 0 100 = + 4
Addition mod N
-5 1011 0100 +4 1 100 = - 4
a+b mod N
1010 0101
-6 +5 -
3+4 mod 16 1001 0110
-7 1000 0111 +6
(+7) +(-4) mod 16
-8 +7

0111 • Only one representation for 0

1100
0 0 11 • One more negative number than positive number
Rules for Addition and subtraction

• Rule 1:
To add two numbers, add their n-bit representation, ignoring their carry-out signal from MSB
position. Sum will be algebraically correct value in 2’s compliment representation if
answer is in the range - 2n-1 to +2n-1-1.

• Rule 2:
• To subtract two numbers X and Y, ie to perform X-Y, form the 2’s compliment of Y and
then add it to X as in rule 1. Again result will be algebraically correct value in 2’s
compliment representation if answer is in the range - 2 n-1 to +2n-1-1.
Addition and Subtraction – 2’s Complement

4 0100 -4 1100
If carry-in to the
high +3 0011 + (-3) 1101
order bit =
carry-out then 7 0111 -7 11001
ignore
carry

if carry-in differs 4 0100

from -4 1100
carry-out then -3 1101
overflow +3 0011
1 10001 -1 1111

Simpler addition scheme makes twos complement the most common

choice for integer number systems within digital systems
2’s-Complement Add and Subtract Operations

(a) 0010 (+ 2) (b) 0100 (+ 4)

+ 0011 (+ 3) + 1010 (- 6 )
0101 (+ 5) 1110 (- 2 )
(c) 1011 (- 5 ) (d) 0111 (+ 7)
+ 1110 (- 2 ) + 1101 (- 3 )
1001 (- 7 ) 0100 (+ 4)
(e) 1101 (- 3 ) 1101
- 1001 (- 7 ) + 0111
0100 (+ 4)
(f) 0010 (+ 2) 0010
- 0100 ( + 4) + 1100
1110 (- 2 )
(g) 0110 (+ 6) 0110
- 0011 (+ 3) + 1101
0011 (+ 3)
(h) 1001 (- 7 ) 1001
- 1011 (- 5 ) + 0101
1110 (- 2 )
(i) 1001 (- 7 ) 1001
- 0001 (+ 1) + 1111
1000 (- 8 )
(j) 0010 (+ 2) 0010
- 1101 (- 3 ) + 0011
0101 ( + 5)

Figure 2.4. 2's-complement Add and Subtract operations.

-6: 1010
-7: 1001
0 0 1 1 (+3) arithmetic Overflow

+3 0011
-
-7 1001===

0011
0111
1 0 1 0----6 arithmetic overflow

+6
-2===1000 (-8)
Overflow - Add two positive numbers to get a negative
number or two negative numbers to get a positive number

-1 +0 -1 +0
-2 1111 0000 +1 -2 1111 0000 +1
1110 0001 1110 0001
-3 +2 -3
1101 1101 +2
0010 0010
-4 -4
1100 0011 +3 1100 0011 +3
-5 1011 -5 1011
0100 +4 0100 +4
1010 1010
-6 0101 -6 0101
1001
+5 +5
0110 1001
0110
-7 1000 0111 +6 -7 1000 +6
0111
-8 +7 -8 +7

5 + 3 = -8 -7 - 2 = +7
Overflow Conditions

0111 1000
5 0101 -7 1001
3 0011 -2 1100
-8 1000 7 10111
Overflow Overflow
0000 1111
5 0101 -3 1101
2 0010 -5 1011
7 0111 -8 11000
No overflow No overflow

Overflow when carry-in to the high-order bit does not equal carry out
Arithmetic overflow

•Overflow cannot occur when 2 no’s having opposite sign are added.
•Overflow can occur only when 2 No’s having the same sign are added
•Overflow can be detected by considering carry into MSB position(Cn-1) and carry out of
MSB position(Cn ). These two are mutually exclusive.

•Let X and Y be the operands and S be the result vector.

•An overflow is said to occur when the sign of S is not same as signs of X and Y, when
both operands X and Y has same sign
Sign Extension
• Task:
• Given w-bit signed integer x
• Convert it to w+k-bit integer with same value
• Rule:
• Make k copies of sign bit:
• X  = xw–1 ,…, xw–1 , xw–1 , xw–2 ,…, x0

w
X • • •
k copies of MSB

• +4= 0100
• 0000 0100 • • •

• -4=1100 X • • • • • •
• 1111 1100
k w
Memory Locations, Addresses, and Operations
• Number and character operands as well as instructions are stored in the memory of a
computer.
• Memory is organized so that group of n bits can be stored or retrieved in a single basic
operation.
• Each group of n bits is referred as word of information and n is called as world length.
• Modern Computers have word length ranges from 16-64 bits.
• A unit of 8 bits is called as byte.
• Accessing the memory to store or retrieve single item of information requires distinct
names/addresses for each item location.
• A number from 0 to 2k -1 indicates addressable location.
• 24 bit address generates address space of 224 (16 M)
• 32-bit address generates address space of 232 (4 G)
Memory Location, Addresses, and
Operation
32-bit word length example
32 bits

b 31 b 30 b1 b0

•
•
•
Sign bit: b 31 = for
0 positive numbers
b 31 = for
1 negative numbers

(a) A signed integer

8 bits 8 bits 8 bits 8 bits

ASCII ASCII ASCII ASCII

character character character character

(b) Four characters

Memory words
Memory Location, Addresses, and
Operation
• To retrieve information from memory, either for one word or one byte (8-bit),
addresses for each location are needed.
• A k-bit address memory has 2k memory locations, namely 0 – 2k-1, called
memory space.
• 24-bit memory: 224 = 16,777,216 = 16M (1M=220)
• 32-bit memory: 232 = 4G (1G=230)
• 1K(kilo)=210
• 1T(tera)=240
Memory Location, Addresses, and
Operation
Byte Addressability

It is impractical to assign distinct addresses to individual bit

locations in the memory.
The most practical assignment is to have successive addresses refer
to successive byte locations in the memory – byte-addressable
memory.
Byte locations have addresses 0, 1, 2, … If word length is 32 bits,
they successive words are located at addresses 0, 4, 8,…
Big-Endian and Little-Endian
Assignments
Big-Endian: lower byte addresses are used for the most significant bytes of the word
Little-Endian: opposite ordering. lower byte addresses are used for the less significant bytes of the word

W ord
address Byte address Byte address

0 0 1 2 3 0 3 2 1 0

4 4 5 6 7 4 7 6 5 4

• •
• •
• •

k k k k k k k k k k
2 - 4 2 - 4 2 - 3 2 - 2 2 - 1 2 - 4 2 - 1 2 - 2 2 - 3 2 - 4

(a) Big-endian assignment (b) Little-endian assignment

Figure 2.7. Byte and word addressing.

Examples of Big Endian and Little Endian Assignments

Big-endian
As we know that in big-endian MSB Byte will store first. It means the MSB Byte will store at the
lowest memory address.
Little-endian
In the little endian machine, LSB byte will store first. So the LSB Byte will store at the lowest memory
address. See the table,
Memory Location, Addresses, and
Operation
Address ordering of bytes
Word alignment
◦ Words are said to be aligned in memory if they begin at a byte addr. that is
a multiple of the num of bytes in a word.
 16-bit word: word addresses: 0, 2, 4,….
 32-bit word: word addresses: 0, 4, 8,….
 64-bit word: word addresses: 0, 8,16,….
Access numbers, characters, and character strings
Memory Operation

• Load (or Read or Fetch)

Copy the content. The memory content doesn’t change.
Address – Load
Registers can be used
• Store (or Write)
Overwrite the content in memory
Address and Data – Store
Registers can be used
References

[1] Carl Hamacher, Zvonko Vranesic, SafwatZaky: Computer Organization, 5th Edition,
Tata McGraw Hill, 2017

17/01/2025 Department of Information Science & Engineering 64

THANK YOU

17/01/2025 Department of Information Science & Engineering 65