Microprocessors and Microconrollers-

ECPE12
II B. Tech-IV Semester

by
Dr. Srinivasulu Jogi
Assistant Professor, ECE
NIT-Tiruchirappalli

N AT I O N A L I N S T I T U T E O F T E C H N O L O G Y T I R U C H I R A P PA L L I ,
TA M I L N A D U , I N D I A
Microprocessors and Microcontrollers-Module 1-8086

Content
• Microprocessor based personal computer system.
• Software model of 8086.
• Segmented memory operation
• Instruction set.
• Addressing modes.
• Assembly language programming.
• Interrupts.
• Programming with DOS and BIOS function calls.
Microprocessors and Microcontrollers-Module 1-8086
Introduction
• A processor is the logic circuitry that responds to and processes the basic instructions that drives a computer.
• The term processor has generally replaced the term central processing unit. The processor in a ersonal computer or embedded
in small devices is often called a microprocessor.
• Microprocessor is a program-controlled device, which fetches the instructions from memory, decodes and executes the instructions.
Most Micro Processor are single-chip devices.
• A general diagram of processor is shown:
Microprocessors and Microcontrollers-Module 1-8086
Features of 8086
• Intel 8086 microprocessor is the enhanced version of Intel 8085 microprocessor. It was designed by Intel in 1976.
• Intel 8086 is built on a single semiconductor chip and packaged in a 40-pin IC package. The type of package is DIP (Dual
Inline Package).
• The 8086 is a 16-bit microprocessor. The term “16-bit” means that its arithmetic logic unit, internal registers and most of its
instructions are designed to work with 16-bit binary words.
• The 8086 has a 16-bit data bus, so it can read data from or write data to memory and ports either 16 bits or 8 bits at a time.
• The 8086 has a 20-bit address bus, so it can directly access 220 or 10,48,576 (1Mb) memory locations. Each of the 10,48,576 memory
locations is byte. Therefore, a sixteen-bit words are stored in two consecutive memory locations.
• The Features of 8086 Microprocessor can generate 16-bit I/O address, hence it can access 216 = 65536 I/O ports.
• The 8086 provides fourteen 16-bit registers.
• The 8086 has multiplexed address and data bus which reduces the number of pins needed, but does slow down the transfer of data
(drawback).
Microprocessors and Microcontrollers-Module 1-8086
Features of 8086
• The 8086 requires one phase clock with a 33% duty cycle to provide optimized internal timing.
• Range of clock rates are 5MHz, 8MHz, and 10MHz.
• The Features of 8086 Microprocessor is possible to perform bit, byte, word and block operations in 8086. It performs the
arithmetic and logical operations on bit, byte, word and decimal numbers including multiply and divide.
• The Intel 8086 is designed to operate in two modes, namely the minimum mode and the maximum mode. When only one 8086
CPU is to be used in a microcomputer system, the 8086 is used in the minimum mode of operation. In this mode the CPU
issues the control signals required by memory and I/O.
• In multiprocessor (more than one processor in the system) system 8086 operates in maximum mode. In maximum mode,
control signals are generated with the help of external bus controller (8288).
• The Intel 8086 supports multiprogramming. In multiprogramming, the code for two or more processes is in memory at the
same time and is executed in a time-multiplexed fashion.
Microprocessors and Microcontrollers-Module 1-8086
Features of 8086
• An interesting feature of the 8086 is that it fetches up to six instruction bytes (4 instruction bytes for 8088) from memory and
queue stores them in order to speed up instruction execution.
• The Features of 8086 Microprocessor provides powerful instruction set with the following addressing modes: Register,
immediate, direct, indirect through an index or base, indirect through the sum of a base and an index register, relative and
implied.
• It has 256 vectored interrupts.
• Memory is byte addressable - Every byte has a separate address that ranges from 00000H to FFFFFH
Microprocessors and Microcontrollers-Module 1-8086
Architecture of 8086
• Fig. shows a block diagram of the 8086 internal
architecture.
• It is internally divided into two separate
functional units. These are the Bus Interface
Unit (BIU) and the Execution Unit (EU).
• These two functional units can work
simultaneously to increase system speed and
hence the throughput.
• Throughput is a measure of number of
instructions executed per unit time
Microprocessors and Microcontrollers-Module 1-8086
Architecture of 8086
BIU
• The bus interface unit is the 8086 Internal
Architecture to the outside world. It provides a
full 16-bit bidirectional data bus and 20-bit
address bus.
• The bus interface unit is responsible for
performing all external bus operations, such as:
• It sends address of the memory or I/O
• It fetches instruction from memory.
• It reads data from port/memory.
• It writes data into port/memory.
• It supports instruction queuing.
Microprocessors and Microcontrollers-Module 1-8086
Architecture of 8086
BIU
• To implement these functions the BIU contains the instruction queue, segment
registers instruction pointer, address summer and bus control logic.
• Instruction Queue:
• To speed up program execution, the BIU fetches six instruction bytes ahead of time
from the memory. These pre-fetched instruction bytes are held for the execution
unit in a group of registers called Queue.
• With the help of queue it is possible to fetch next instruction when current
instruction is in execution.
• The queue operates on the principle first in first out (FIFO). So that the execution
unit gets the instructions for execution in the order they are fetched.
• Feature of fetching the next instruction while the current instruction is executing is
called pipelining.
Microprocessors and Microcontrollers-Module 1-8086
Architecture of 8086
BIU
Memory Segmentation:
• The physical address of the 8086 Internal Architecture is 20-bits wide to
access 1 Mbyte memory locations. However, its registers and memory
locations which contain logical addresses are just 16-bits wide. Hence 8086
uses memory segmentation.
• The memory in an 8086/88 based system is organized as segmented memory.
The Complete physically available memory may be divided into a number of
logical segments.
• The size of each segment is 64 KB. A segment may be located any where in
the memory. Each of these segments can be used for a specific function.
Microprocessors and Microcontrollers-Module 1-8086
Architecture of 8086
BIU
Memory Segmentation:
• In other words, It treats the 1 Mbyte of memory as divided into segments, with a maximum
size of a segment as 64 Kbytes. Thus any location within the segment can be accessed using
16 bits.
• The 8086 Internal Architecture allows only four active segments at a time, as shown in the
Fig. 6.4. For the selection of the four active segments the 16-bit segment registers are
provided within the BIU of the 8086. These four registers are :
• Code segment (CS) register,
• Data segment (DS) register,
• Stack segment (SS) register,
• Extra segment (ES) register.
Microprocessors and Microcontrollers-Module 1-8086
Architecture of 8086
Memory Segmentation:
• These are used to hold the upper 16-bits of the starting addresses of the four memory
segments, on which 8086 works at a particular time.
• For example, the value in CS identifies the starting address of 64 K-byte segment known as
code segment. By “starting address“, we mean the lowest addressed byte in the active code
segment. The starting address is also known as base address or segment base.
• Function of segment registers:
• The CS register holds the upper 16-bits of the starting address of the segment from
which the BIU is currently fetching the instruction code byte.
• The SS register is used for the upper 16-bits of the starting address for the program
stack (all stack related instructions will operate on stack)
• ES register and DS register are used to hold the upper 16-bits of the starting address of
the two memory segments which are used for data.
Microprocessors and Microcontrollers-Module 1-8086
Architecture of 8086
BIU
Memory Segmentation-Rules:
• The four segments can overlap for small programs. In a minimum system all four segments can start at the address
00000H.
• The segment can begin/start at any memory address which is divisible by 16.
• Advantages:
• It allows the memory addressing capacity to be 1 Mbyte even though the address associated with individual
instruction is only 16-bit.
• It allows instruction code, data, stack, and portion of program to be more than 64 KB long by using more than
one code, data, stack segment, and extra
• It facilitates use of separate memory areas for program, data and stack.
• It permits a program or its data to be put in different areas of memory, each time the program is executed i.e.
program can be relocated which is very useful in multiprogramming.
Microprocessors and Microcontrollers-Module 1-8086
Architecture of 8086
BIU
Instruction Pointer:
• The instruction pointer register holds the 16-bit address of the next Code byte within the code
segment. The value contained in the IP is referred to as an offset. This value must be offset from
(added to) the segment base address in CS to produce the required 20-bit physical address.
• Generation of 20-bit physical address:
• The contents of the CS register are multiplied by 16 i.e. shifted by 4 position to the left by
inserting 4 zero bits and then the offset i.e. the contents of IP register are added to the shifted
contents of CS to generate physical address. As shown in the Fig, the contents of CS register
are 348AH, therefore the shifted contents of CS register are 348A0H. When the BIU adds
the offset of 4214H in the IP to this starting address, the result is 20-bit physical of
38AB4H.
Microprocessors and Microcontrollers-Module 1-8086
Architecture of 8086
BIU
Segment and Offset register combinations:
• The value contained in the instruction pointer is called as an offset
because this value must be added to the base address of the code
segment , which is available in the CS register to find the 20 bit physical
address.
• Few combinations of segment and offset registers in 8086 are as shown:
Microprocessors and Microcontrollers-Module 1-8086
Architecture of 8086
EU
• The execution unit of 8086 Internal Architecture tells the BIU from where to fetch
instructions or data, decodes instructions and executes instructions. It contains
• Control Circuitry
• Instruction Decoder
• Arithmetic Logic Unit (ALU)
• Flag Register
• General Purpose Registers
• Pointers and Index Registers
Microprocessors and Microcontrollers-Module 1-8086
Architecture of 8086
EU
Control Circuitry, Instruction Decoder, ALU::
• The control circuitry in the EU directs the internal operations. A decoder in the EU translates the instructions fetched
from memory into a series of actions which the EU performs. ALU is 16-bit. It can add, subtract, AND, OR, XOR,
increment, decrements, complement and shift binary numbers.
• Flag Register:
• A flag is a flip–flop which indicates some condition produced by the execution of an instruction or controls certain
operations of the EU. The flag register contains nine active flags as shown in the Fig.
Microprocessors and Microcontrollers-Module 1-8086
Architecture of 8086
EU-Flag Register:
• A flag is a flip–flop which indicates some condition produced by the execution of an instruction or controls certain
operations of the EU. The flag register contains nine active flags as shown in the Fig.
Microprocessors and Microcontrollers-Module 1-8086
Architecture of 8086
EU-General Purpose Registers:
• The EU has. 8 general purpose registers labeled AH, AL, BH, BL, CH, CL, DH,
and DL. These registers can be used individually for temporary storage of 8 bit
data. The AL register is also called accumulator. Certain pairs of these general
purpose registers can be used together to store 16-bit data, such as AX, BX, CX
and DX.
EU-Pointers and Index Group Registers:
• All segment registers are 16-bit. But it is necessary to put 20-bit address (physical
address) on the address bus. To get 20-bit physical address one more register is
associated with each segment register the way IP is associated with CS.
• These additional registers belong to the pointer and index group. The pointer and
index group consists of instruction pointer (IP), stack pointer (SP), BP (base
pointer), source index (SI) and destination index (DI) registers.
Microprocessors and Microcontrollers-Module 1-8086
Architecture of 8086
EU-Stack Pointer:
• The stack pointer (SP) register contains the 16-bit
offset from the start of the segment to the top of stack.
For stack operation, physical address is produced by
adding the contents of stack pointer register to the
segment base address in SS. To do this the contents of
the stack segment register are shifted four bits left and
the contents of SP are added to the shifted result. If the
contents of SP are 9F20H and SS are 4000H then the
physical address is calculated as follows
Microprocessors and Microcontrollers-Module 1-8086
Architecture of 8086
EU-Base Pointer, Source Index and Destination Index (BP, SI and DI):
• These three 16-bit registers can be used as general purpose registers. However, their main use is to hold the 16-bit offset of
the data word in one of the segments.
EU-Base Pointer:
• We can use the BP register instead of SP for accessing the stack using the based addressing. mode. In this case, the 20-bit
physical stack address is calculated from BP and SS.
EU-Source Index:
• Source index (SI) can be used to hold the offset of a data word in the data segment. In this case, the 20-bit physical data
address is calculated from SI.
EU-Destination Index:
• The ES register .points to the extra segment in which data is stored. String instructions always use ES and DI to determine
the 20-bit physical address for the destination.
Microprocessors and Microcontrollers-Module 1-8086
Addressing Modes of 8086
Addressing Modes (AM):
• Addressing mode indicates a way of locating data or operands. Depending upon the data types used in the instruction and the
memory addressing modes, any instruction may belong to one or more addressing modes, or some instruction may not
belong to any of the addressing modes. Thus addressing modes describe the types of operands and the way they are accessed
for executing an instruction.
• According to the flow of instruction execution, the instructions may be categorized as:
• Sequential control flow instructions
• Control transfer instructions
Sequential control flow instructions:
• Sequential control flow instructions are the instructions which after execution, transfer control to the next instruction
appearing immediately after it in the program.
• For example, the arithmetic, logical, data transfer and processor control instructions are sequential control flow instructions
Microprocessors and Microcontrollers-Module 1-8086
Addressing Modes of 8086
Control transfer instructions
• The control transfer instructions, on the other hand , transfer control to some predefined address or the address somehow
specified in the instruction, after their execution.
• For example INT, CALL, RET and JUMP instructions fall under this category
• The addressing modes for sequential control flow instructions are explained as follows:
1. Immediate AM:
• In this type of addressing, immediate data is a part of instruction, and appears in the form of successive byte or bytes .
• For example, MOV AX, 6558H;
MOV BL, 54H;
2. Direct AM:
• In the direct addressing mode, a 16-bit memory address (offset) is directly specified in the instruction as a part of it.
• For example, MOV AX, [5000H];
MOV [2000H], BX;
Microprocessors and Microcontrollers-Module 1-8086
Addressing Modes of 8086
3. Register AM:
• In the register addressing mode, the data is stored in a register and it is referred using the particular register. All the registers,
except IP, may be used in this mode
• For example, MOV AX, BX;
MOV BL, CL;
4. Register Indirect AM:
• Sometimes, the address of the memory location which contains data or operand is determined in an indirect way, using the
offset registers. This mode of addressing is known as register indirect mode . In this addressing mode, the offset address of
data is in either BX or SI or DI register.
• The default segment is either DS or ES. The data is supposed to be available at the address pointed to by the content of any
of the above registers in the default data segment.
• For example, MOV AX, [BX];
Microprocessors and Microcontrollers-Module 1-8086
Addressing Modes of 8086
5. Indexed AM:
• In this addressing mode, offset of the operand is stored in one of the Index registers. DS is the default segment for index
registers SI and DI. In the case of string instructions DS and ES are default segments for SI and DI respectively. This mode
is a special case of the above discussed register indirect addressing mode.
• For example, MOV AX, [SI];
MOV BL, [DI];
6. Register Relative AM:
• In this addressing mode, the data is available at an effective address formed by adding an 8-bit or 16-bit displacement with
the content of any one of the registers BX, BP, SI and DI in the default (either DS or ES) segment.
• For example, MOV AX, 50H[SI];
MOV 10H[DI], AX;
Microprocessors and Microcontrollers-Module 1-8086
Addressing Modes of 8086
7. Based Indexed AM:
• The effective address of the data is formed, in this addressing mode, by adding the content of a base register (any one of BX
or BP) to the content of an index register (any one of SI or DI). The default segment register may be DS or ES.
• For example, MOV AX, [BX][SI];
MOV [BX][DI], AX;
8. Register Based Indexed AM:
• The effective address is formed by adding an 8-bit or 16-bit displacement with the sum of contents of anyone of the base
registers (BX or BP) and any one of the index registers (SI or DI), in a default segment.
• For example, MOV AX, 50H[BX][SI];
MOV 10H[BX][DI], AX;
Microprocessors and Microcontrollers-Module 1-8086
Addressing Modes of 8086
The addressing modes for control transfer instructions are explained as follows
Control transfer flow AM:
• For the control transfer instructions, the addressing modes depend upon whether the destination location is within the same
segment or in a different one. It also depends upon the method of passing the destination address to the processor
• Basically there are two addressing modes for the control transfer instructions, viz, intersegment and intrasegment addressing
modes.
• If the location to which the control is to be transferred lies in a different segment other than the current one, the mode is
called intersegment mode. If the destination location lies in the same segment, the mode is called intrasegment mode
Microprocessors and Microcontrollers-Module 1-8086
Addressing Modes of 8086
9. Intrasegment Direct AM:
• In this mode, the address to which the control is to be transferred lies in the same segment in which the control transfer
instruction lies and appears directly in the instruction as an immediate displacement value.
• For example,
JMP SHORT LABEL; LABEL lies -128 to +127 from the current IP content.
10. Intrasegment Indirect AM :
• In this mode, the address to which the control is to be transferred lies in the same segment in which the control transfer
instruction lies but it is passed to the instruction indirectly. Here the branch address is found as the content of a register or a
memory location.
• For example,
JMP [BX]; Jump to effective address stored in BX.
Microprocessors and Microcontrollers-Module 1-8086
Addressing Modes of 8086
11. Intersegment Direct AM:
• In this mode, the address to which the control is to be transferred lies in a different segment. This AM provides a means of
branching from one code segment to another code segment. Here both CS and IP contents are specified directly in the
instruction.
• For example,
JMP 5000H:2000H; Jump to effective address 2000H in segment 5000H.
12. Intersegment Indirect AM :
• In this mode, the address to which the control is to be transferred lies in a different segment and it is passed to the instruction
indirectly, i.e. contents of memory block containing four bytes, i.e. IP(LSB), IP(MSB), CS(LSB), and CS(MSB)
sequentially.
• For example,
JMP [2000H]; Jump to effective address stored in BX.
Microprocessors and Microcontrollers-Module 1-8086
Instruction Set of 8086
Instruction Set:
• 8086 supports 7 types of instructions.
• Data Transfer Instructions
• Arithmetic Instructions
• Logical Instructions
• Branch and Loop Instructions
• String Instructions
• Flag Manipulation Instructions
• Machine Control Instructions
General Syntax:
Label Instruction Mnemonic Operand 1, Operand 2;
Microprocessors and Microcontrollers-Module 1-8086
Instruction Set of 8086
1. Data Transfer Instructions:
• Instructions that are used to transfer data/ address in to registers, memory locations and I/O ports.
• Generally involve two operands: Source operand and Destination operand of the same size.
• Source: Register or a memory location or an immediate data and Destination : Register or a memory location.
• MOV:MOVE
Microprocessors and Microcontrollers-Module 1-8086
Instruction Set of 8086
1. Data Transfer Instructions:
• PUSH:PUSH POP:POP
Microprocessors and Microcontrollers-Module 1-8086
Instruction Set of 8086
1. Data Transfer Instructions:
• XCHG: Exchange XLAT: Translate
Microprocessors and Microcontrollers-Module 1-8086
Instruction Set of 8086
1. Data Transfer Instructions:
• IN: Input & OUT: Output
Microprocessors and Microcontrollers-Module 1-8086
Instruction Set of 8086
1. Data Transfer Instructions:
• LEA: Load effective address LDS/LES: Load data pointer
Microprocessors and Microcontrollers-Module 1-8086
Instruction Set of 8086
1. Data Transfer Instructions:
•
Microprocessors and Microcontrollers-Module 1-8086
Instruction Set of 8086

:Remaining category of instructions, please go through the

textbooks which I have shared:
Advanced Microprocessors and Peripherals by
KM Bhurchandi & AK Ray-Page no: 43-67
Microprocessors and Microcontrollers-Module 1-8086
Memory Interfacing with 8086

:Please go through the class notes where we have discussed

in detail with examples and also go through the textbooks
which I have shared:
Advanced Microprocessors and Peripherals by
KM Bhurchandi & AK Ray-Page no: 149-158
Microprocessors and Microcontrollers-Module 1-8086
Interrupts of 8086
Interrupts:
• An interrupt is a condition that halts the microprocessor temporarily to work on a different task and then returns to its
previous task. An interrupt is an event or signal that requests the CPU’s attention.
• This halt allows peripheral devices to access the microprocessor. Whenever an interrupt occurs, the processor completes the
current instruction and starts the implementation of an Interrupt Service Routine (ISR) or Interrupt Handler.
• ISR is a program that tells the processor what to do when the interrupt occurs. After the ISR execution, control returns to the
main routine where it was interrupted.
• In the 8086 microprocessor following tasks are performed when the microprocessor encounters an interrupt:
• The CPU pushes the flags register onto the stack.
• The CPU pushes a far return address (segment: offset) onto the stack, segment value first.
• The CPU determines the cause of the interrupt (i.e., the interrupt number) and fetches the four byte interrupt vector
from address 0:vector*4.
• The CPU transfers control to the routine specified by the interrupt vector table entry.
Microprocessors and Microcontrollers-Module 1-8086
Interrupts of 8086
Interrupts:
• Interrupts are particularly useful when interfacing I/O devices that
provide or require data at relatively low data transfer rate.
• The interrupt can came from any of the three sources
• By external signal
• By a special instruction in the program
• By the occurrence of some condition
• An interrupt caused by an external signal is referred as Hardware
interrupt.
• A condition interrupts or interrupts caused by special instructions are
called software interrupts.
Microprocessors and Microcontrollers-Module 1-8086
Interrupts of 8086
Interrupts:
• Interrupts are particularly useful when interfacing I/O devices that provide or require data at relatively low data transfer rate.
• The different types of interrupts present in the 8086 microprocessor are given by:
• Hardware Interrupts
• Software Interrupts
• Hardware Interrupts: Hardware interrupts are those interrupts that are caused by any peripheral device by sending a signal
through a specified pin to the microprocessor. There are two hardware interrupts in the 8086 microprocessor.
• NMI (Non-Maskable Interrupt): It is a single pin non-maskable hardware interrupt that cannot be disabled. It is the
highest priority interrupt in the 8086 microprocessor. After its execution, this interrupt generates a TYPE 2 interrupt.
• INTR (Interrupt Request): It provides a single interrupt request and is activated by the I/O port. This interrupt can be
masked or delayed. It is a level-triggered interrupt. It can receive any interrupt type, so the value of IP and CS will
change on the interrupt type received.
Microprocessors and Microcontrollers-Module 1-8086
Interrupts of 8086
Interrupts:
• Software Interrupts: These are instructions inserted within the program to generate interrupts. Interrupts are generated by a
software instruction and operate similarly to a jump or branch instruction
• There are 256 software interrupts in the 8086 microprocessor. The instructions are of the format INT type, where the type
ranges from 00 to FF. The starting address ranges from 00000 H to 003FF H.
• These are 2-byte instructions. IP is loaded from type * 04 H, and CS is loaded from the following address given by (type *
04) + 02 H.
• ISR: For every interrupt, there must be an interrupt service routine (ISR), or interrupt handler. When an interrupt is invoked,
the microprocessor runs the interrupt service routine.
• For every interrupt, there is a fixed location in memory that holds the address of its ISR. The group of memory locations set
aside to hold the addresses of ISRs is called the interrupt vector table
• When an interrupt is occurred, the microprocessor stops execution of current instruction. It transfers the content of program
counter (CS and IP) into stack.
Microprocessors and Microcontrollers-Module 1-8086
Interrupts of 8086
Interrupts:
• Software Interrupts:
• After this, it jumps to the memory location specified by
Interrupt Vector Table (IVT). After that the code written
on that memory area will execute.
• The first 1Kbyte of memory of 8086 (00000 to003FF)
is set aside as a table for storing the starting addresses
of Interrupt Service Procedures(ISP). Since 4-bytes are
required for storing starting addresses of ISPs, the table
can hold 256 Interrupt procedures.
• The starting address of an ISP is often called the
Interrupt Vector or Interrupt Pointer .Therefore the
table is referred as Interrupt Vector Table.
Microprocessors and Microcontrollers-Module 1-8086
Interrupts of 8086
Interrupts:
• Software Interrupts: Some important software interrupts are
• INT n is invoked as software interrupts- n is the type no in the range 0 to 255(00 to FF). Interrupts are divided into three
groups
• Type 0 to Type4 (Dedicated Interrupts)-
• TYPE 0 interrupt represents division by zero situation. (INT 00H)
• TYPE 1 interrupt represents single-step execution during the debugging of a program. (INT 01H)
• TYPE 2 interrupt represents non-maskable NMI interrupt. (INT 02H)
• TYPE 3 interrupt represents break-point interrupt. (INT 03H)
• TYPE 4 interrupt represents overflow interrupt. (INT 04H/INTO)
• Type 5 to 31(Not used by 8086, reserved for higher processor like 80286, 80386.
• Type 32-255(Available for user) - User defined interrupts
Microprocessors and Microcontrollers-Module 1-8086
Interrupts of 8086-DOS & BIOS
Interrupts: DOS & BIOS
• In PC, part of the operating system is located in the permanent memory (ROM) and part is loaded during power up.
• The part located in ROM is referred to as ROM-BIOS (Basic Input/ Output System).
• The other part which is loaded in RAM during power-up from hard disk is known as DOS(Disk Operating System)
• BIOS is located in a 8 Kbyte ROM at the top of memory, the address range being from FE000H to FFFFFH
• The programs with ROM-BIOS provide the most direct, lowest level interaction with the various devices in the system
• The ROM-BIOS contains routines for
• Power-on self test
• System configuration analysis
• Time of the day
• Print screen
• Boot strap loader
Microprocessors and Microcontrollers-Module 1-8086
Interrupts of 8086-DOS & BIOS
Interrupts: DOS & BIOS
• In PC, part of the operating system is located in the permanent memory (ROM) and part is loaded during power up.
• The part located in ROM is referred to as ROM-BIOS (Basic Input/ Output System).
• The other part which is loaded in RAM during power-up from hard disk is known as DOS(Disk Operating System)
• BIOS is located in a 8 Kbyte ROM at the top of memory, the address range being from FE000H to FFFFFH
• The programs with ROM-BIOS provide the most direct, lowest level interaction with the various devices in the system
• The ROM-BIOS contains routines for
• I/O support program for
• a. Asynchronous communication
• b. Keyboard
• c. Printer
• d. Display
Microprocessors and Microcontrollers-Module 1-8086
Interrupts of 8086-DOS & BIOS
Interrupts: DOS & BIOS
• Most of these programs are accessible to ALP through software interrupt instruction (INT).
• The design goal for the ROM-BIOS programs is to provide a device-independent interface to the various physical devices in
the system.
• Using ROM-BIOS one can output characters to various physical devices like the printer or display, one can read character
from keyboard.
• But still few things are not possible with ROM-BIOS
• It is not possible to provide ability to load and execute programs directly
• It is not possible to store data on the diskette organized as logical files.
• ROM-BIOS have no command-interpreter to allow copying files, print files, deleting files.
Microprocessors and Microcontrollers-Module 1-8086
Interrupts of 8086-DOS & BIOS
Interrupts: DOS & BIOS
• It is the DOS that provides these services.
• When we turn ON our computer, we expect to see message or a prompt.
• We expect to be able to look at the diskette directory to see what data files or programs the diskette contains.
• We expect to run a program by typing name.
• We want to copy programs from one diskette to another, print programs and delete programs.
• All these services are provided by group of programs called DOS.
• The services provided by DOS can be grouped into following categories
Microprocessors and Microcontrollers-Module 1-8086
Interrupts of 8086-DOS & BIOS
Interrupts: DOS & BIOS
• The services provided by DOS can be grouped into following categories.
• Character Device I/O
• File Management
• Memory Management
• Directory Management
• Executive Functions
• Command Interpreter
• Utility Programs
Microprocessors and Microcontrollers-Module 1-8086
Interrupts of 8086-DOS & BIOS
Interrupts: DOS & BIOS
Microprocessors and Microcontrollers-Module 1-8086
Pin Configuration of 8086
PIN Description:
• 8086 was the first 16-bit microprocessor available in 40-pin DIP (Dual
Inline Package) chip. It uses a 5V DC supply for its operation. The
8086 uses a 20-line address bus. It has a 16-line data bus.
• The 20 lines of the address bus operate in multiplexed mode. The 16-
low order address bus lines have been multiplexed with data and 4
high-order address bus lines have been multiplexed with status signals.
• AD0-AD15: Address/Data bus. These are low order address bus. They
are multiplexed with data. When AD lines are used to transmit memory
address the symbol A is used instead of AD, for example A0-A15.
When data are transmitted over AD lines the symbol D is used in place
of AD, for example D0-D7, D8-D15 or D0-D15.
Microprocessors and Microcontrollers-Module 1-8086
Pin Configuration of 8086
PIN Description:
• A16-A19: High order address bus. These are multiplexed with status signals.
• S2, S1, S0: Status pins. These pins are active during T4, T1 and T2 states and
is returned to passive state (1,1,1 during T3 or Tw (when ready is inactive).
These are used by the 8288 bus controller for generating all the memory and
I/O operation) access control signals. Any change in S2, S1, S0 during T4
indicates the beginning of a bus cycle.
• A16/S3, A17/S4, A18/S5, A19/S6 : The specified address lines are
multiplexed with corresponding status signals.
• BHE’/S7: Bus High Enable/Status. During T1 it is low. It is used to enable
data onto the most significant half of data bus, D8-D15. 8-bit device
connected to upper half of the data bus use BHE (Active Low) signal. It is
multiplexed with status signal S7. S7 signal is available during T2, T3 and T4.
Microprocessors and Microcontrollers-Module 1-8086
Pin Configuration of 8086
PIN Description:
• RD’: This is used for read operation. It is an output signal. It is active when low.
• READY : This is the acknowledgement from the memory or slow device that they have completed the data transfer. The
signal made available by the devices is synchronized by the 8284A clock generator to provide ready input to the
microprocessor. The signal is active high(1).
• INTR : Interrupt Request. This is triggered input. This is sampled during the last clock cycles of each instruction for
determining the availability of the request. If any interrupt request is found pending, the processor enters the interrupt
acknowledge cycle. This can be internally masked after resulting the interrupt enable flag. This signal is active high(1)
and has been synchronized internally.
• NMI : Non maskable interrupt. This is an edge triggered input which results in a type II interrupt. A subroutine is then
vectored through an interrupt vector lookup table which is located in the system memory. NMI is non-maskable
internally by software. A transition made from low(0) to high(1) initiates the interrupt at the end of the current
instruction. This input has been synchronized internally.
Microprocessors and Microcontrollers-Module 1-8086
Pin Configuration of 8086
PIN Description:
• INTA : Interrupt acknowledge. It is active low(0) during T2, T3 and Tw of each interrupt acknowledge cycle.
• MN/MX’ : Minimum/Maximum. This pin signal indicates what mode the processor will operate in.
• RQ’/GT1′, RQ’/GT0′ : Request/Grant. These pins are used by local bus masters used to force the microprocessor to
release the local bus at the end of the microprocessor’s current bus cycle. Each of the pin is bi-directional. RQ’/GT0′
have higher priority than RQ’/GT1′.
• LOCK’ : Its an active low pin. It indicates that other system bus masters have not been allowed to gain control of the
system bus while LOCK’ is active low(0). The LOCK signal will be active until the completion of the next instruction.
• TEST’: This examined by a ‘WAIT’ instruction. If the TEST pin goes low(0), execution will continue, else the processor
remains in an idle state. The input is internally synchronized during each of the clock cycle on leading edge of the clock.
• CLK: Clock Input. The clock input provides the basic timing for processing operation and bus control activity. Its an
asymmetric square wave with a 33% duty cycle.
Microprocessors and Microcontrollers-Module 1-8086
Pin Configuration of 8086
PIN Description:
• RESET: This pin requires the microprocessor to terminate its present activity immediately. The signal must be active
high(1) for at least four clock cycles.
• Vcc : Power Supply( +5V D.C.)
• GND : Ground
• QS1,QS0 : Queue Status. These signals indicate the status of the internal 8086 instruction queue according to the table
shown below:
• M/IO’: This signal is used to distinguish between memory and I/O operations. The M Signal is Active high whereas the
IO’ Signal is Active Low. When this Pin is High, the memory operations takes place. On the other hand, when the Pin is
low, the Input/Output operations from the peripheral devices takes place.
• DT/R’ : Data Transmit/Receive. This pin is required in minimum systems, that want to use an 8286 or 8287 data bus
transceiver. The direction of data flow is controlled through the transceiver.
Microprocessors and Microcontrollers-Module 1-8086
Pin Configuration of 8086
PIN Description:
• DEN: Data enable. This pin is provided as an output enable for the 8286/8287 in a minimum system which uses
transceiver. DEN is active low(0) during each memory and input-output access and for INTA cycles.
• HOLD/HOLDA: HOLD indicates that another master has been requesting a local bus .This is an active high(1). The
microprocessor receiving the HOLD request will issue HLDA (high) as an acknowledgement in the middle of a T4 or T1
clock cycle.
• ALE : Address Latch Enable. ALE is provided by the microprocessor to latch the address into the 8282 or 8283 address
latch. It is an active high(1) pulse during T1 of any bus cycle. ALE signal is never floated, is always integer.
Microprocessors and Microcontrollers-Module 1-8086
General Bus Operation of 8086
Bus Operation with Timing Diagrams:
• The 8086 microprocessor supports two modes of operation, Minimum Mode and Maximum Mode. Both modes involve
a bus operation cycle, which is the sequence of steps that the microprocessor follows to read or write data from or to an
external device.
• The 8086 has a combined address and data bus commonly referred as a time multiplexed address and data bus
• The main reason behind multiplexing address and data over the same pins is the maximum utilization of processor pins
and it facilitates the use of 40 pin standard DIP package.
• The bus can be demultiplexed using a few latches and trans-receivers, when ever required
• Basically, all the processor bus cycles consist of at least four clock cycles. These are referred to as T1, T2, T3, T4. The
address is transmitted by the processor during T1. It is Present on the bus only for one cycle.
• The negative edge of this ALE pulse is used to separate the address and the data or status information. In maximum
mode, the status lines S0, S1 and S2 are used to indicate the type of operation. Status bits S3 to S7 are multiplexed with
higher order address bits and the BHE signal.
Microprocessors and Microcontrollers-Module 1-8086
General Bus Operation of 8086
Bus Operation with Timing Diagrams:
• Address is valid during T1 while status bits S3 to S7 are valid during T2 through T4.
• The read cycle begins in T1 with the assertion of address latch enable (ALE) signal and also M / IO signal. During the
negative going edge of this signal, the valid address is latched on the local bus.
• The BHE and A0 signals address low, high or both bytes. From T1 to T4 , the M/IO signal indicates a memory or I/O
operation.
• At T2, the address is removed from the local bus and is sent to the output. The bus is then tristated. The read (RD)
control signal is also activated in T2.
• The read (RD) signal causes the address device to enable its data bus drivers. After RD goes low, the valid data is
available on the data bus.
• The addressed device will drive the READY line high. When the processor returns the read signal to high level, the
addressed device will again tristate its bus drivers.
Microprocessors and Microcontrollers-Module 1-8086
General Bus Operation of
8086
Bus Operation with Timing Diagrams:
• A write cycle also begins with the assertion of ALE and the emission
of the address. The M/IO signal is again asserted to indicate a
memory or I/O operation. In T2, after sending the address in T1, the
processor sends the data to be written to the addressed location.
• The data remains on the bus until middle of T4 state. The WR
becomes active at the beginning of T2 (unlike RD is somewhat
delayed in T2 to provide time for floating).
• The BHE and A0 signals are used to select the proper byte or bytes
of memory or I/O word to be read or write.
• The M/IO, RD and WR signals indicate the type of data transfer as
specified in the timing diagram.
Microprocessors and Microcontrollers-Module 1-8086
General Bus Operation of 8086
Timing Diagrams:
Microprocessors and Microcontrollers-Module 1-8086
Minimum & Maximum
mode 8086 system
Minimum mode:
• In the 8086 microprocessor, there are two modes
of operation: minimum mode and maximum
mode.
• Minimum mode is used when the 8086
microprocessor is operating as a standalone
processor without any external coprocessors or
support chips. In this mode, the 8086 uses a single
8/16-bit bus for both data and instructions, and a
single 20-bit address bus. The minimum mode
requires a minimum set of support chips, such as
clock generator, address latch, and bus controller.
Microprocessors and Microcontrollers-Module 1-8086
Minimum & Maximum
mode 8086 system
Minimum mode:
• When MN/MX’ = 1, the 8086 microprocessor runs
in the minimum mode. All the control signals
required for memory operations and I/O interfaces
are provided by the system’s only processor
running in minimum mode, the 8086, alone. The
circuit in this case is simple, but it does not permit
multiprocessing.
• In this mode, the microprocessor chip itself
transmits all control signals. The system’s latches,
transceiver, clock generator, memory, and I/O
devices make up the remaining parts.
Microprocessors and Microcontrollers-Module 1-8086
Minimum & Maximum
mode 8086 system
Maximum mode:
• Maximum mode is used when the 8086 microprocessor is
operating with one or more external coprocessors or support
chips. In this mode, the 8086 uses a multiplexed bus for data
and instructions, and a 20-bit address bus. The maximum
mode requires additional support chips, such as a bus
controller, a clock generator, and a data buffer.
• When 8086 is used as more than just a processor to perform
calculations, that is when 8086 is operating in maximum
mode. The MN/MX’ pin is connected to the ground to operate
the 8086 in maximum mode. The system’s components are
identical to those in the minimum mode system.
Microprocessors and Microcontrollers-Module 1-8086
Minimum & Maximum mode 8086
system
Maximum mode:
• In this we can connect more processors to 8086
• 8288 bus controller- Address form the address bus is latched
into 8-bit latch. Three such latches are required because address
bus is 20 bit. The ALE(Address latch enable) is connected to
STB(Strobe) of the latch. The ALE for latch is given by 8288
bus controller.
• The data bus is operated through 8-bit transceiver. Two such
transceivers are required, because data bus is 16-bit. The
transceivers are enabled the DEN signal, while the direction of
data is controlled by the DT/R signal. DEN is connected to OE’
and DT/ R’ is connected to T. Both DEN and DT/ R’ are given
by 8288 bus controller.
Microprocessors and Microcontrollers-Module 1-8086
Programmable Peripheral Interface-8255
8255-PPI:
• It is an I/O port chip used for interfacing I/O devices with microprocessor system
• It is device used to implement parallel data transfer between processor and slow peripheral devices like ADC, DAC,
keyboard, 7-segment display, LCD etc.
• It is a programmable device.
• It has 24 I/O programmable pins like PA,PB,PC (port A-C).
• 8255A has three ports-Port A, Port B, and Port C
• Port A and Port B are 8 bit parallel ports. Port C can be split into two parts, i.e. PORT C lower (PC0-PC3) and PORT C
upper (PC7-PC4) by the control word.
• These three ports are further divided into two groups. Group A includes PORT A and upper PORT C. Group B includes
PORT B and lower PORT C
• These two groups can be programmed in three different modes.
Microprocessors and Microcontrollers-Module 1-8086
Programmable Peripheral Interface-8255
8255-PPI:
• These two groups can be programmed in three different modes.
• Three operating modes
• Mode-0(simple I/O port)
• Mode-1(Handshake I/O port)
• Mode-2(Bidirectional I/O port)
• Mode-0: In this mode, Port A and B is used as two 8-bit ports and Port C as two 4-bit ports.
• Each port can be programmed in either input mode or output mode where outputs are latched and inputs are not
latched.
• Ports do not have interrupt capability. Ports in mode 0 is used to interfaces LEDs, Hexa keypad and 7 segment LEDS
to the processor.
• Mode 1: In this mode, Port A and B is used as 8-bit I/O ports. They can be configured as either input or output ports.
• Each port uses three lines from port C as handshake signals.
• Inputs and outputs are latched
Microprocessors and Microcontrollers-Module 1-8086
Programmable Peripheral Interface-8255
8255-PPI:
• Mode 1: :(Input/output with Hand shake)
• In this mode, input or output is transferred by hand shaking Signals.
• Handshaking signals is used to transfer data between whose data transfer is not same.
• For example, the computer send the data to the printer large speed compared to the printer.
• When computer send the data according to the printer speed at the time only, printer can accept.
• If printer is not ready to accept the data then after sending the data bus , computer uses another handshaking signal to
tell printer that valid data is available on the data bus.
• Each port uses three lines from port C as handshake signals
• Mode 2: bi-directional I/O data transfer.
• In this mode, Port A can be configured as the bidirectional port and Port B either in Mode 0 or Mode 1.
• Port A uses five signals from Port C as handshake signals for data transfer.
• The remaining three signals from Port C can be used either as simple I/O or as handshake for port B.
Microprocessors and Microcontrollers-Module 1-8086
Programmable Peripheral Interface-8255
8255-PPI:
• Mode 2: bi-directional I/O data transfer.
• This mode allows bidirectional data transfer over a single 8-bit data bus using handshake signals.
• This feature is possible only Group A
• Port A is working as 8-bit bidirectional.
• PC3-PC7 is used for handshaking purpose.
• The data is sent by CPU through this port , when the peripheral request it.
• CONTROL WORD FORMATS:
• In the INPUT mode , When RESET is High all 24 pins (3-ports) be a input mode
• This condition is maintained even after RESET goes low.
• This can be avoid by writing single control word to the control registers , when required
Microprocessors and Microcontrollers-Module 1-8086
Programmable Peripheral Interface-8255
8255-PPI:
• Pin Configuration
• Data bus(D0-D7):These are 8-bit bi-directional buses, connected
to 8086 data bus for transferring data.
• CS’: This is Active Low signal. It stands for Chip Select. A LOW
on this input selects the chip and enables the communication
between the 8255 and the CPU.
• Read’: This is Active Low signal, when it is Low the
microprocessor reads data from a selected I/O port of 8255A.
• Write’: This is Active Low signal, when it is Low the
microprocessor writes data into a selected I/O port.
• Address (A0-A1):This is used to select the ports.
Microprocessors and Microcontrollers-Module 1-8086
Programmable Peripheral Interface-8255
8255-PPI:
• Pin Configuration
• RESET: This is used to reset the device. That means clear control
registers.
• PA0-PA7:It is the 8-bit bi-directional I/O pins used to send the
data to peripheral or to receive the data from peripheral.
• PB0-PB7:Similar to PA
• PC0-PC7:This is also 8-bit bidirectional I/O pins. These lines are
divided into two groups.
• PC0 to PC3(Lower Groups)
• PC4 to PC7 (Higher groups)
• These two groups working in separately using 4 data’s.
Microprocessors and Microcontrollers-Module 1-8086
Programmable Peripheral Interface-8255
8255-PPI-Block Diagram:
• Block Diagram-Data Bus Buffer
• It is a 8-bit bidirectional Data bus.
• Used to interface between 8255 data bus with system bus.
• The internal data bus and Outer pins D0-D7 pins are connected in
internally.
• The direction of data buffer is decided by Read/Control Logic.
• Read/write: This is getting the input signals from control bus and
Address bus
• Control signal are RD and WR.
• Address signals are A0,A1,and CS.
• 8255 operation is enabled or disabled by CS.
Microprocessors and Microcontrollers-Module 1-8086
Programmable Peripheral Interface-8255
8255-PPI-Block Diagram:
• Block Diagram-Group A and B
• Group A and B get the Control Signal from CPU and send the
command to the individual control blocks.
• Group A send the control signal to port A and Port C (Upper)
PC7-PC4.
• Group B send the control signal to port B and Port C (Lower)
PC3-PC0.
• PORT A:
• This is a 8-bit buffered I/O latch.
• It can be programmed by mode 0 , mode 1, mode 2 .
Microprocessors and Microcontrollers-Module 1-8086
Programmable Peripheral Interface-8255
8255-PPI-Block Diagram:
• Block Diagram-Group A and B
• PORT B:
• This is a 8-bit buffer I/O latch.
• It can be programmed by mode 0 and mode 1.
• PORT C:
• This is a 8-bit Unlatched buffer Input and an Output latch.
• It is divided into two parts.
• It can be programmed by bit set/reset operation.
Microprocessors and Microcontrollers-Module 1-8086
Programmable Peripheral Interface-8255
8255-PPI-Operating Modes
• Two operating modes:
• Bit set/Reset mode
• I/O mode( mode 0, mode 1, mode2)
• Bit set/reset mode: The PORT C can be Set or Reset by sending OUT instruction to the CONTROL registers.
• I/O Mode:
• MODE 0(Simple input / Output):
• In this mode , port A, port B and port C is used as individually (Simply).
• Features:
• Outputs are latched , Inputs are buffered not latched.
• Ports do not have Handshake or interrupt capability
Microprocessors and Microcontrollers-Module 1-8086
Programmable Peripheral Interface-8255
8255-PPI-Operating Modes
• Control Word:
• Two control words:
• I/O mode set control word(MSW)
• Bit set/reset control word(BSR)
• MSW is used to specify I/O functions.
• BSR is used to set/reset individual pins of Port C.
• Both the control words are written in the same control register.
• 8255 ports are programmed by writing control word in the control word in the control register.
• For setting I/O functions and mode of operation the I/O mode set control word is send to control register.
• For setting/ resetting pins of port C, the bit set/reset control word is send to control register.
Microprocessors and Microcontrollers-Module 1-8086
Programmable Peripheral Interface-
8255
8255-PPI-Operating Modes
• Control Word:
• PC0-PC7 is set or reset as per the status of B0.
• A BSR word is written for each bit
• Example: PC3 is Set then control register will be
0XXX0111.
• PC4 is Reset then control register will be 0XXX01000.
• X is a don’t care.
• The control word for both mode is same.
• Bit B7 is used for specifying whether word loaded in to Bit
set/reset mode or Mode definition word.
• B7=1=Mode definition mode.
• B7=0=Bit set/Reset mode.
Microprocessors and Microcontrollers-Module 1-8086
Programmable Peripheral Interface-8255
8255-PPI-Interfacing Example with 8086
• Interface an 8255 with 8086 to work as an I/O port. Intialize Port A as output port, port B as input port, and port
C as output port. Port A address should be 0740H. Write an ALP to sense switch positions SW0-SW7 connected at
port B. The sensed pattern should be displayed on Port A to which 8 LEDs are connected, while port C lower
displays number of ON switches out of total 8 switches.
• Solution: First find the CWR

• The port address decoding can be done as follows:

Microprocessors and Microcontrollers-Module 1-8086
Programmable Peripheral Interface-8255
8255-PPI-Interfacing Example with 8086
• Interface an 8255 with 8086 to work as an I/O port. Intialize Port A as output port, port B as input port, and port
C as output port. Port A address should be 0740H. Write an ALP to sense switch positions SW0-SW7 connected at
port B. The sensed pattern should be displayed on Port A to which 8 LEDs are connected, while port C lower
displays number of ON switches out of total 8 switches.
• Solution: First find the CWR

• The port address decoding can be done as follows:

Microprocessors and Microcontrollers-Module 1-8086
Programmable Peripheral
Interface-8255
8255-PPI-Interfacing Example with 8086
• Interface an 8255 with 8086 to work as an I/O port.
Intialize Port A as output port, port B as input port,
and port C as output port. Port A address should
be 0740H. Write an ALP to sense switch positions
SW0-SW7 connected at port B. The sensed pattern
should be displayed on Port A to which 8 LEDs are
connected, while port C lower displays number of
ON switches out of total 8 switches.
• Solution: Interfacing Diagram
Microprocessors and Microcontrollers-Module 1-8086
Programmable Peripheral
Interface-8255
8255-PPI-Interfacing Example with 8086
• Interface an 8255 with 8086 to work as an I/O port.
Intialize Port A as output port, port B as input port,
and port C as output port. Port A address should
be 0740H. Write an ALP to sense switch positions
SW0-SW7 connected at port B. The sensed pattern
should be displayed on Port A to which 8 LEDs are
connected, while port C lower displays number of
ON switches out of total 8 switches.
• Solution: Program
Thank you