Machine Structure II

Chapter I
Combinational Logic Circuits

Presented by:

BEN SI SAID KARIM

[email protected]
Copyright © Karim Ben Si Said L1 – INFO -2024/2025 1
Chapter objectives

By the end of this chapter, you should be able to:

✓ Understand Combinational Logic – Differentiate between combinational and sequential circuits

✓ Apply Boolean Algebra to Simplify and design logic key combinational logic circuit such as adders, multiplexers,
decoders, and encoders.

✓ Solve Real-World Problems – Implement logic functions using multiplexers, demultiplexers or decoders

Copyright © Karim Ben Si Said L1 – INFO -2024/2025 2

Chapter I Outlines

I. Combinational logic, definitions

II. implementing combinational logic
III. Combinational circuits
IV. Arithmetic circuits
V. Multiplexers and demultiplexers
VI. Code converters

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Chapter- 2: Combinational Logic
Combinational logic- definitions
• A combinational logic system is a component which can assess a combination of Boolean
variables as inputs and gives Boolean outputs according to its logic function. The output or
outputs depend upon the present state of combination of the logic inputs.
• In combinational logic, the outputs depend only on the current values of the inputs, with no
regard for the past input values or for the outputs (feedback)

• Circuits are used in combinatorial logic to carry out operations such as data manipulation
and selection, coding, decoding, etc.

• Logic gates are considered as the basic combinational

logic systems with one output, allowing to perform
basic logic operations between inputs such as NOT,
AND, OR, NAND, NOR, XOR, Etc..)
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Chapter- 2: Combinational Logic
Combinational logic- definitions
• In a combinational logic system, representation is achieved through a box containing inputs and
outputs. Inputs within this system may exist in two forms: normal or complemented.

• The presence of a bubble attached to the box indicates the complemented state for the
corresponding input. (example: input B).

Each output is defined by its logic expression based on the inputs’ values. It remains unaffected by
the states of other outputs or the historical states of that specific input.

A
• In certain combination logic systems, we encounter not B Combinational
LOGIC S1
only inputs and outputs, but also command and control SYSTEM S2
inputs (for example: x, y). N

X Y
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Chapter- 2: Combinational Logic
Implementing combinational logic

The different steps involved in the design of a combinational logic circuit are as follows:

1. Define the Problem Clearly: Statement of the problem and identification of input and
output variables.
2. Expressing the relationship between the input and output variables.
3. Construction of a truth table to meet input–output requirements.
4. Writing Boolean expressions for various output variables in terms of input variables.
5. Minimization of Boolean expressions.
6. Implementation of minimized Boolean expressions.

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Chapter- 2: Combinational Logic
Implementing combinational logic
A combinational logic system
While designing a combinational circuit, The following guidelines should be followed

1. The circuit should have the minimum number of gates, and the gates to use should have the
minimum number of inputs.

2. The number of interconnections should be a minimum to reduce the propagation time from
the inputs to the outputs
3. Consider Fan-out and Fan-in: Avoid excessive fan-out and fan-in to maintain signal integrity.
• fan-out (the number of gates connected to the output)
• fan-in (the number of inputs to a gate).

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Chapter- 2: Combinational Circuits
Combinational circuits
three classes of combinational logic circuits can be distinguished:
• Logic and Arithmetic computation circuits
• Data routing and transmission circuits
• Code converters.

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Chapter II: Combinational Logic

I. Combinational circuits
→ Arithmetic circuits

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Chapter- 2: Combinational circuits

→ Arithmetic circuits

• This category concerns combinational circuits designed for carrying out arithmetic operations,
including addition, subtraction, multiplication, and division, specifically on binary data

• Addition and subtraction are the two most commonly used arithmetic operations, as the other
two, namely multiplication and division, are respectively the processes of repeated addition
and repeated subtraction

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Chapter- 2: Arithmetic circuits
→ Half-Adder
• A half adder is an arithmetic combinational circuit that can be used to perform addition of two
bits. Such circuit has two inputs that represent the two bits to be added and two outputs, with
one producing the SUM bit output and the other producing the CARRY bit.

• To develop such circuit, the previously described steps are followed:

1. Define the inputs and outputs:
– Two inputs (A, B)
– Two outputs (the result of the Sum (S), the carry bit (C))
2. Build the Truth table of the system
3. Derive and simplify the Boolean expressions of the outputs

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Chapter- 2: Arithmetic circuits
→ Half-Adder
A B S C
1. Box Diagram
0 0 0 0
2. Truth Table
0 1 1 0
1 0 1 0
1 1 0 1

3. Simplified logic expression


S= Aഥ. B + A. B
ഥ = AB
C = A. B
4. logic diagram

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Chapter- 2: Arithmetic circuits
→ Full Adder
• The limitation of a half-adder lies in its inability to account for the carry from previous bits
when performing the sum operation for binary numbers with more than one bit.

• To accurately handle multi-bit additions, it becomes necessary to incorporate a full-adder

circuit, which considers not only the current bit but also the carry generated from previous bit
additions, Carry 11
A A 1110
B
Full S
Adder B 0110
Cin Cout
S 10100

• Thus the full-adder performs additions between three bits: two bits of the numbers to sum A
and B, and the carry bit from the previous two bits addition CIN

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Chapter- 2: Arithmetic circuits
→ Full-Adder
3. Simplified logic expression
1. Box Diagram
ഥ. B + Cin A. B
S = Cin A ഥ.B
ഥ + Cin A ഥ + Cin A. B

Cin A B S Cout ഥ . Cin B + Cin . B

S=A ഥ + 𝐴. (Cin. B + Cin . B
ഥ
0 0 0 0 0 ഥ . Cin B + 𝐴. (Cin B)
S=A
0 0 1 1 0
𝑺 = 𝐀.  𝐂𝐢𝐧 𝐁
2. Truth Table 0 1 0 1 0
0 1 1 0 1
ഥ . B + Cin A. B
Cout = Cin A. B + Cin A ഥ + Cin A. B
1 0 0 1 0
1 0 1 0 1 Cout = AB. Cin + Cin + Cin. A B
1 1 0 0 1 𝐂𝐨𝐮𝐭 = 𝐀𝐁 + 𝐂𝐢𝐧. 𝐀𝐁
1 1 1 1 1
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Chapter- 2: Arithmetic circuits
→ Full-Adder

4. logic diagram

Thus, a full adder performs

addition between three bits
and has two outputs: sum 𝑺 = 𝐀.  𝐂𝐢𝐧 𝐁
result (S) and carry (Cout)

• It contains two Half-adders

𝐂𝐨𝐮𝐭 = 𝐀𝐁 + 𝐂𝐢𝐧. 𝐀 𝐁
(green, orange)

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Chapter- 2: Arithmetic circuits
→ Multiple-bits Adder
• To perform addition between two
binary numbers A, B with N bits each,
N adders should be used

• We perform addition from LSB (a0+b0)

to MSB (an+bn), the LSB bits don’t
have a previous carry bit, thus they
require only ½ adder

• The carry-bit input of each full adder

receives the carry-bit output of the
previous adder.

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Chapter- 2: Arithmetic circuits
→ Cascaded adder

Parallel adder is a multiple bit adder, this circuit exists as an integrated circuit, it performs
addition of two 4-bits numbers

• Exercise:

Draw the logic diagram of a two 8-bits

numbers adder using the 74LS283
integrated circuit (IC)

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Chapter- 2: Arithmetic circuits
→ Half-Subtractor
• A half subtractor is an arithmetic combinational circuit that can be used to perform
subtractions of two bits. Such circuit has two inputs that represent the two bits to be
subtracted and two outputs, with one producing the Difference bit output and the other
producing the Borrow bit.

• The BORROW output specifies whether a ‘1’ has been borrowed to perform the subtraction.

To develop such circuit, the same steps as in half adder are followed:

1. Define the inputs and outputs:

– Two outputs (the result of the Difference (D), the Borrow bit (Bout))
– Two inputs (A, B) A
2. Build the Truth table of the system Half D

3. Derive and simplify the Boolean expressions of the outputs B Subtractor Bout
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Chapter- 2: Arithmetic circuits
→ Half-Subtractor A B D Bout
0 0 0 0
1. Box Diagram
2. Truth Table 0 1 1 1
1 0 1 0
1 1 0 0

D =AB
3. Simplified logic expression

D= A ഥ. B + A. B
ഥ = AB 4. logic diagram
ഥ. B
Bout = A ഥ B
Bout = A.

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Chapter- 2: Arithmetic circuits
→ Full Subtractor
• The limitation of a half-subtractor lies in its inability to manage the borrow bits when
performing the subtraction operation for binary numbers with more than one bit.

• To handle multi-bit subtraction, it becomes necessary to incorporate a full-Subtractor circuit,

which considers not only the current bit but also the borrow-bits.

A
Full D
B
Bin Subtractor Bout

• Thus the full-adder performs additions between three bits: two bits of the numbers to sum A
and B, and the carry bit from the previous two bits addition CIN
Copyright © Karim Ben Si Said L1 – MI -2024/2025 20
Chapter- 2: Arithmetic circuits
→ Full-Subtractor
1. Box Diagram 3. Simplified logic expression
The expression of the difference output D is determined
following the same method as in the full-adder:
2. Truth Table
D = A.  B  BIN
A B BIN D Bout
0 0 0 0 0 For the expression of the Borrow output Bout, a Karnaugh
0 0 1 1 1 map is determined the simplified expression:
0 1 0 1 1 B BIN
A 00 01 11 10
0 1 1 0 1
0 0 1 1 1
1 0 0 1 0
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0 ഥ. BIN + A
ഥ. B
Bout = B. BIN + A
1 1 1 1 1
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Chapter- 2: Arithmetic circuits
→ Full-Subtractor
4. logic diagram
Thus, a full subtractor performs subtraction between three bits and has two outputs: difference result (D)
and Borrow (Bout)

D = A.  B  BIN

ഥ. BIN + A
Bout = B. BIN + A ഥ. B
Bout

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Chapter- 2: Arithmetic circuits
→ Cascaded Subtractor
Also known as Multiple bits or parallel subtractor
• Exercise:

Develop a subtractor of two numbers with 4-bits each, using the 74283 IC (4-bits binary adder)
and the two’s complement calculation method 𝐴 − 𝐵 = 𝐴 + (−𝐵)

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Chapter- 2: Arithmetic circuits

→ Magnitude Comparator
• A magnitude comparator is an arithmetic combinational circuit that can compare between two
binary numbers. It allows to detect whether two numbers are equal or different, and indicates if
a number is greater or smaller than another.

• To achieve that, we begin with comparison of

Two 1-bit numbers comparator : the outputs are:

✓ G = 1 when A is greater than B

✓ S = 1 when A is smaller than B

✓ E = 1 when A is equal to B

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Chapter- 2: Arithmetic circuits
→ 1-bit-Magnitude Comparator
• A 1-bit magnitude comparator is used to compare between two 1-bits binary numbers A and B.
It indicates: equality superiority and inferiority.

G= S= E=
A B
A>B A<B A=B
0 0 0 0 1
0 1 0 1 0
1 0 1 0 0
1 1 0 0 1
ഥ
𝐺 = A. B
𝑆=A ഥ. B
𝐸=A ഥ. B
ഥ + A. B = AB

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Chapter- 2: Arithmetic circuits
→ 1-bit-Magnitude Comparator
• The equality expression can be expressed in terms of the S and G outputs
ഥ
𝐺 = A. B
𝑆=A ഥ. B
𝐸=A ഥ. B
ഥ + A. B = AB
𝐸 = (𝐺 + 𝑆)′


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Chapter- 2: Arithmetic circuits
→ 2-bits-Magnitude Comparator
Example: Create a 2-bits comparator using 1-bit comparators and some logic gates

For 2-bit numbers A(a1 a0) and B(b1 b0):

• 𝐀 = 𝐁 if a1 = b1 And a0 = b0
• 𝐀 > 𝐁 if a1 > b1 Or a1 = b1 And a0 > b0
• 𝐀 < 𝐁 if a1 < b1 Or a1 = b1 And a0 < b0

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Chapter- 2: Arithmetic circuits
→ 8-bits-Magnitude Comparator

Exercise:
1. Create a 4-bits comparator using 1-bit
comparators and some logic gates

2. Create an 8-bits comparator by

cascading two 7485 IC

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Chapter II: Combinational Logic

I. Combinational circuits
→ Data routing and transmission circuits:
Multiplexer and demultiplexer circuits

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Chapter- 2: Data routing and transmission
→ Multiplexer
• The multiplexer (MUX) is a data selector or converging switch. It can transform information
presented in the form of n parallel bits into information presented in the form of n serial bits.

• A multiplexer has several inputs (I0, I1, … IN) and one output (S). The output is connected to the
input (I0 for example) being selected using the address inputs (A0, A1, … AM).

• Thus, the addresses allow the selection of one data

input, and directing it towards the output S.

• A beverage vending machine operates like a

multiplexer, where each drink button serving as an
address input. Pressing a button directs the machine
to dispense the corresponding drink.

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Chapter- 2: Data routing and transmission
→ Multiplexer
• The number M of addresses inputs (Ai ) depends on the number N of the inputs (Ii ).
Ln(N)
𝑁 = 2𝑀 => M = Ln(2)

Example 1 : develop a 4x1 mux

➢ with N = 4 inputs, we need N = 2 inputs for address A0 and A1

➢ The input combinations 00, 01, 10 and 11 on the select lines respectively A1 A0 S
switch I0, I1, I2 and I3 to the output. 0 0 I0
0 1 I1
ഥ0 A
S =A ഥ1. I0 + A
ഥ0 A1. I1 + A0 A
ഥ1. I2 + A0 A1. I3
1 0 I2
1 1 I3
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Chapter- 2: Data routing and transmission
→ Multiplexer
The logic diagram of the 4x1 multiplexer is given bellow

A1
A0
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Chapter- 2: Data routing and transmission
→ Multiplexer
• In certain combinational logic circuits, an enable input is used. It allows to activate or disactivate
the circuit.

Example 2: develop a 2x1 mux with Enable input (En)

En
➢ For 𝑁 = 2, => 𝑀 = 1, we need 1 input for address A0

The output takes the value of the inputs only when the system in
enabled (En = 0)
En A0 S
ഥ 0 En. I0+ A0En. I1
S =A 1 X 0
0 0 I0
0 1 I1
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Decimal A B C F2
Chapter- 2: Data routing and transmission 0 0 0 0 0
→ function implementation with multiplexer 1 0 0 1 0
2 0 1 0 1
• One of the most common applications of a multiplexer is its use for
3 0 1 1 0
implementation of combinational logic Boolean functions.
4 1 0 0 1
Example: implement the following expression F using a 8-to-1 MUX 5 1 0 1 0
6 1 1 0 0
F A, B, C = ෍ 2, 4, 7 7 1 1 1 1

• The function F has true value (1) for the three minterms (2, 4 and 7)
present in the given Boolean function, and false value (0) for the
other combinations (0, 1, 3, 5, and 6)

• Thus, the three minterms inputs are tied to logic ‘1’. The remaining
five possible minterms absent in the Boolean function are tied to
logic ‘0’.
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Chapter- 2: Data routing and transmission
→ Demultiplexer
• The demultiplexer (DEMUX) is a data switching circuits. Contrary to
multiplexer, a demultiplexer can transform information presented in the form
of n bits word into information presented in the form of n parallel bits.
• A demultiplexer has several outputs (S0, S1, … SN) and one input (I). The input
is directed to the output (S1 for example) being selected using the address
inputs (A0, A1, … AM).

• The classification of coins in a beverage machine can be considered an

example of a demultiplexer-like operation. The machine is sorting or
classifying the introduced coin (1 input) based on its value.

• Each type of coin represents a distinct output channel, and the

demultiplexer-like process ensures that each coin goes to the correct
compartment.
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Chapter- 2: Data routing and transmission
→ Demultiplexer
• As for the multiplexer, the number M of addresses bits (Ai ) depends on
the number N of the outputs (Ii ).
Ln(N)
𝑁 = 2𝑀 => M = Ln(2)

Example : develop a 1x4 Demux with enable input

➢ For 𝑀 = 4, 𝑁 = 2, we need 2 inputs for address A0 and A1

➢ Each selected output takes the value of the input for a En A1 A0 S0 S1 S2 S3
corresponding address 0 X X 0 0 0 0
1 0 0 I 0 0 0
ഥ0 A
S0 = A ഥ1. I. En
1 0 1 0 I 0 0
𝑆1 = ഥA0 A1. I. En
1 1 0 0 0 I 0
ഥ1. I. En
𝑆2 = A0 A
1 1 1 0 0 0 I
𝑆3 = A0 A1. I. En
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Chapter- 2: Data routing and transmission
→ Demultiplexer
• The logic diagram of the 1-to-4 demultiplexer is given bellow

ഥ0 A
𝑆0 = A ഥ1. I. En
𝑆1 = ഥA0 A1. I. En
ഥ1. I. En
𝑆2 = A0 A
𝑆3 = A0 A1. I. En

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Chapter- 2: Data routing and transmission
→ Mux-Demux
• With its capability to transform information presented in the form of n parallel bits into
information presented in the form of n serial bits, a multiplexer is valuable for facilitating data
transmission across a data bus

Example: Instead of using 8-bits bus to transmit data (fig-1), with a 8x1 MUX and 1x8 DEMUX , we
can use only one wire for the transmission bus (fig-2)

(fig-1) (fig-2)
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Chapter- 2: Data routing and transmission
→ Encoder
• An encoder is a multiplexer without its single output line. It has n output lines and 2N or fewer
inputs. The output corresponds to a binary code of the inputs on N lines (bits).

• Thus, such system converts a binary input to a unique binary code output

• There are different types of encoders:

➢ 4 to 2 Encoder
➢ Octal to Binary Encoder (8 to 3 Encoder)
➢ Decimal to BCD Encoder
➢ Priority Encoder

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Chapter- 2: Data routing and transmission
→ Encoder Example: Decimal to BCD Encoder
Each output Ai is true when some inputs are true.
e.g. from the table of truth, A3 is ‘ 1’ when 8 or 9 are true
➢ 𝐴3 = 8 + 9
➢ 𝐴2 = 4 + 5 + 6 + 7
➢ 𝐴1 = 2 + 3 + 6 + 7
➢ 𝐴0 = 1 + 3 + 5 + 7 + 9

This type of encoder has ten inputs—one for each decimal digit—and four outputs corresponding to the BCD code, as
shown in Figure 6–36. This is a basic 10-line-to-4-lin 1
1

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Chapter- 2: Data routing and transmission
→ Encoder – an application
• Decimal to BCD Encoder can be used to encode the ten decimal digits on a numeric keypad
for processing by the logic circuitry.
• For the 0 key, no encoding is necessary; however, this line may be connected to other
circuits that detect the key press

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Chapter- 2: Data routing and transmission
→ Priority Encoder
• A priority encoder is designed to address the challenge that arises when multiple inputs of an
encoder are simultaneously activated. A priority is assigned to each input.

• It efficiently identifies and encodes the highest-priority active input, ensuring that the output
accurately reflects the most significant input, thus resolving conflicts and providing a
systematic approach to handle multiple input signals.

• The priority function means that the encoder will produce a code for the output corresponding
to the highest-order decimal digit input that is active and will ignore any other lower-order
active inputs

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D3 D2 D1 D0 A B
Chapter- 2: Data routing and transmission
0 0 0 0 X X
→ Priority Encoder 0 0 0 1 0 0

Example: Design 4 inputs priority encoder where: D3 has the 0 0 1 X 0 1

highest priority 0 1 X X 1 0
1 X X X 1 1
A = D2 + D 3 B = D3 + D1 D2’

A B
D1 D0 D1 D0
D3 D2 00 01 11 10 D3 D2 00 01 11 10
00 X 0 0 0 00 X 0 1 1
01 1 1 1 1 01 0 0 0 0
11 1 1 1 1 11 1 1 1 1
10 1 1 1 1 10 1 1 1 1

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Chapter- 2: Data routing and transmission
→ Decoder
• A decoder is a digital circuit that detects the presence of a specified combination of bits (code) on
its inputs and indicates the presence of that code by a specified output level.

• A decoder is a demultiplexer without its single input line. It has N input lines and 2N or fewer
outputs. Each output represents the code of the N bit inputs.

• Thus, such system decodes a unique binary input to a unique binary code output.

• There are different types of decoders:

➢ Basic binary decoder

➢ 4-bits decoder
➢ BCD to decimal decoder

44
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Chapter- 2: Data routing and transmission
→ Decoder - Basic decoder
• In basic decoder are used usually to decode and indicate that some combinations are present
at the input.

Example: we need to create a decoder which indicates when a binary 1001 occurs on the
inputs of a digital circuit.

• In this case, the decoder has 4 inputs, and 1 output 𝑆 ; a HIGH level is produced when the right
combination (1001) occurs on the inputs (𝐴0 = 1, 𝑎𝑛𝑑 𝐴1 = 0, 𝑎𝑛𝑑 𝐴2 = 0, 𝑎𝑛𝑑 𝐴3 =1).

𝑆 = A0 ഥA1 A
ഥ2 A3

45
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Chapter- 2: Data routing and transmission
→ Decoder – 4-bits decoder
Decoding functions and truth table for a 4-line to 16-line (1-of-16) decoder with active-low outputs

46
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Chapter- 2: Data routing and transmission

→ Decoder – BCD to decimal decoder

a decimal digit output (0,1,..9) is activated (false) for its corresponding BCD Code

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Chapter- 2: Data routing and transmission
→ Decoder – an application
• As with multiplexer and demultiplexer, it possible also to build logic functions using
decoders.
Example: develop a half-adder using a 2x4 decoder and some logic gates
The expressions of the outputs for the half-adder are:

ഥ . B + A. B
S = AB = A ഥ
C = A. B

ഥ. B or A. B
The output S is true for the combinations A ഥ

The output C is true for the combinations A. B

Exercise: develop a full-adder using a 3x8 decoder and some logic gates
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Chapter II: Combinational Logic

I. Combinational circuits
→ Code Converters

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Chapter- 2: Code converters
→ Code converters
• Code converters or transcoders allow to transition between different coding format. They
enable the conversion from one code to another.

• Here are few examples of code converters

➢ Binary to Gray Code Converter:

➢ Gray to Binary Code Converter:
➢ BCD to Excess-3 Code Converter:
➢ 7-Segment Display Decoder:
➢ ASCII to Binary Converter:

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Chapter- 2: Code converters
→ Code converters – BCD to 7 segments
• 7 segment display has 7 lighting segment (a, b,
c, d, e, f, g and a dot LED dt)
• To display a decimal digit, we consider the dec w x y z a b c d e f g
0 0 0 0 0
inputs from 0 to 9, the remaining combinations
1 0 0 0 1
(10, 11, 12, 13, 14 and 15) are prohibited. 2 0 0 1 0
3 0 0 1 1
Exercise: 4 0 1 0 0
5 0 1 0 1
1. Complete the following truth table with the 6 0 1 1 0
missing values 7 0 1 1 1
8 1 0 0 0
2.Simplify the expressions of each output a, b, c, 9 1 0 0 1
d, e, f, g with Karnaugh map 10 1 0 1 0 X X X X X X X
11 1 0 1 1 X X X X X X X
3.Draw the logic diagram of this transcoder 12 1 1 0 0 X X X X X X X
13 1 1 0 1 X X X X X X X
14 1 1 1 0 X X X X X X X
15 1 1 1 1 X X X X X X X
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Said L1 – MI -2024/2025
Chapter- 2: Code converters
→ Code converters – Gray to Binary
Exercise 2:

As in the previous exercise, develop a 3-bits Gray to binary converters

1. Create the truth table
2.Simplify the expressions of each output a, b, c with Karnaugh map
3.Draw the logic diagram of this transcoder

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➢ BY THE END OF THIS CHAPTER,

The students should be able to :

• Understand the concept of combinational logic

• Design a combinational logic circuits to perform arithmetic, transcoding or data

routing operations

• Implement logic functions using multiplexers, demultiplexers or decoders

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