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MODULE 3 :
BASIC SRUCTURE OF COMPUTERS

1. FUNCTIONAL UNITS

• A computer consists of 5 functionally independent main parts:

1) Input
2) Memory
3) ALU
4) Output & Input unit
5) Control units.

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2. BASIC OPERATIONAL CONCEPTS

• An Instruction consists of 2 parts, 1) Operation code (Opcode) and 2) Operands.

OPCODE OPERANDS
• Data/operands are stored in memory.
• The individual instruction are brought from the memory to the processor.
• Then, the processor performs the specified operation.
• Let us see a typical instruction
ADD LOCA, RO
• This instruction is an addition operation. The following are the steps to execute the
instruction Step 1: Fetch the instruction from main-memory into the processor.
Step 2: Fetch the operand at location LOCA from main-memory into the processor.
Step 3: Add the memory operand (i.e. fetched contents of LOCA) to the contents of
register RO. Step 4: Store the result (sum) in RO.
• The same instruction can be realized using 2 instructions as:
Load LOCA, R1
Add R1, RO
• The following are the steps to execute the instruction:
Step 1: Fetch the instruction from main-memory into the processor.
Step 2: Fetch the operand at location LOCA from main-memory into the
register Rl. Step 3: Add the content of Register Rl and the contents of register
RO.
Step 4: Store the result (sum) in RO.

MAIN PARTS OF PROCESSOR

• The processor contains ALU, control-circuitry and many registers
• The processor contains n general-purpose registers R0 through Rn-1

• The IR holds the instruction that is currently being exec ted.

• The control-unit generates the timing-signals that determine t h e given action is to take
place.
• The PC contains the memory-a dress of the next-instruction to be fetched & executed.
• During the execution of an instruction, the contents of PC are updated to point to next
instruction.
• The MAR holds the address of the memory-location to be accessed.
• The MDR contains the data to be written into or read out of the addressed location.
• MAR and MDR facilitates the communication with
memory.
• (IR Instruction-Register, PC Program Counter)
• (MAR Memory Address Register, MDR Memory Data Register)

STEPS TO EXECUTE AN INSTRUCTION

1) The address off instruction (to be executed) gets loaded into PC.
2) The contents of PC (i.e. address) are transferred to the MR & control-unit issues Read
signal to memory.
3) After certain amount of lapsed time, the first instruction is read out of memory and
placed into MDR.
4) Next, the contents of MDR a e transferred to IR. At this point, the instruction can be decoded &

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executed.
5) To fetch an operand, its address is placed into MAR & control-unit issues Read signal. As
a result, the operand is transferred from memory into MDR, and then it is transferred from
MDR to ALU.
6) Likewise required number of operands is fetched into processor.

7)Finally, ALU performs the desired operation.

8)If the result of this operation is to be stored in the memory, then the result is sent o the MDR.
9)The address of the location where th e result is to be stored is sent to the MAR and a Write
cycle is initiated.
10)At some point during execution, contents of PC are incremented to point to next instruction
in the program.

3. BUS STRUCTURE

• A bus is a group of lines that serves as a computer path for several devices.
• A bus may be lines or wires.
• The lines carry data or address or control signal

1) There are 2 types of Bus structures: 1) Single Bus structure and 2) Multiple Bus s ructure
2) Single Bus Structure
► Because the bus can be used for only one transfer at a time, only 2 units can actively use
the bus at any given time.
►Bus control lines a e used to arbitrate multiple requests for use of the bus.
► Advantages:
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1) Low cost &

2) Flexibility for attach ng peripheral devices.
3) Multiple Bus Structure

► Systems that contain multiple buses achieve more con currency in operations.
► Two or more transfers can be carried out at the same time.
Advantage: Better performance.
► Disadvantage: Increased cost.

• The devices connected to a bus vary widely in their speed of ope ration.
• To synchronize their op rational-speed, buffer-registers can be used.

• Buffer Registers
_ are included with the devices to hold t he information during transfers.
_ prevent a high-speed processor from being locked to a slow I/0 device during data transfers.

4. PERFORMANCE

1. Processor clock
2. Basic performance equation
3. Clock rate
4. Performance measurement

• The most important measure of performance of computer is how quickly it can execute program
• The speed of a computer is affected by the design of
1) Instruction-set.
2) Hardware & the technology in which the hardware is implemented
3) Software including the operating system .
• Because programs are usually written in a HLL, performance is also affected by the compiler
that translates programs into machine language. (HLL High Level Language).
• For best performance, it is necessary to design the compiler, machine instruction set and hardware
in a co ordinated way.

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• Let us examine the flow of program instructions and data between the memory & the processor.
• At the start of execution, all program instructions are stored in the main-memory.
• As execution proceeds, instructions are fetched into the processor, and a copy is placed in the cache.
• Later, if the same instruction is needed a second time, it is read directly from the cache.
• A program will be executed faster
if movement of instruction/data between the main-memory and the processor is minimized
which is achieved by using the cache.

4.1 PROCESSOR CLOCK

PROCESSOR CLOCK
• Processor circuits are controlled by a timing signal called a Clock.
• The clock defines regular time intervals called Clock Cycles.
To execute a machine instruction, the processor divides the action to be performed into a
sequence of basic steps such that each step can be completed in one clock cycle.

R=1/P

• Let P = Length of one clock cycle

• R = Clock rate.
• Relation between P and R is given by
• R is measured in cycles per second.
• Cycles pe second is also called Hertz (Hz)

4.2 BASIC PERFORMANCE EQUATION

BASIC PERFORMAN CE EQUATION
• Let T = Processor time r e q u i r e d to executed a
program.
N = Actual number of instruction executions.
S = Average number of basic steps needed to execute one machine
instruction.
R = Clock rate in cycles per second.
• The program execution time is given by
T=N*S/R….(1)
• Equation 1 is referred to as the basic performance equation.
• To achieve high performance, the computer designer must require a value of T, which
means reducing N and S, and increasing R.

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The value of N is reduced if source program is compiled into fewer machine

instructions.
The value of S is reduced if instructions have smaller number of basic steps to
perform.
► The value of R can be increased by using a hi her frequency clock.
• Care has to be taken while modifying values since changes in one p rameter may affect the other.

4.3 CLOCK RATE

t
r.
This reduces the time needed to compute a basic step. (ICintegrated c rcuits).
This allows the clock period P to be reduced and the clock rate R to be increased.
2) Reducing the amount of processing done in one basic step also reduces the clock period P.
• In presence of a cache, the percentage of accesses to the main-memory is small.
Hence, much of performance-gain expected from the use of faster technology can be realized.
The value of Twill be reduced by same factor as R is increased,,." S & N are not
affected.

4.4 PERFORMANCE MEASUREMENT

PERFORMA NCE MEASUREMENT
• Benchmark refers to standard task used to measure how well a processor operates.
• The Performance Measure is the time taken by a computer to execute a given benchmark.
• SPEC selects & publishes the standard programs along with their test results for different
application domains. (SPEC System Performance Evaluation Corporation).

SPEC Rating is given by

• SPEC rating = 50 The computer under test is 50 times as fa st as reference-computer.

• The test is repeat for all the programs in th SPEC suite. Then
the geometric mean of the results is computed.
• Let SPEC = Rating fo r program ,,i' in the suite.
Overall SPEC rating for the computer is given by

where n = no. of programs in the suite

Problem 1:
List the steps needed to execute the machine instruction
add Ro, LOC
in terms of transfers between the components processor and some simple control commands. Assume that
the address of the memory-location containing this instruction is initially in register PC.
Solution:
1. Transfer the contents of register PC to register MAR.
2. Issue a Read command to memory.
And, then wait until it has transferred the requested word into register MDR.
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3. Transfer the instruction from MDR into IR and decode it.

4. Transfer the address LOCA from IR to MAR.
5. Issue a Read command and wait until MDR is loaded.
6. Transfer contents of MDR to the ALU
7. Transfer contents of R0 to the ALU.
8. P reform addition of the two operands in the ALU and tran sfer result into RO.
9. Transfer contents of PC to ALU.
10. Add 1 to operand i ALU and transfer incremented address to PC.

ocessor and some simple control commands.

Assume that the address of the memory-location containing this instruction is initially in register PC.
Solution:
1. Transfer the contents of register PC to register MAR.
2. Issue a Read command to memory.
And, then wait until it has transferred the requested word into register MDR.
3. Transfer the instruction from MDR into IR and decode it.
4. Transfer contents of Rl and R2 to the ALU.
5. Perform addition of two operands in the ALU and transfer answer into R3.
6. Transfer co tents of PC to ALU.
7. Add 1 to operand in ALU and transfer incremented address to PC.

Problem 3:
A program contains 1000 instructions. Out of that 25% instructions requires 4 clock cycles,40% instructions
require 5 clock cycles and remaining require 3 clock cycles for execution. Find the total time required to
execute the program running in a 1 GHz machine.
Solution:
N = 1000
25% of N= 250 instructions require 4 clock cycles.
40% of N =400 instructions require 5 clock cycles. 35% of
N=350 instructions require 3 clock cycles.
T = (N*S)/R= (250*4+400*5+350*3)/1X10 9 =(1000+2000+1050)/1*109= 4.05 µs.

steps needed / machine instruction = 20

Solution:

INSTRUCTION SET: CISC AND RISC

RISC CISC
Simple instructions taking one cycle com intructions taking multiple cycle.
Instructions are executed by hardwired control Instructions are executed by microprogrammed
unit. control unit.
Few Instructions Many instructions.
Fixed format instructions. Variable format instructions.
Few addressing modes and most instructions Many addressing modes.
have register to register addressing mode.
Multiple register set . Single register set.
Highly pipelined. No pipelined or less pipelined.
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MACHINE INSTRUCTIONS AND PROGRAMS

5. MEMORY LOCATION AND ADDRESSES

1. Byte addressability
2. Big Endian & Little-Endian assignments
3. Word alignment
4. Accessing Numbers, Characters, Character string

• Each cell can store a bit of information i.e. 0 or 1 (Figure 2.1).

• E ach group of n bits is referred to as a word of information, and n is called the word length.
• The word length can vary from 8 to 64 bits. A
unit of 8 bits is called a byte.
• Accessing the memory to store or retrieve a single item o information (word/byte) requires distin ct
addresses for each item locat ion. (It is customary to use numbers from O through 2k-1 as the addresses
of successive-locations in the memory).
• If 2k = no. of addressable locations;
then 2k addresses constitute the address-space of the computer.
For example, a 24-bit address generates an address-space of 224 locations (16 MB).

Fig. Memory word

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Fig: Example of encoding information of 32 bit word

BIG-ENDIAN & LITTLE-ENDIAN ASSIGNMENTS

• There are two ways in which byte-addresses are arranged (Figure 2.3).
1) Big-Endian: Lower byte-addresses are used for the more significant bytes of the word.
2) Little-Endian: Lower byte-addresses a e used for the less significant bytes of the word
• In both cases, byte-addresses 0, 4, 8........... a e taken as the addresses of successive words in the
memory.

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• Consider a 32-bit integer (in ex): 0x12345678 which consists of 4 bytes: 12, 34, 56, and 78.
►Hence this integer will occupy 4 bytes n memory.
Assume, we store it at memory address starting 1000.

On little-endian, memory will look like Address Value

1000 78
1001 56
1002 34
1003 12
On big-endian, memory will look like
Address Value
1000 12
1001 34
100
100

WORD ALLIGMENT
• Words said to be Aligned in memory if they begin at a byte-address that is multiple e o f the number
of bytes

Example

• If word length 32 bits, aligned words begin at byte addresses 0,4,8

• If word length16(2 bytes), aligned words begin at byte-addresses 0, 2, 4 ....
• If the word length is 64(2 bytes), ligned words b gin at byte-addresses 0, 8, 16 .....
Words are said to have Unaligned Addresses if t ey begin at an arbitrary byte-address.

6. MEMORY OPERATION

• To memory operations are:

1)Load (Read/Fetch) &
2) Store (Write).
• The Load operation transfers a copy of the contents of a specific memory-location to the
p r o cessor. The memory contents remain unchanged.
• Steps for Load operation:
1) Processor sends the address of the desired location to the memory.
2) Processor issues ,,read" signa to memory to fetch the data.
3 Memory reads the data stored at that address.
4) Memory sends the re d data to the processor.
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• The Store operation transfers the information from the register to the specified
memory- location. This will destroy the original contents of that memory-
location.
• Steps for Store operation are:
1) Processor sends the address of the memory-location where it wants to store data.
2) Processor is use,, write" signal to memory to store the data.
3) Content of register(MDR) is written into the specified memory-location.

7. INSTRUCTIONS & INSTRUCTION SEQUENCING

1. Register transfer notation
2. Assembly language notation
3. Basic instruction types
4. Instruction execution & straight-line sequencing
5. Branching
6. Conditional codes

• A computer must have instructions capable of performing 4 types of operations:

1) Data transfers between the memory and the registers (MOV, PUSH, POP, XCHG).
2) Arithmetic and logic operations on data (ADD, SUB, UL, DIV, AND, OR, NOT).
3) Program sequencing and control (CALL.RET, LOOP, IN).
4) 1/0 transfers (IN, OUT).

2 types of notation :
1. RTN
2. ALN

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BASIC INSTRUCTION TYPES

Inst Syntax Example Description Instructio

ruction ns for
Type Operatio
n C<-
[A]+[B]
Three code Add A,B,C Add the contents
Add Sourcel,Source2,Destination of memory-
res s locations A & B.
Then, place the result i
location C.
Two Opcode Source, Destination Add A,B Add the contents Move B,
Address of memory- C Add
locations A & B. Then, A, C
place the result into
location Balancing the
original
contents of this
location.
Operand B is both a
source and a
destination.
One Opcode Source/Destination Load A Copy contents of Load
Address memory- location A into A Add
accumulator. B
Add B Ad c ontents of Store
memory- location B to C
contents of accumulator
register & place sum
back into
accumulator.
Store C Copy the contents of
the accumulator into
location C.
Zero Opcode [no Source/Destination] Push Locations of II Not possible
Addre operands are defined
ss implicitly.
The operands are
stored in
a pushdown stack.

• Access to data in the registers is much faster than to data stored in memory-locations.
• Let Ri represent a generate. The instructions: Load A,Ri
Store Ri,A
Add A,Ri
are generalizations of the Load, Store and Add Instructions for the single-accumulator case, in
which register Ri performs the function of the accumulator.
In processors, where arithmetic operations as allowed only on operands that are in register task
• C<-[A]+[B] can be performed y the instruction sequence:
Move A,Ri
Move B,RJ
Add Ri,Rj
Move Rj,C
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Program Explanation
• Consider the program for adding the content of A & B
• Separate Add instruction is used to add each number to the contents of registers .
• After all the content of A & B are transferred to register C.

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BRANCHING

Program Explanation
• Consider the program for adding a list of n numbers (Figure 2.9).
• The Address of the memory-locations containing then numbers are symbolically given as
NUMl, NUM2 NUMn.
• Separate Add instruction is used to add each number to the contents of register RO.
• After all the numbers have been added, the result is placed in memory-location SUM.

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CONDITIONL CODES

• The processor keeps track of information about the results of various operations. This is
accomplished by recording the required I nformation in individual bits, called Condition Code
Flags.
• These flags are grouped together in a special processor-register called the condition code register
(or statue register).
• Four C ommonly used flags are:
1) N (negative) set to 1 if the result is negative, otherwise cleared to 0.
2) Z (zero) set to 1 if the re ult is 0; otherwise, cleared to 0
3) V (overflow) set to 1 if arithmetic overflow occurs; otherwise, cleared to 0.
4) C (carry) set to 1 if a carry-out results from the op ration; otherwise cleared to 0.
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8. ADDRESSING MODES
1. Implementation of variable and constant
2. Indirection and pointers
3. Indexing and Arrays
4. Base with index mode
5. Relative mode
6. Additional addressing mode

IMPLEMENTATION OF VARIABLE AND CONSTANTS

• Variable is represented by allocating a memory-location to hold its value.
• Thus, the value can be changed as needed using appropriate instructions.
• There are 2 accessing modes to access the variables:
1) Register Mode
2) Absolute Mode
Register Mode
• The operand is the content of a register.
• The name (or address) of the register i given in the instr uction.
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• Registers are used s temporary storage locations where the da a in a register are accessed.
• For example, the instruction
Move R , R2 ;Copy content of register Rl into register R2.
Absolute (Direct) Mode
• The operand is in a memory-location.
• The address of memory-location is given explicitly in the instruction.
• The absolute mode can represent global variables in the program.
• For example, the instruction
Move LOC, R2 ;Copy content of memo y-location LOC into register R2.
Immediate Mode
• The operand is given explicitly in the instruction.
• For example, the instruction
Move #200, RO ; Place the value 200 in register R
• Clearly, the immediate mode is only used to specify the value of a source-operand.

• To execute the Add instruction in fig 2.11 (a), the processor uses the value which is in register Rl,
as the EA of the operand.
• It requests a read operation from the memory to read the contents of location B. The value read is the
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desired operand, which the processor adds to the contents of register RO.
• Indirect addressing through a memory-location is also possible as shown in fig 2.ll(b). In this
case, the processor first reads the contents of memory-location A, then requests a second read operation
using the value Bas an address to obtain the operand.

Program Explanation
• In above program, Register R2 is used as a pointer to the numbers in the list, and the operands
are accessed indirectly through R2.
• he initialization-section of the program loads the counter-value n from memory-location N into Rl
and uses the immediate address ng-mode to place the address value NUMl, which is the address of
the first number in the list, into R2. Then it clears RO to 0.
• The first two instructions in the loop implement the unspecified instruction block starting at LOOP.
The first time through the l oop, the instruction Add (R2), RO fetches the operand at location
NUMl and adds it to RO.
• The second Add instruction adds 4 to the contents of the pointer R2, so that it will contain the address
value NUM2 when the above instruction is executed in the second pass through the loop

INDEXING AND ARRAYS

• A different kind of flexibility for accessing operands is useful in dealing with lists and arrays.
Index mode
• The operation is indicated as X(Ri)
where X=the constant value which defines an offset(also called a displacement).
Ri=the name of the index register which contains address of a new location.
• The effective-address of the operand is given by EA=X+[Ri]
• The contents of the index-register are not changed in the process of generating the
effective- address.
• The constant X may be given either
--+ as an explicit number or
--+ as a symbolic-name representing a numerical value.

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• Fig(a) illustrates two ways of using the Index mode. In fig(a), the index register, R1, contains the
address of a memory-location, and the value X defines an offset(also called a displacement) from this
address to the location where the operand is found.
• To find EA of operand: Eg:
Add 20(R1), R2
EA=>1000+20=1020
• An alternative use is illustrated in fig(b). Here, the constant X corresponds to a memory address,
and the contents of the index register define the offset to the operand. In either case, the effective-
address is the sum of two values; one is given explicitly in the instruction, and the other is stored in
a register.
Example

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sters which can be denoted as

y be used to contain th offset X.
• The second register is usually called the base register.
• The effectively -address of the operand is given by EA=[Ri]+[Rj]
• This for of indexed addressing provides more flexibility in acessing operands because
both components of the effective-address scan be changed.
Base with Index & Offset Mode
• Another version of the Index mode uses 2 registers plus a constant, which can be denoted
as X(Ri, Rj)
• The effective-address of the operand is given by EA=X+[Ri]+[Rj]
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• This added flexibility is useful in accessing multiple components inside each item in a record,
where the beginning of an item is specified by the (Ri, Rj) part of the addressing-mode. In other
words, this mode implements a 3-dimensional array.

RELATIVE MODE
• This is similar to index-mode with one difference:
The effective-address is determined using the PC in place of the general purposes register Ri.
• The operation is indicated as X(PC).
• X(PC) denotes an effective-address of the operand which is X locations above or below the cu
rent contents of PC.
• Since the addressed-location is identified "relative" to the PC, the name Relative mode is
associated with this type of addressing
• This mode is used commonly in conditional branch instructions.
• An instruction such as
Branch > 0 LOOP ; Causes program execution o go to the branch target location
identified by name LOOP if branch condition is satisfied.

ADDITIONAL ADDRESSING MODES

1) Auto Increment Mode

►
Effective address of operand is contents of a register specified in the instruction (Fig: 2.16).
► After accessing the operand, t h e contents of this register are automatically incremented
to point to the next item in a list.
Implicitly, the increment amount is 1.
► This mode is denoted as
(Ri)+ ; where Ri=pointer-register.
2) Auto Decrement Mode
► The contents of a register specified in the in instruction are first automatically
decremented and are then use as the effective address of the operand.
► This mode is denoted as
-(Ri) ; where Ri=pointer-register.
► These 2 modes can be used together to implement an important data structure called a stack.

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