UNIT-3

Addressing Modes
&
Instruction Set
Of 8086
UNIVERSITY OF GONDAR
INSTITUTE OF TECHNOLOGY
COMPILED BY: TIGABU Y.
@2021 1
Introduction
Program
A set of instructions written to solve a problem.

Instruction
Directions which a microprocessor
follows to execute a task or part of a
task.

Computer language

High Level
Low Level

Machine Language
Assembly Language
 Binary bits  English Alphabets
 ‘Mnemonics’
 Assembler Mnemonics 
Machine Language

2
Introduction... Cont’d
Program is a set of instructions written to solve a problem. Instructions are the
directions which a microprocessor follows to execute a task or part of a task.
Broadly, computer language can be divided into two parts as high-level language
and low level language. Low level language are machine specific. Low level
language can be further divided into machine language and assembly language.

Machine language is the only language which a machine can understand.

Instructions in this language are written in binary bits as a specific bit pattern. The
computer interprets this bit pattern as an instruction to perform a particular task.
The entire program is a sequence of binary numbers. This is a machine-friendly
language but not user friendly. Debugging is another problem associated with
machine language.

To overcome these problems, programmers develop another way in which

instructions are written in English alphabets. This new language is known as
Assembly language. The instructions in this language are termed mnemonics. As
microprocessor can only understand the machine language so mnemonics are
translated into machine language either manually or by a program known as
assembler.

Efficient software development for the microprocessor requires a complete

familiarity with the instruction set, their format and addressing modes. Here in
this chapter, we will focus on the addressing modes and instructions formats of
microprocessor 8086.
3
ADDRESSING
MODES OF
8086
4
Addressing Modes in 8086
• The different ways that a processor can access
data are referred to as addressing modes.

• The addressing mode describes the types of

operands and the way they are accessed for
executing an instruction.

• The addressing modes of any processor can be

broadly classified as:
1. Data Addressing Modes
2. Program Memory Addressing Modes
3. Stack Memory Addressing Modes 5
Addressing Modes
• control transfer instructions
 These branch instructions are instructions
which are responsible for changing the
regular flow of the instruction execution and
shifting the control to some other location.
o For example INT, CALL, RET & JMP
instructions fall under this category.
• The addressing modes for Sequential control
flow instructions are explained are listed in
the next slide.
6
Data Addressing Modes
• Every Instruction of a program has to operate
on a data/operand.
• Different ways in which source operand is
denoted in an instruction are known as
addressing modes.
• Addressing mode is the way in which the
operand is specified.
• The different ways in which a processor can
access data are called addressing modes.
• Addressing mode indicates a way of locating
data or operands. 7
Various Data Addressing Modes
Group I : Addressing modes for
1. Immediate Addressing
accessing register and immediate data
2. Register Addressing

3. Direct Addressing

4. Register Indirect Addressing

5. Based (with displacement) Addressing

6. Indexed (with displacement) Addressing Group II : Addressing modes for

accessing memory data
7. Based Index Addressing

8. Based Indexed with displacement

9. String Addressing

10. Direct I/O port Addressing

Group III : Addressing modes for
11. Indirect I/O port Addressing accessing I/O ports

12. Implied Addressing Group V : Implied Addressing mode

8
1. IMMEDIATE ADDRESSING MODE
• In immediate addressing mode, an 8-bit or 16-bit
immediate data is directly specified as part of the
instruction.

• Example 1:
MOV DL, 08H

• The 8-bit data (08H) given in the instruction is

moved to DL
(DL)  08H

• Example 2:
MOV AX, 0A9FH

• The 16-bit data (0A9FH) given in the instruction is

moved to AX register. AH AL
(AX)  0A9FH AX 0A 9F
 In this addressing mode, the segment register can’t be 9
2.REGISTER ADDRESSING MODE
• The instruction will specify the name of the
register which holds the data to be operated by
the instruction.
• the data is stored in a register and it is referred using
the particular register.

• Source & Destination Operands: Registers

• Example 1: 8 bit register as source of operand

MOV CL, DH
• The content of 8-bit register DH is moved to
another 8-bit register CL: (CL)  (DH)
• Example 2: 16 bit register as source of operand
MOV AX, BX 10
Memory Access
• To access memory we use the four registers: BX, SI, DI and
BP.

• Combining these registers inside [ ] symbols, we can get

different memory locations ( Effective Address, EA)

• Supported Combinations (supported addressing modes):

[BX + SI] [BX + SI + d8]

[SI]
[BX + DI] [BX + DI + d8]
[DI]
[BP + SI] [BP + SI + d8]
d16 (variable offset only)
[BP + DI] [BP + DI + d8]
[BX]

[SI + d8] [BX + SI + d16] [SI + d16]

By default DS segment
[DI + d8] [BX + DI + d16] [DI + d16] register is used for all modes
[BP + d8] [BP + SI + d16] [BP + d16]
[BX + d8] [BP + DI + d16] [BX + d16] except those with BP register,
for these SS segment register
BX SI is used.
+ disp
BP DI
11
Memory Access: Valid Combinations
• You can form all valid combinations by
taking only one item from each column or
skipping the column by not taking anything
from it.
• BX and BP never go
together, SI and DI
also don’t go together.

[BX + SI] [BX + SI + d8]

[SI]
[BX + DI] [BX + DI + d8]
[DI]
[BP + SI] [BP + SI + d8]
d16 (variable offset only)
[BP + DI]
[BX]
[BP + DI + d8] • Displacement(disp)
can be inside or
outside of [] symbols.
[SI + d8] [BX + SI + d16] [SI + d16]
[DI + d8] [BX + DI + d16] [DI + d16] • Valid Combinations
[BP + d8] [BP + SI + d16] [BP + d16]
[BX + d8] [BP + DI + d16] [BX + d16] represent Effective
Addresses
𝑂𝑓𝑓𝑠𝑒𝑡 𝐴𝑑𝑑𝑟𝑒𝑠𝑠≤ 𝐸𝑓𝑓𝑒𝑐𝑡𝑖𝑣𝑒 𝐴𝑑𝑑𝑟𝑒𝑠𝑠< 𝑃h𝑦𝑠𝑖𝑐𝑎𝑙𝑙 𝐴𝑑𝑑𝑟𝑒𝑠𝑠 12
3. DIRECT ADDRESSING MODE
• Here, the Effective address of the memory location at which the
data operand is stored is specified in the instruction.
• a 16-bit memory address (offset) directly specified in the instruction as a
part of it.
Example:
MOV BX, [1234H]
 Here if DS=2000H and offset (Effective Address) =1234H
Physical Address=DS*10H+Offset Address
=2000H*10H+1234H
=21234H
 This instruction moves the contents of 21234H & 21235H
memory location into BL and BH register respectively.

• The square brackets around the 1234H denotes the contents of

the memory location. When executed, this instruction will copy
the contents of the memory locations; 1234 H & 1235H, in the
data segment into BX register.

• This addressing mode is called direct because the displacement

of the operand from the segment base is specified directly in
the instruction.
13
4. REGISTER INDIRECT ADDRESSING MODE
• In Register indirect addressing, name of the register which holds
the Effective Address (EA) will be specified in the instruction.
• the address of the memory location which contains data or operands is
determined in an indirect way, using the offset registers.

• Registers used to hold Effective Address of an operand are any of

the following registers: BX, SI, DI .
• The segment is Data segment by default.

Note : Register/ memory

• Example: enclosed in brackets refer
MOV AX, [BX] to content of register/
memory
Operations:

EA = (BX)
BA = (DS) x 10 H where:
MA = BA + EA DS = Data Segment
EA = Effective Address
(AX)  (MA) or,
BA = Base Address
(AL)  (MA) MA = (Physical) Memory Address
(AH)  (MA +1)
14
5.Indexed Addressing Mode
• SI or DI register is used to hold an index value for memory data
and a signed 8-bit or unsigned 16-bit displacement will be
specified in the instruction.

• Displacement is added to the index value in SI or DI register to

obtain the Effective Address (EA).

• In case of 8-bit displacement, it is sign extended to 16-bit

before adding to the base value.

• Example: MOV CX, [SI + A2H] ; indexing addressing mode with displacement

Operations:

FFA2H  A2H (Sign extended)

EA = (SI) + FFA2H
BA = (DS) x 10 H
MA = BA + EA

(CX)  (MA) or,

(CL)  (MA)
(CH)  (MA + 1)
15
6. Based Addressing Mode
• In Based Addressing, BX or BP is used to hold the base value for effective
address and a signed 8-bit or unsigned 16-bit displacement will be specified
in the instruction.

• In case of 8-bit displacement, it is sign extended to 16-bit before adding to

the base value.

• When BX holds the base value of Effective Address ( EA ), 20-bit physical

address is calculated from BX and DS.

• When BP holds the base value of EA, BP and SS is used.

• Example: MOV AX, [BX + 08H]; Based Addressing Mode with displacement

Operations:

0008H  08H (Sign extended)

EA = (BX) + 0008H
BA = (DS) x 10 H
MA = BA + EA

(AX)  (MA) or,

(AL)  (MA)
(AH)  (MA + 1)
16
7.BASED & INDEX ADDRESSING MODES
• In Based Index Addressing, the effective address is computed
from the sum of a base register (BX or BP), an index register
(SI or DI).

• Example: MOV DX, [BX + SI ] or MOV DX, [BX][SI]

Operations:

EA = (BX) + (SI)
BA = (DS) x 10 H
MA = BA + EA

(DX)  (MA) or,

(DL)  (MA)
(DH)  (MA + 1)

17
8.BASED & INDEX with Displacement ADDRESSING
MODES
• In Based Index with displacement Addressing, the effective
address is computed from the sum of a base register (BX or
BP), an index register (SI or DI) and a displacement.

• Example 1: MOV DX, [BX + SI + 0AH]

Operations:

000AH  0AH (Sign extended)

EA = (BX) + (SI) + 000AH

BA = (DS) x 10 H
MA = BA + EA

(DX)  (MA) or,

(DL)  (MA)
(DH)  (MA + 1)

• Example 2: MOV AX, [BX + SI + 06H]

AH  [BX + SI + 07H] : AL  [BX + SI + 06H]

18
9. Strings Addressing Mode
• Employed in string operations to operate on string data.

• The effective address (EA) of source data is stored in SI register and the OA of
destination is stored in DI register.

• Segment register for calculating base address of source data is DS and that of the
destination data is ES.

• Example: MOVS BYTE ; in another way [ES:DI]  [DS:SI]

Operations:

Calculation of source memory location:

EAD = (SI) BAD = (DS) x 10 H MAD = BAD + EAD

Calculation of destination memory location:

Note : Effective address of EAE = (DI) BAE = (ES) x 10 H MAE = BAE + EAE
the Data Segment

Note : Effective address of (MAE)  (MAD)

the Extra segment

If DF = 1, then (SI)  (SI) – 1 and (DI)  (DI) – 1

If DF = 0, then (SI)  (SI) +1 and (DI)  (DI) + 1

19
9. Strings Addressing Mode
• Example: MOVS BYTE ; in another way [ES:DI]  [DS:SI]

Operations:

Calculation of source memory location:

EAD = (SI) BAD = (DS) x 10 H MAD = BAD + EAD

Calculation of destination memory location:

Note : Effective address of
EAE = (DI) BAE = (ES) x 10 H MAE = BAE + EAE
the Data Segment

Note : Effective address of (MAE)  (MAD)

the Extra segment
If DF = 1, then (SI)  (SI) – 1 and (DI)  (DI) – 1
If DF = 0, then (SI)  (SI) +1 and (DI)  (DI) + 1

20
10. Direct I/O Port Addressing
• These addressing modes are used to access data from
standard I/O mapped devices or ports.

• Standard I/O devices uses port addressing modes

• In direct port addressing mode, an 8-bit port address is

directly specified in the instruction.

• Example: IN AL, [09H]

Operations:
PORTaddr = 09H
(AL)  (PORT)

Content of port with address 09H is

moved to AL register

21
11. Indirect I/O Port Addressing
• In indirect port addressing mode, the instruction will
specify the name of the register which holds the port
address. In 8086, the 16-bit port address is stored in
the DX register.
• Example: OUT [DX], AX

Operations:
PORTaddr = (DX)
(PORT)  (AX)

Content of AX is moved to port whose address

is specified by DX register.

22
12. Implied Addressing Mode
• Instructions using this mode have no operands.
The instruction itself will specify the data to be
operated by the instruction.

• Example 1: STC

 Sets the Carry Flag to one.

• Example 2: CLC

 This clears the carry flag to zero.

• Example 3: CLD

 This clears the Direction flag to zero.

23
Exercise

24
Addressing Modes (cont’d)
• Program Memory Addressing Modes
o According to the flow of instruction execution, the
instructions may be categorized as
1. Sequential Control Flow Instructions
2. Control Transfer (BRANCH) Instructions
o Sequential control flow instructions are the instructions
which after execution, transfer control to the next
instruction appearing immediately after it (in the sequence)
in the program.
 For example the arithmetic, logic, data transfer and processor
control instructions are Sequential control flow instructions.
o The control transfer instructions on the other hand transfer
control to some predefined address or the address
somehow specified in the instruction, after their execution.
 For example INT, CALL, RET & JMP instructions fall under this
category. 25
Addressing Modes in 8086
• Program Memory Addressing Modes
 This addressing mode is required for instructions
that cause a branch in the program
 These instructions are: JMP & CALL
 If the branch is within the segment, it is called as an
Intra-Segment Branch or a Near Branch.
o The destination location is within the current segment
 If the branch is in a different segment, it’s called as an
Inter-segment Branch or a Far Branch.
o The destination location is from a different segment (it
can be any memory location within the entire memory
locations)
 In both instructions the name of a memory address, called a
label is specified ins the instruction instead of address.
26
Addressing Modes in 8086
• Program Memory Addressing Modes
• For the control transfer instructions, the addressing modes depend upon
whether the destination location is within the same segment or in a different
one. It also depends upon the method of passing the destination address to the
processor
• Inter-Segment: Address to which the control is to be transferred is in a different
segment

• Intra-Segment: Address to which the control is to be transferred lies in the same

27
segment.
Addressing Modes in 8086
• Program Memory Addressing Modes
 Intra-Segment Direct Addressing Mode
o Address where to transfer program control is
specified directly in the instruction as an 8-bt (16-
bit) displacement.
o The effective address is thus calculated by adding
this displacement to the current value of IP.
o As it’s intra-segment, only IP changes, CS doesn’t
change.
o If the displacement is 8-bit it’s called as a short
branch.
o This addressing mode is also called as Relative
Addressing Mode.
28
Addressing Modes in 8086
• Program Memory Addressing Modes
 Intra-Segment Direct Addressing Mode

NB: PREV & Next are labels 29

Addressing Modes in 8086
• Program Memory Addressing Modes
 Intra-Segment Indirect Addressing Mode
o Address where to transfer program control is
specified indirectly in the instruction through a
register or a memory location ( in DS only)
o The value in the IP is replaced with the new
value.
o As it is intra-segment, only IP changes, CS
doesn’t change.
o Eg: JMP WORD PTR [BX] ; IP {DS:[BX], DS:[BX + 1]}
Prefixes used in order to tell the assembler/compiler about data type.

30
Addressing Modes in 8086
• Program Memory Addressing Modes
 Intra-Segment Indirect Addressing Mode

31
Addressing Modes in 8086
• Program Memory Addressing Modes
 Inter-Segment Direct Addressing Mode
o The new branch location is specified directly in
the instruction
o Both CS and IP get new values, as this is an
inter-segment branch.

32
Addressing Modes in 8086
• Program Memory Addressing Modes
 Inter-Segment Indirect Addressing Mode
o The new branch location is specified indirectly in
the instruction through a register or a memory
location ( in DS only)
o Both IP and CS get new values, as this is an inter-
segment branch
o Eg: JMP DWORD PTR [BX]; IP {DS:[BX], DS:[BX + 1]}
; CS {DS:[BX +2], DS:[BX + 3]}

33
Addressing Modes in 8086
• Stack Memory Addressing Modes
 The STACK is a portion of read/write memory set
aside by the user for the purpose of storing
information temporarily.
 When the information is written on the stack, the
operation is called PUSH.
 When the information is read from stack, the
operation is called POP.
The Microprocessor stores the information,
much like stacking plates. If it is desired to take
out the first stacked plate, we will have to
remove all plates above the first plate in the
reverse order
34
Addressing Modes in 8086
• Stack Memory Addressing Modes
 PUSH POP Operations…

 The Microprocessor stores the information,

much like stacking plates. If it is desired to
take out the first stacked plate, we will have
to remove all plates above the first plate in
the reverse order.
 This means that, the first information pushed
on to the stack is the last information popped
off from the stack.
o This type of operation is known as first in,
last out (FILO) or last in first out (LIFO)
35
Addressing Modes in 8086
• Stack Memory Addressing Modes
 This STACK is implemented with the help of special
memory pointer register, called stack pointer.
 During PUSH and POP operation, stack pointer
register gives the address of memory where the
information is to be stored or to be read.
 The memory location currently pointed by stack
pointer is called top of stack.
o Stack Pointer always points to the top of stack.

36
Addressing Modes in 8086
• Stack Memory Addressing Modes
 Function of PUSH and POP operations…
o Temporarily stores the contents of 16-bit register
or memory location or program status word, and
retrieves when required.
o When the programmer realizes the shortage of the
registers, he stores the present contents of the
registers in the stack with the help of PUSH
instruction and then uses these registers for other
functions.
o After completion of other function, programmer
loads the previous contents of the register from
the stack with the help of POP Instruction. 37
Addressing Modes in 8086
• Stack Memory Addressing Modes
 PUSH Operation…
o The PUSH instruction decrements stack pointer by
two and copies a word from some source to the
location in the stack where the stack pointer
points. ( here the source must be a word = 16-bit)
o The source of the word can be a general purpose
register, a segment register, or memory.
o The next slide shows the map of the stack before
and after execution of PUSH AX and PUSH CX
Instructions.

38
Addressing Modes in 8086
• Stack Memory Addressing Modes
 PUSH Operation…
o Higher order byte of the source operand stored @ SP-1
o Lower order byte of the source operand stored @ SP-2
Where SP is stack Pointer, and lets assume stack was empty

39
Addressing Modes in 8086
• Stack Memory Addressing Modes
 POP Operation…
o The POP instruction copies a word from some the
stack location pointed to by the stack pointer (SP)
to the destination.
o The destination can be a general purpose register,
a segment register, or memory.
o After the word is copied to the specified
destination, the stack pointer is automatically
incremented by 2.
o The next slide shows the map of the stack before
and after execution of POPH DX and POP BX
Instructions. 40
Addressing Modes in 8086
• Stack Memory Addressing Modes
 POP Operation…
o The byte @ SP is transferred to lower order byte position.
o Then, the byte @ SP+1 will be transferred to higher order
byte position. Then again SP will be incremented again.

(a) Before execution (a) After execution of POP BX and POP DX

41
Addressing Modes in 8086
• Types of Stack Memory Addressing Modes
 Register Addressing Mode
o In this addressing mode the operands are
specified in registers ( Only 16-bit registers)
o Eg: PUSH BX ; Transfers BH at location pointed by SP-1
; and BL at Locations pointed by SP-2 in
; the stack segment.
;then, SP SP-2
 Register Indirect Addressing Mode
o In this addressing mode the addresses of the
operand is specified in the registers
o Eg: PUSH [BX] ; This instruction will transfer a word
form ; location pointed by BX and BX+1 in
Data Segment ; to SP -1 and SP – 2 in Stack
Segment respectively. 42
Addressing Modes in 8086
• Stack Memory Addressing Modes
 Flag Addressing Mode
o Here the contents of Flag Register are transferred
to and from the Stack.
o Eg: PUSHF ; This instruction will transfer higher byte
; of Flag Register to SP-1 and lower byte to
; SP-2 in the Stack Segment
 Segment Register Addressing Mode
o Here the Segment Registers (except CS) are
transferred to and from the Stack.
o Eg: PUSH DS ; This instruction will transfer higher byte
; of DS Register to SP-1 and lower byte to
; SP-2 in the Stack Segment

43
INSTRUCTIO
N SET of
8086 44
Instruction set basics

• Microprocessor executes instructions given by user.

• Instructions should be in a language known to
microprocessor
• Microprocessor understands the language of 0’s and 1’s
only
o This language is called Machine Language.

45
Instruction set basics

• Microprocessor understands only Machine language

o Cannot understand Assembly Language
• Assembler:- it converts the instruction into sequence of
binary bits, so that this bits can be read by the processor.
• Mnemonics:- these are the symbolic codes for either
instructions or commands to perform a particular
function.
o E.g. MOV, ADD, SUB etc.

46
Instruction set basics
• Instruction:- An instruction is a binary pattern designed
inside a microprocessor to perform a specific function.

• The entire group of instructions that a microprocessor

supports is called Instruction Set.

• 8086 has more than 20,000 instructions.

47
Instruction set basics
• A program consists of a number of CPU instructions.
• Each instruction consist of an
o instruction code (Opcode) and
o one or more operands (data which the instruction manipulates).
• Opcode:- It stands for operational code. It specifies the type of
operation to be performed by CPU. It is the first field in the
machine language instruction format.
o E.g. 08 is the opcode for instruction “MOV X,Y”.
• Operand:- We can also say it as data on which operation should act.
o operands may be register values or memory values.
o The CPU executes the instructions using information present in this field.
 It may be 8-bit data or 16-bit data.
• The instruction code specifies to the CPU what to do, where the data
is located and where the output data will be put. 48
Types of instruction set of 8086
microprocessor
1. Data Transfer/Copy Instructions
2. Arithmetic Instructions
3. Bit Manipulation Instructions
I. Logical Instructions
II. Shift & Rotate Instructions
4. Control Transfer (Branch) Instructions
5. Iteration Control (Loop) Instructions
6. Flag Manipulation & Machine (Processor) Control
Instructions
I. Flag Manipulation Instructions
II. Processor Control Instructions
7. String Instructions
8. Interrupt Instructions 49
(1). Data copy/transfer instructions.
 Instructions that are used to copy/transfer data/
address in to registers, memory locations and I/O
ports.
 Generally involve two operands: Source operand
and Destination operand of the same size.
 Source: Register or a memory location or an
immediate data
 Destination : Register or a memory location.
 The size should be a either a byte or a word.
 A 8-bit data can only be moved to 8-bit register/
memory and a 16-bit data can be moved to 16-bit
register/ memory.
50
(1). Data copy/transfer instructions.
Mnemonics:
 MOV, PUSH, POP, XCHG, IN, OUT, XLAT, LEA, LDS,
LES, LAHE, SAHE, PUSHF, POPF
Instruction to transfer word:
 MOV, PUSH, POP, XCHG, XLAT,

Instructions for input and output port transfer:

 IN, OUT
Instructions to transfer the Address
 LEA, LDS, LES
Instructions to transfer flag registers:
 LAHF, SAHF, PUSHF, POPF
51
(1). Data copy/transfer instructions.
(1). MOV Destination, Source
 There will be transfer of data from source to destination.
Used to copy the byte or word from the provided source to
the provided destination.
 Source can be register, memory location or immediate
data.
 Destination can be register or memory operand.
 Both Source and Destination cannot be memory location or
segment registers at the same time.
 In other words, direct loading of the segment registers with immediate
data is not permitted. To load the segment registers with immediate
data, one will have to load any general-purpose register with the data
and then it will have to be moved to that particular segment register.
Example: (MOV DS, 5000H; Not permitted (invalid)) 52
(1). Data copy/transfer instructions.
(1). MOV Destination, Source

53
(1). Data copy/transfer instructions.
(1). MOV Destination, Source

54
BEFORE AFTER
EXECUTION EXECUTION
AX 2000H MOV BX,AX BX 2000H

BEFORE AFTER
EXECUTION EXECUTION
A AL M A AL
H
MOV CL,M H
B BL
H B BL
40 40
C CL H
H
C CL 40
D DL
H H 55
Stack Organization
Holds data temporarily and stores return addresses used
by procedures
It is Last IN First Out (LIFO) buffer
 Describes the way data are stored and removed
from the stack
 Data are placed on the stack with a PUSH
instruction; removed with a POP instruction.
• SS:SP points to top of the stack.
• Last filled location in the stack.
• Expands down.
• Fills from higher to lower addresses

56
Stack Pointer
It is a 16-bit register, contains the address of the
data item currently on top of the stack.
Stack operation includes pushing (providing)
data on to the stack and popping (taking) data
from the stack.
Pushing operation decrements stack pointer
and Popping operation increments stack
pointer. i.e. there is a last in first out (LIFO)
operation.
57
(2). Push Source
Source can be register, segment register or memory.
This instruction pushes the contents of specified source on
to the stack.
In this stack pointer is decremented by 2, i.e.,
o The higher byte data is pushed first into (SP-1).
o Then lower byte data is pushed into (SP-2).
o Then, SP SP-2

58
(2). Push Source

59
(2). Push Source

60
(2). Push Source
Let
And
DS = 1122 H
assume
ES = 3344 H
the stack

Note the stack fo the following two consecutive operations

Push DS Push ES

61
INITIAL POSITION

(1) STACK
POINTER
DECREMENTS SP & STORES HIGHER
BYTE

(2) STACK POINTER

HIGHER BYTE

DECREMENTS SP & STORES LOWER

BYTE
(3) STACK
POINTER LOWER BYTE
HIGHER BYTE

62
BEFORE EXECUTION
SP 2002H
2000H
BH BL
2001H
CH 10 CL 50
DH DL
2002H

PUSH CX
AFTER EXECUTION
2000H 50
SP 2000H
BH BL
2001H 10
CH 10 CL 50

DH DL 2002H

63
(3) POP Destination
Destination can be register, segment register or memory.
This instruction pops (takes) the contents of specified
destination.
o In this stack pointer is incremented by 2, this
means
 The lower byte data (the value @ SP) is popped first.
 Then higher byte data (the value @ SP+1) is popped
next.
 Then, SP SP+2

64
(3) POP Destination

65
(3) POP Destination

66
(3) POP Destination

Assume we have a
given stack

Note fthe stack for the operation:

POP CS
CS [SS : SP]
SP SP + 2

67
INITIAL POSITION AND READS LOWER
BYTE

(1) STACK POINTER LOWER BYTE

INCREMENTS SP & READS HIGHER

BYTE
LOWER BYTE
(2) STACK POINTER HIGHER BYTE

INCREMENTS SP

LOWER BYTE
HIGHER BYTE
(3) STACK POINTER

68
BEFORE EXECUTION

2000H 30
SP 2000H
2001H 50
BH BL
2002H

POP BX
AFTER EXECUTION
2000H 30
SP 2002H 2001H 50
BH 5 BL 30 2002H
0
69
(4). XCHG Destination, source;
This instruction exchanges contents of Source
with destination.
Source can be register or memory location.
Destination can be memory location or register
However, exchange of data contents of two
memory locations is not permitted.

70
(4). XCHG Destination, source;

71
BEFORE EXECUTION AFTER EXECUTION

AH 20 AL 40 AH 70 AL 80

BH 70 BL 80 BH 20 BL 40

XCHG AX,BX
72
(5)IN AL/AX, 8-bit/16-bit port address
Used to read a byte or word from the provided
port to the accumulator.
It reads data from the specified port address.
It copies data to accumulator from a port with 8-
bit or 16-bit address.
Direct Addressing modes Mode:
 In this mode, 8-bit address of the port is a part
of the instruction

73
(5)IN AL/AX, 8-bit/16-bit port address
Indirect Addressing modes Mode:
 In this addressing mode, the address of the port is
referred from DX register.
o DX is the only register allowed to carry port
address.
 Since DX is 16 bit register, the port address can be
any number between 0000H to FFFFH.
o It is possible to address up to 65,536 ports in this
mode.

74
(5)IN AL/AX, 8-bit/16-bit port address

75
BEFORE EXECUTION

PORT 10 AL
80H

IN AL,80H
AFTER EXECUTION

PORT 10 AL 10
80H
76
OUT 8-bit/16-bit port address, AL/AX
Used to send out a byte or word from the accumulator to the
provided port
It writes a byte from AL or word from AX to the specified
port address.
It copies contents of accumulator to the port with 8-bit or
16-bit address.
Direct Addressing Mode:
 In this addressing mode, 8-bit address of the port is a
part of the instruction.

77
OUT 8-bit/16-bit port address, AL/AX
Indirect Addressing modes Mode:
 In this addressing mode, the address of the port is
referred from DX register.
o DX is the only register allowed to carry port
address.
 Since DX is 16 bit register, the port address can be
any number between 0000H to FFFFH.
o It is possible to access up to ports in this mode.

78
OUT 8-bit/16-bit port address, AL/AX

79
BEFORE EXECUTION

PORT 10 AL 40
50H

OUT 50H,AL
AFTER EXECUTION

PORT 40 AL 40
50H
80
(7) XLAT
Also known as translate instruction.
Used to translate a byte in AL using a table in the
memory.
E.g. XLAT; Translate a byte in AL
 This instruction replaces a byte in AL register with a
byte from a lookup table in memory
 BX register stores the offset of the starting address of
the lookup table and AL register stores the byte
number from the lookup table.
 This instruction copies byte from address pointed by
[BX+AL] back into AL.
81
(7) XLAT
Also known as translate instruction.
Used to translate a byte in AL using a table in the
memory.
It is used to find out codes in case of code conversion.
 i.e. it translates code of the key pressed to
the corresponding 7-segment code.
After execution this instruction contents of AL register
always gets replaced.
E.g. XLAT;

82
8. LEA 16-bit register (dest.), address (source)

LEA Also known as Load Effective Address

(LEA).
Used to load the address of operand into the
provided register
LEA REG, Source
 This instruction determines the offset of the variable or
memory location named as ‘Source’ and load this
address in the specified 16-bit register.
E.g.

83
(9). LDS 16-bit register (source), address (dest.);
LDS Also known as Load Data Segment (LDS).
• Used to load DS register and other provided register
with words from memory.
• LDS REG, Mem
 This instruction loads new values into the specified register,
REG, and into the DS register from four successive memory
locations.
o This instruction copies words from two memory locations into
the register, REG, specified in the instruction.
o It then copies a word form the next two memory locations into
the DS register.
• E.g.

84
(10). LES 16-bit register (source), address (dest.);
LES Also known as Load Extra Segment (LES).
• Used to load ES register and other provided register
with words from memory.
• LES REG, Mem
 This instruction loads new values into the specified register,
REG, and into the ES register from four successive memory
locations.
o The word from the first two memory locations is copied into the
specified register, REG, specified in the instruction.
o It then copies a word from the next two memory location is
copied into ES register.
• E.g.

85
LEA, LES, LDS

These instructions load a segment register and

general purpose registers with an address
directly from memory
The general forms of these registers

86
(1) LDS BX,5000H;
(2) LES BX,5000H;

15 0 7 0
BX 20 10 10 5000H
20
5001H
30
DS/ES 40 30 5002H
40 5003H

87
(11). LAHF
• Load lower byte of flag register in AH
 This instruction loads the AH register from the
contents of lower byte of the flag register.
• This command is used to observe the status of the
all conditional flags of flag register.

(12). SAHF

• Copy AH register to lower byte of flag

register
 The contents of the AH register are copied
into the lower byte of the flag register.
88
PUSH & POP
(13). PUSHF:- This instruction decrements the
stack pointer by 2.
It copies contents of flag register to the memory
location pointed by stack pointer.

(14). POPF:- This instruction increments the stack

pointer by 2.
It copies contents of memory location pointed by
stack pointer to the flag register.

89
(2). Arithmetic Instructions
These instructions perform the
operations like:
 Addition,
 Subtraction,
 Increment,
 Decrement,
 Negation,
 Comparison,
 Multiplication,
 Division,
 BCD Arithmetic
 ASCII Arithmetic 90
(2). Arithmetic Instructions

(1). ADD destination, source;
This instruction adds the contents of source operand with the
contents of destination operand.
 The source may be immediate data, memory location or register.
 The destination may be memory location or register.
 However, both the source and destination operands cannot be memory
operands.
 That means memory to memory addition is not possible.
• Also the contents of the segment registers cannot be added using this
instruction
 The result is stored in destination operand.
 AX is the default destination register.
 Affected Flags: AF, CF, OF, PF, SF, ZF

 E.g. (1). ADD AX,2020H;

(2). ADD AX,BX;
91
(2). Arithmetic Instructions
(1). ADD destination, source;
ADD REG2/ MEM, REG1/MEM

ADD REG2, REG1 (REG2)  (REG1) + (REG2)

ADD REG2, MEM (REG2)  (REG2) + (MEM)
ADD MEM, REG1 (MEM)  (MEM)+(REG1)

ADD REG/MEM, DATA

ADD REG, DATA (REG)  (REG)+ DATA

ADD MEM, DATA (MEM)  (MEM)+DATA
ADD A, DATA

ADD AL, DATA8 (AL)  (AL) + DATA8

ADD AX, DATA16 (AX)  (AX) +DATA16
92
BEFORE EXECUTION AFTER EXECUTION

AH 30 AL 30
AH 10 AL 10 ADD AX,2020H

1010
+2020
3030

BEFORE EXECUTION AFTER EXECUTION

AH 10 AL 10 AH 30 AL 30
ADD AX,BX
BH 20 BL 20 BH 20 BL 20

93
ADC destination, source
 This instruction adds the contents of source operand with the
contents of destination operand and the carry flag bit (which may
be set as a result of the previous calculations) .

 The source may be immediate data, memory location or

register.

 The destination may be memory location or register.

 The result is stored in destination operand.

 AX is the default destination register.

 Affected Flags: AF, CF, OF, PF, SF, ZF

94
ADC destination, source

95
ADD destination, source
ADC destination, source

96
ADD destination, source
ADC destination, source

97
(3) INC source
 This instruction increases the contents of source operand by 1.
 The source may be memory location or register.
 The source can not be immediate data.
 The result is stored in the same place.
 Flags Affected: AF, OF, PF, SF, ZF
 Note: CF is not affected
 If contents of 8-bit register are FFH and 16-bit register are
FFFFH, after INC instruction contents of registers will be zero
without affecting carry flag.

98
(3) INC source

99
BEFORE EXECUTION AFTER EXECUTION

AH 10 AL 11 INC AX AH 10 AL 12

BEFORE EXECUTION AFTER EXECUTION

5000H 1011 INC [5000H] 5000H 1012

100
4. DEC source
 This instruction decreases the contents of source operand
by 1.
 The source may be memory location or register.
 The source can not be immediate data.
 The result is stored in the same place.
 Flags Affected: AF, OF, PF, SF, ZF
 Note: CF is not affected
 If the contents of 8-bit register are 00H and 16-bit register
are 0000H, after DEC instruction contents of register will
be FFH and FFFFH respectively without affecting carry
flag.

101
4. DEC source

102
BEFORE EXECUTION AFTER EXECUTION

AH 10 AL 11 DEC AX AH 10 AL 10

BEFORE EXECUTION AFTER EXECUTION

5000H 1051 DEC [5000H] 5000H 1050

103
5. NEG source
This instruction replaces the number in a
destination with 2’s complement of that
number.
 This instruction can be implemented by
inverting each bit and adding 1(one) to it.
The source may be memory location or
register.
The source can not be immediate data.
The result is stored in the same place.
Flags Affected: AF, CF, OF, PF, SF, ZF

104
(6) SUB destination, source;
This instruction subtracts the contents of source
operand from contents of destination.
The source may be immediate data, memory
location or register.
The destination may be memory location or
register.
The result is stored in the destination place.
Flags Affected: AF, CF, OF, PF, SF, ZF

E.g. (1). SUB AX,1000H;

(2). SUB AX,BX; 105
(6) SUB destination, source;

106
BEFORE EXECUTION AFTER EXECUTION

AH 20 AL 00 SUB AX,1000H AH 10 AL 00

2000
-1000
=1000

BEFORE EXECUTION AFTER EXECUTION

AH 20 AL 00 AH 10 AL 00
BH 10 BL 00 SUB AX,BX
BH 10 BL 00
107
(7). SBB destination, source;
 Also known as Subtract with Borrow.
 This instruction subtracts the contents of the source
operand & the borrow flag (CF) which may reflect the
result of the previous calculations, from contents of
destination operand.
 Subtraction with borrow, here means subtracting 1
from the subtraction obtained by SUB, if carry
(borrow) flag is set.
 The source may be immediate data, memory location
or register.
 The destination may be memory location or register.
 The result is stored in the destination place.
 E.g. (1). SBB AX,1000H;
(2). SBB AX,BX;
108
(7). SBB destination, source;

109
BEFORE EXECUTION AFTER EXECUTION

B 1 SBB AX,1000H
AH 20 AL 20 AH 10 AL 1F
2020
- 1000
1020 -1 = 101F
BEFORE EXECUTION AFTER EXECUTION
B 1
AH 20 AL 20 AH 10 AL 1F
SBB AX,BX
BH 10 BL 10 BH 10 BL 10

110
(6) SUB destination, source;
(7). SBB destination, source;

111
(6) SUB destination, source;
(7). SBB destination, source;

112
(8). CMP destination, source
 This instruction compares the contents of source
operand with the contents of destination operands.
 For comparison, it subtracts the source operand from
the destination operand but does not store the result
anywhere.
 The source may be immediate data, memory
location or register.
 The destination may be memory location or
register.
 The source and destination both can’t be memory
location.

113
(8). CMP destination, source
 The flags are affected depending upon the result of the
subtraction:
 If both of the operands are equal, zero flag is set.
 If the source operand is greater than the destination
operand, carry flag is set or else, carry flag is reset.
 Then resulting carry & zero flag will be set or reset.

Example:

114
(8). CMP destination, source

115
(8). CMP destination, source

116
(8). CMP destination, source

117
D=S: CY=0,Z=1
BEFORE EXECUTION D>S:
CY=0,Z=0 AFTER EXECUTION
D<S: CY=1,Z=0
AH 10 AL 00
CMP AX,BX CY 0 Z 1
BH 10 BL 00

BEFORE EXECUTION AFTER EXECUTION

AH 10 AL 00
CMP AX,BX CY 0 Z 0
BH 00 BL 10

BEFORE EXECUTION AFTER EXECUTION

AH 10 AL 00
CMP AX,BX CY 1 Z 0
BH 20 BL 00

118
BCD Numbers
 Binary-Coded Decimal(BCD): is a class of binary encodings of decimals
numbers where each decimal digit is represented by a fixed number of
bits, usually four or eight.
 As most computers deal with data in 8-bit bytes, it’s possible to use
one of the following methods to encode a BCD number.
o Unpacked: Each numeral is encoded into one byte, with four
bits representing the numeral and the remaining bits having no
significance.
o Packed: Two numerals are encoded into a single byte, with one
numeral in the least significant nibble ( bits 0 through 3) and the
other numeral in the most significant nibble ( bits 4 through 7).

119 119
BCD Examples
 Binary-Coded Decimal(BCD)

 Examples: encoding the decimal number 91D.

 Using unpacked BCD

o Decimal 9 1
o Binary 0000 1001 0000 0001
 Using Packed BCD, the same number would fit into a single
byte.
o Decimal 9 1
o Binary 1001 0001
120 120
(9) BCD Arithmetic
 The 8086 provides two instructions to support BCD arithmetic.

 They correct result of BCD addition and a BCD subtraction

 DAA (Decimal Adjust after Addition)

It is used to make sure that the result of adding two BCD
numbers is adjusted to be a correct BCD number.
It only works on AL register.

 DAS (Decimal Adjust after Subtraction)

It is used to make sure that the result of subtracting two

BCD numbers is adjusted to be a correct BCD number.
It only works on AL register. 121
(9) BCD Arithmetic… cont’d
DAA Instruction works as follows

1. If the value of the low-order four bits (D3-

D0) in the AL register is greater than 9 or if
AF is set, the instruction adds 6 (06 = 0000
0110) to adjust the low-order four bits.
2. If the value of the high-order four bits (D7-
D4) in the AL register is greater than 9 or if
CF is set, the instruction adds 6 (60 = 0110
0000) to adjust the high-order four bits.
122 122
(9) BCD Arithmetic… cont’d
 DAA Instruction works as follows

The Instruction updates the AF, CF, PF, and ZF

The OF is undefined after DAA instruction.

123 123
(9) BCD Arithmetic… cont’d
 DAA Instruction works as follows

124 124
(9) BCD Arithmetic… cont’d
DAS Instruction works as follows

1. If the value of the low-order four bits (D3-

D0) in the AL register is greater than 9 or if
AF is set, the instruction subtracts 6 (06 =
0000 0110) to adjust the low-order four bits.
2. If the value of the high-order four bits (D7-
D4) in the AL register is greater than 9 or if
CF is set, the instruction subtracts 6 (60 =
0110 0000) to the adjust high-order four bits.
125 125
(9) BCD Arithmetic… cont’d
DAS Instruction works as follows

The Instruction updates the AF, CF, PF, and ZF

The OF is undefined after DAA instruction. 126

(9) BCD Arithmetic… cont’d
DAS Instruction works as follows

The Instruction updates the AF, CF, PF, and ZF

The OF is undefined after DAA instruction.

127 127
ASCII
AAA (ASCII Adjust after Addition):
The data entered from the terminal is in ASCII
format.
In ASCII, 0 – 9 are represented by 30H – 39H.
This instruction allows us to add the ASCII
codes.
This instruction does not have any operand.

Other ASCII Instructions:

AAS (ASCII Adjust after Subtraction)
AAM (ASCII Adjust after Multiplication)
128 128
AAD (ASCII Adjust Before Division)
(10) ASCII Arithmetic … cont’d
AAA (ASCII Adjust after Addition):

129 129
(10) ASCII Arithmetic … cont’d
AAA (ASCII Adjust after Addition):

130 130
(10) ASCII Arithmetic … cont’d
AAS (ASCII Adjust after Subtract):
The data entered from the terminal is in ASCII
format.
In ASCII, 0 – 9 are represented by 30H – 39H.
This instruction allows us to add the ASCII
codes.
This instruction does not have any operand.

131 131
(10) ASCII Arithmetic … cont’d
AAS (ASCII Adjust after Subtract):
The data entered from the terminal is in ASCII
format.
In ASCII, 0 – 9 are represented by 30H – 39H.
This instruction allows us to add the ASCII
codes.
This instruction does not have any operand.

132 132
(10) ASCII Arithmetic… cont’d
AAM (ASCII Adjust after
Multiplication):
The data entered from the terminal is in ASCII
format.
In ASCII, 0 – 9 are represented by 30H – 39H.
This instruction allows us to add the ASCII
codes.
This instruction does not have any operand.

133 133
(10) ASCII Arithmetic… cont’d
AAM (ASCII Adjust after
Multiplication):

134 134
(10) ASCII Arithmetic… cont’d
AAD (ASCII Adjust before Division):

135 135
(10) ASCII Arithmetic… cont’d
AAD (ASCII Adjust before Division):

136 136
Multiplication
This group of instructions consists of
following group of instructions
 MUL: Unsigned Multiplication
 IMUL: Signed Multiplication

137
MUL Instruction
 Syntax: MUL source
 This instruction multiplies an unsigned byte from source
and an unsigned byte in AL register, or an unsigned word
from source and an unsigned word in AX register.
 The source can be a register or a memory location.
 When the byte is multiplied by the contents of AL, the
result is stored in AX.
o The most significant byte is stored in AH and the least
significant byte is stored in AL.
 When a word is multiplied by the contents of AX, the most
significant word of the result is stored in DX and least
significant word of result is stored in AX.

E.g. (1). MUL BH // AX= AL*BH;

138
(2). MUL CX // DXAX=AX*CX;
MUL Instruction
Syntax: MUL Source; ; source can be Register or Memory

MUL REG/ MEM

MUL REG FOR BYTE : (AX)  (AL) X (REG8)

FOR WORD : (DX)(AX)  (AX) X (REG16)

MUL MEM FOR BYTE : (AX)  (AL) X (MEM8)

FOR WORD : (DX)(AX)  (AX) X (MEM16)

E.g.
(2). MUL BH // AX= AL*BH;
(3). MUL CX //DX AX=AX*CX;
(4). MUL WORD PTR [BX} //DXAX = AX times word in
//DS pointed by [BX]

Flags Affected: AF, PF, SF, and ZF 139

IMUL Instruction
 Syntax: IMUL source
 This instruction multiplies a signed byte from some source and a
signed byte in AL register, or a signed word from some source and
a signed word in AX register.
 The source can be a register or a memory location.
 When a signed byte is multiplied by AL, a signed result will be put
in AX.
o The most significant byte is stored in AH and the least
significant byte is stored in AL.
 When a signed word is multiplied by AX, the high-order word of
the signed result is stored in DX and the low-order word of the
signed result is stored in AX.
 To multiply a signed byte with a signed word, it is necessary to
move the byte into a word location and fill the upper byte of the
word with copies of the sign bit. This can be done using CBW
instruction.
140
IMUL Instruction
Syntax: IMUL source ; source can be register or memory

IMUL REG/ MEM

IMUL REG FOR BYTE : (AX)  (AL) X (REG8)

FOR WORD : (DX)(AX)  (AX) X (REG16)

FOR BYTE : (AX)  (AX) X (MEM8)

IMUL MEM FOR WORD : (DX)(AX)  (AX) X (MEM16)

E.g. (1). IMUL BH // AX= AL*BH; // (-3) * (-4) = 12.

(2). IMUL CX // DXAX=AX*CX;

• If the upper byte of a 16-bit result or the upper word of a 32-bit result contains only
copies of the sign bit ( all 0’s or all 1’s), then the CF and the OF will be both 0’s.
141
• The AF, PF, SF and ZF flags are all undefined after IMUL.
Division Instruction
This group of instructions consists of
following group of instructions
 DIV: Unsigned Division
 IDIV: Signed Division

142
DIV Instruction… cont’d
Syntax: DIV source
 This is used to divide an unsigned word by a byte
or to divide an unsinged double word by a word.
 CASE ONE:
o When dividing a word by a byte, the word
must be in AX register.
 After division, AL will contain an 8-bit quotient
and AH will contain an 8-bit remainder.
 If an attempt is made to divide by 0 or the quotient
is too large to fit in AL register (greater than FFH),
the 8086 will automatically execute a type 0
interrupt.

143
DIV Instruction… cont’d
Syntax: DIV source
 CASE TWO:
o When a double word is divided by a word, the
most significant word of the double word must be
in DX and the least-significant word of the double
word must be in AX.
 After division, AX will contain a 16-bit quotient
and DX will contain a 16-bit remainder.
 If an attempt is made to divide by 0 or the quotient
is too large to fit in AX register (greater than
FFFFH), the 8086 will automatically execute a type
0 interrupt.
o The source can be a register or a memory location.
144
DIV Instruction… cont’d
Syntax: DIV source
 To divide a byte by a byte
o It is necessary to put the dividend byte in
AL and fill AH with all 0’s.
 To divide a word by a word
o It is necessary to put the dividend word in
AX and fill DX with all 0’s

145
DIV Instruction… cont’d
Syntax: DIV source
 To divide a byte by a byte
o It is necessary to put the dividend byte in
AL and fill AH with all 0’s.
 To divide a word by a word
o It is necessary to put the dividend word in
AX and fill DX with all 0’s
 E.g.
MOV AX, 0203 // AX=0203
MOV BL, 04 // BL=04
DIV BL // AL=0203/04=50 (i.e. AL=50 & AH=03)
146
DIV Instruction… cont’d

147
IDIV Instruction

Syntax: IDIV source

 This is used to divide a signed word by a signed
byte, or to divide a singed double word by a signed
word.
 Rest all is similar to DIV instruction.
 E.g.
MOV AX, -0203 // AX=-0203
MOV BL, 04 // BL=04
IDIV BL // AL=-0203/04=-50 (i.e. AL=-50 & AH=03)

148
IDIV Instruction … cont’d

149
Multiplication and Division Examples

150
BEFORE EXECUTION

AH 00 AL 05
BH 00 BL 03
CH CL

MUL BX AX=lower 16 bit {000F}

DX=Higher 16 bit {0000}
AFTER EXECUTION 0005*0003 = 0000 000F

AH 00 AL 0F
BH BL
CH CL
DH 00 DL 00
151
BEFORE EXECUTION

AH 00 AL 0F

BH 00 BL 02
CH CL AX=Quotient {0007}
DX=Reminder {0001}

DIV BX 000F =7 1
AFTER EXECUTION 0002 2

AH 00 AL 07
BH BL
CH CL
DH 00 DL 01 152
153
154
155
Bit Manipulation Instructions
These instructions are used to perform operations where
data bits are involved.
 These instructions are used at the bit level.
 These instructions are grouped into:
 Logical Instructions
 Shift & Rotate Instructions
Logical Instructions
 Instructions to perform Logical operations
o NOT
o AND
o OR
o XOR
o TEST
156
Bit Manipulation Instructions
Shift and Rotate Instructions
 Instructions to perform Shift operations
o SHL… Shift Left
o SAL… Shift Arithmetic Left
o SHR… Shift Right
o SAR… Shift Arithmetic Right
 Instructions to perform Rotate operations
o ROL… Rotate Left
o ROR… Rotate Right
o RCL… Rotate Left through Carry flag
o RCR… Rotate Right through Carry flag
157
AND
Syntax: AND destination, source
 Used for adding each bit in a s source byte/word with the
corresponding bit in a destination byte/word.
 Stores result in the destination
 The source may be an immediate number, a register, or a
memory location
 The destination may be a register or a memory location
 The source and destination both can’t be memory
locations.
 AND operation with two inputs produces result logic 1 only
when both inputs are logic 1.
 The CF and OF are both 0 after AND, the PF, SF, and ZF
are affected, AF is undefined.

158
AND
AND A, DATA
AND AL, DATA8 (AL)  (AL) & DATA8

AND AX, DATA 16 (AX)  (AX) & DATA16

AND REG/ MEM, DATA

AND REG, DATA (REG)  (REG) & DATA

MOV MEM, DATA (REM)  (MEM) & DATA

AND REG2/MEM, REG1/MEM

AND REG1, REG2 (REG1)  (REG1) & (REG2)

AND REG1, MEM (REG1)  (REG1) & (MEM)

AND MEM, REG2 (REM)  (MEM) & (REG2)

159
AND

The AND operation clears bits of a binary number.

The task of clearing a bit in a binary number is called
masking.
Figure below shows masking using AND operations

160
OR
Syntax: OR destination, source
 Used to multiply each bit in a source byte/word with the
corresponding bit in a destination byte/word.
 Stores result in the destination
 The source may be an immediate number, a register, or a
memory location
 The destination may be a register or a memory location
 The source and destination both can’t be memory
locations.
 OR operation with two inputs produces result logic 0 only
when both inputs are logic 0.
 The CF and OF are both 0 after OR, the PF, SF, and ZF are
affected, AF is undefined.

161
OR
OR A, DATA

OR AL, DATA8 (AL)  (AL) | DATA8

OR AX, DATA 16 (AX)  (AX) | DATA16

OR REG2/MEM, REG1/MEM

OR REG2, REG1 (REG1)  (REG1) | (REG2)

(REG2)  (REG2) | (MEM)

OR REG2, MEM
(MEM)  (MEM) | (REG1)
OR MEM, REG1

OR REG/ MEM, DATA

OR REG, DATA (REG)  (REG) | DATA 162

OR

The OR operation sets (makes one) any bit in the binary

number.
This illustrated in the figure below

163
XOR
Syntax: XOR destination, source
 Used to perform Exclusive-OR operation over each bit in a
source byte/word with the corresponding bit in a
destination byte/word.
 Stores result in the destination
 The source may be an immediate number, a register, or a
memory location
 The destination may be a register or a memory location
 The source and destination both can’t be memory locations.
 XOR operation with two inputs produces result logic 0 only
when both inputs are logic 0.
 The CF and OF are both 0 after XOR, the PF, SF, and ZF
are affected, AF is undefined.

164
XOR
XOR A, DATA

XOR AL, DATA8 (AL)  (AL) ^ DATA8

XOR AX, DATA 16 (AX)  (AX) ^ DATA16

XOR REG2/MEM, REG1/MEM

XOR REG2, REG1 (REG1)  (REG1) ^ (REG2)

(REG2)  (REG2) ^ (MEM)

XOR REG2, MEM
(MEM)  (MEM) ^ (REG1)
XOR MEM, REG1

XOR REG/ MEM, DATA

XOR REG, DATA (REG)  (REG) ^ DATA 165

XOR

The XOR operation inverts (complements) some bits of

a register or memory location.
This instruction allows part of a number to be
inverted or complemented.
This illustrated in the figure below

166
NOT instruction
Syntax: NOT destination

The NOT instruction inverts each bit of a byte or a

word.
The destination can be a register or a memory
location.
NB: NOT instruction affects no flags

167
TEST and Bit Test Instruction
Syntax: TEST destination, source

The TEST instruction performs the AND operation.

 The difference is that the AND instruction changes
the destination operand, while the TEST instruction
does not.
 A TEST only affects the condition of the flag register,
which indicates the result of the test.
168
TEST
TEST A, DATA

TEST AL, DATA8 MODIFY FLAGS  (AL) & DATA8

TEST AX, DATA 16 MODIFY FLAGS  (AX) & DATA16

TEST REG2/MEM, REG1/MEM

TEST REG2, REG1 MODIFY FLAGS  (REG1) & (REG2)

MODIFY FLAGS  (REG2) & (MEM)

TEST REG2, MEM
MODIFY FLAGS  (MEM) & (REG1)
TEST MEM, REG1

TEST REG/ MEM, DATA

TEST REG, DATA MODIFY FLAGS  (REG) & DATA

TEST MEM, DATA MODIFY FLAGS  (MEM) & DATA

169
TEST and Bit Test Instruction
 Flags after TEST operation
 PF, SF and ZF will be updating to show the results of
the ANDing.
 PF has meaning only for the lower 8-bits of the
destination.
 AF will be undefined.

 The TEST instructions functions in the similar manner as

a CMP instruction.
 The difference is that the TEST instruction normally
tests a single bit ( or occasionally multiple bits), while
the CMP instruction tests the entire byte or word.
170
TEST and Bit Test Instruction
 The fig below shows the bit pattern and test operation for
testing of bit 0.
 If ZF is set ( ZF = 1) after this operation, the bit
under test bit-0 is zero; otherwise bit-0 is 1.

• The zero flag is usually tested by JZ or JNZ instructions.

• Therefore, the TEST instruction is usually followed
by either the JZ or JNZ instruction.
171
Bit Manipulation Instructions(LOGICAL
Instructions)
• AND
– Especially used in clearing certain bits (masking)
xxxx xxxx AND 0000 1111 = 0000 xxxx (clear the
first four bits)
– Examples: AND BL, 0FH

• OR
– Used in setting certain bits
xxxx xxxx OR 0000 1111 = xxxx 1111
(Set the upper four bits)

172 172
XOR
– Used in Inverting bits

xxxx xxxx XOR 0000 1111 = xxxxx’x’x’x’

-Example: Clear bits 0 and 1, set bits 6 and 7,

invert
bit 5 of register CL:
AND CL, FCH ; 1111 1100 B
OR CL, C0H ; 1100 0000B
XOR CL, 20H ; 0010 0000B

173 173
BEFORE EXECUTION AFTER EXECUTION

AH FF AL AH 11 AL 11
FF AND AX,BXH
BH 11 BL 11
BH 11 BL 11

AX = FFFFH = 1111 1111 1111 1111

BX = 1111H = 0001 0001 0001 0001 AND
(&)
AND
0001 0001 0001 0001 = 1111H

174
BEFORE EXECUTION AFTER EXECUTION

AH FF AL FF AH FF AL FF
OR AX,BXH
BH 11 BL 11 BH 11 BL 11

AX = FFFFH = 1111 1111 1111 1111

BX = 1111H = 0001 0001 0001 0001 OR

OR 1111 1111 1111 1111 = FFFFH

175
BEFORE EXECUTION AFTER EXECUTION

AH FF AL AH EE AL EE
FF XOR AX,BXH
BH 11 BL 11
BH 11 BL 11

AX = FFFFH = 1111 1111 1111 1111

BX = 1111H = 0001 0001 0001 0001

XOR 1110 1110 1110 1110 = EEEEH

176
BEFORE EXECUTION AFTER EXECUTION

AH 00 AL 00
AH FF AL FF NOT AXH

AX = FFFFH = 1111 1111 1111 1111

NOT 0000 0000 0000 0000 = 0000H

177
Shift & Rotate Instructions
Shift Instructions
 These instructions position or move binary data to
the left or right by shifting them within the register or
memory location.
 They also perform multiplication by powers of (left
shift) and division by powers of (right shift)
 The shift operations can be classified as:
o Logical shifts
o Arithmetic shifts
 The Logical Shifts move a 0 into the rightmost bit position
for a logical left shift (SHL) and 0 into the leftmost bit
position for a logical right shift (SHR).

178
Shift & Rotate Instructions
Shift Instructions … continued
 The Logical Left Shift (SHL) and Arithmetic Logical Shift (SAL)
operations are identical.
 However, Logical Right Shift (SHR) and Arithmetic Right Shift ( SAR)
operations are different, because;
o SAR copies the sign bit through the number, while SHR copies a 0
through the number.
 Logical Shift operations are used with unsigned numbers; they perform
multiplication or division of unsigned numbers.
 On the other hand, Arithmetic Shift operations are used with signed
numbers; they perform multiplication or division of signed numbers.
179
Shift & Rotate Instructions
Shift Instructions … continued

180
SHL/ SAL
Syntax: SHL/SAL destination, count
 SHL and SAL are two mnemonics for the same instruction.
 This instruction shifts each bit in the specified destination to the left and
0 is stored at LSB position.
 The MSB is shifted into the carry flag.
 The destination can be a byte or a word in a register or memory
 The number of shifts are indicated by count.
 If the number of shifts are greater than 1, then shift count must be
loaded in CL register and CL must be placed in the count position of the
instruction.
 FLAGS: All flags are affected.
181
SHL/ SAL
 Diagram bellow shows SHL/SAL instruction for byte operation

182
SHL Instruction
The SHL (shift left) instruction performs a logical
left shift on the destination operand, filling the
lowest bit with 0.

0
CF

mov dl,5d

shl dl,1
183 183
SHL

184
SHR Instruction
Syntax: SHR destination, count
 This instruction shifts each bit in the specified destination to the right
and 0 is stored at MSB position.
 The LSB is shifted into the carry flag.
 The destination can be a byte or a word in a register or in a memory
location.
 The number of shifts are indicated by count.
 If the number of shifts are greater than 1, then shift count must be
loaded in CL register and CL must be placed in the count position of the
instruction.
 FLAGS: All flags are affected.
185
SHR Instruction
 Diagram blow shows SHR instruction for byte operation.

186
SHR Instruction
The SHR (shift right) instruction performs a logical
right shift on the destination operand. The highest bit
position is filled with a zero.

0
CF

MOV DL,80d
SHR DL,1 ; DL = 40
SHR DL,2 ; DL = 10
187 187
SHR

188
SAR Instruction
Syntax: SAR destination, count
 This instruction shifts each bit in the specified destination some number
of bit positions to the right.
 As a bit is shifted out of the MSB position, a copy of the old MSB is put
in the MSB position.
 The LSB will be shifted into CF
 In case of multiple shifts , CF will contain the bit most recently shifted in
from the LSB.
 Bits Shifted into CF previously will be lost.
 The destination cab be a byte /word in a register or in a memory.

189
SAR Instruction
Syntax: SAR destination, count
 The number of shifts are indicated by count.
 If number of shifts required is one, you can place one (1) in the count
position.
 If the number of shifts are greater than 1, then shift count must be
loaded in CL register and CL must be placed in the count position of the
instruction.
 FLAGS: All flags are affected.

190
SAR Instruction
 Diagram blow shows SAR instruction for byte operation.

191
SAR
Instruction
 SAR (shift arithmetic right) performs a
right arithmetic shift on the destination
operand.

CF

An arithmetic shift preserves the number's

sign.
MOV DL,-80
SAR DL,1 ; DL = -40
SAR DL,2 ; DL = -10
192 192
Shifting left n bits multiplies the operand by2n
For example, 5 * 22 = 20

Shifting right n bits divides the operand by 2n

For example, 80 / 23 = 10

mov dl,5 Before: 00000101 =5

After: 00001010 = 10
shl dl,1

193 193
Shift & Rotate Instructions
Rotate Instructions
 These instructions position or move binary data by rotating the
information in a register or memory location, either from one end to
another or through the carry flag.

194
ROL Instruction
Syntax: ROL destination, count
 This instruction rotates all bits in a specified byte or word to the left some
number of bit positions.
 MSB is placed as new LSB and a new CF.
 The destination can be a byte or a word in a register or in a memory location.
 The number of shifts are indicated by count.
 If number of shifts required is one, you can place one (1) in the count position.
 If the number of shifts are greater than 1, then shift count must be loaded in CL
register and CL must be placed in the count position of the instruction.

195
ROL Instruction
 Diagram blow shows ROL instruction for byte operation.

196
ROL
Instruction
ROL (rotate) shifts each bit to the left
The highest bit is copied into both the Carry
flag and into the lowest bit
No bits are lost

CF

MOV Al,11110000b
ROL Al,1 ; AL = 11100001b

MOV Dl,3Fh
ROL Dl,4 ; DL = F3h
197 197
ROR Instruction
Syntax: ROR destination, count
 This instruction rotates all bits in a specified byte or word to the right some
number of bit positions.
 LSB is placed as new MSB and a new CF.
 The destination can be a byte or a word in a register or in a memory location.
 The number of shifts are indicated by count.
 If number of shifts required is one, you can place one (1) in the count position.
 If the number of shifts are greater than 1, then shift count must be loaded in CL
register and CL must be placed in the count position of the instruction.

198
ROR Instruction
 Diagram blow shows ROR instruction for byte operation.

199
ROR
Instruction
ROR (rotate right) shifts each bit to the right
The lowest bit is copied into both the Carry flag
and into the highest bit
No bits are lost

C
F

MOV AL,11110000b
ROR AL,1 ; AL = 01111000b

MOV DL,3Fh
ROR DL,4 ; DL = F3h
200 200
RCL Instruction
Syntax: RCL destination, count
 This instruction rotates all bits in a specified byte or word some number of bit
positions to the left along with the carry flag .
 MSB is placed as new Carry and previous Carry is placed as a new LSB. The
destination can be a byte or a word in a register or in a memory location.
 The number of shifts are indicated by count.
 If number of shifts required is one, you can place one (1) in the count position.
 If the number of shifts are greater than 1, then shift count must be loaded in CL
register and CL must be placed in the count position of the instruction.

201
RCL Instruction
 Diagram blow shows RCL instruction for byte operation.

202
RCL
Instruction
RCL (rotate carry left) shifts each bit to the left
 Copies the Carry flag to the least significant bit
 Copies the most significant bit to the Carry flag

CF

CLC ; CF = 0
MOV BL,88H ; CF,BL = 0 10001000b
RCL BL,1 ; CF,BL = 1 00010000b
RCL BL,1 ; CF,BL = 0 00100001b
203 203
RCL
Instruction

204 204
RCR Instruction
Syntax: RCR destination, count
 This instruction rotates all bits in a specified byte or word some number of bit
positions to the right along with the carry flag .
 LSB is placed as new Carry and previous Carry is placed as a new MSB.
 The destination can be a byte or a word in a register or in a memory location.
 The number of shifts are indicated by count.
 If number of shifts required is one, you can place one (1) in the count position.
 If the number of shifts are greater than 1, then shift count must be loaded in CL
register and CL must be placed in the count position of the instruction.

205
RCR Instruction
 Diagram blow shows RCR instruction for byte operation.

206
RCR
Instruction
RCR (rotate carry right) shifts each bit to the
right
Copies the Carry flag to the most significant bit
Copies the least significant bit to the Carry flag
CF

STC ; CF = 1
MOV AH,10H ; CF,AH = 00010000 1
RCR AH,1 ; CF,AH = 10001000 0

207 207
RCR
Instruction

208
SHL Instruction
The SHL (shift left) instruction performs a logical
left shift on the destination operand, filling the
lowest bit with 0.
0
CF

BEFORE
EXECUTION
0 0 0 0 0 1 0 1 =05H
CF
0 0 0 0 1 0 1 0 =0AH
AFTER 0
EXECUTION

209
SHR Instruction

0
CF

BEFORE
EXECUTION
0 0 0 0 0 1 0 1 =05H
CF
AFTER 0 0 0 0 0 0 1 0
EXECUTION
1
=02H
210
ROL Instruction

CF

BEFORE
EXECUTION 0 0 0 0 0 1 0 1 =05H

CF
AFTER 0 0 0 0 0 1 0 1 0 =0AH
EXECUTION

211
ROR Instruction

CF

0 0 0 0 0 1 0 1 =05H
BEFORE
EXECUTION

CF

AFTER 1 0 0 0 0 0 1 0 1 =82H
EXECUTION

212
Branching Instructions
(or) Program execution
Transfer Instructions
These instructions cause change in the sequence of the
execution of instruction.
This change can be through a condition or
sometimes unconditional.
The conditions are represented by flags.

213
Program Control Transfer
(Branch) Instructions
Aka program execution transfer instructions.
 These instructions transfer the flow of execution of the
program to a new address specified in the instruction
directly or in directly
 Depending upon the addressing modes, the CS may or may
not be modified. These type of instructions are classified as:
I. Unconditional Transfer instructions – CALL, RET, JMP
II. Conditional Transfer Instructions – J cond.
 In the assembly language programming, more than one
data/ code/ stack segments can be defined. But only one
segment of each type can be accessed at any time.

214
Program Control Transfer
(Branch) Instructions
• Depending upon the addressing modes, the CS may or may not
be modified. These type of instructions are classified as:
I. Unconditional Transfer instructions – CALL, RET, JMP
o In case of these instructions, the execution control is
transferred to the specified location independent of any
status or condition.
o The CS and IP are unconditionally modified to the new
CS and IP.
II. Conditional Transfer Instructions – J cond.
o In case of these instructions, the execution control is
transferred to the specified location provided the result of
the previous operation satisfies a particular condition,
otherwise, the execution continues in normal flow
sequence.
215
Program Control Transfer Instructions
CALL
 Used to call a procedure and save their return
address to stack.
 Procedure
o aka subroutine.
o is a group of instructions stored as a separate program
in the memory and it is called/invoked from the main
program whenever required.
• Types of Procedure
 depends on where the procedure is stored in the main
memory.
 Near Procedure & Far Procedure
o If it is in the same code segment where the main program is
stored it is referred to as near procedure, otherwise it is
called far procedure. 216
Program Control Transfer Instructions
• CALL
• Types of Procedures
I. Near Procedure (i.e., 32 KB displacement)
o for near procedures, CALL instruction pushes only
the IP register contents on the stack, since CS register
contents remains unchanged for main program and
procedure.
II. Far Procedure (any where outside the current segment)
o But for far procedures, CALL instruction pushes IP
and CS on the stack.
• The modes for them are respectively called as intrasegment
and intersegment addressing modes.

217
Program Control Transfer Instructions
• CALL
• Types of CALLs
I. Near CALL
o is a call to a procedure which is in the same code
segment as the CALL instruction.
o When a near call is being executed, the SP is
decremented by 2 and then the address (offset address
on IP) of the next instruction after the CALL
instruction, is copied onto the stack.
o IP is then get loaded with the offset of the first
instruction of the procedure in same segment.
II. Far CALL
o is a call to a procedure which is in a different segment
from that which contains the CALL instruction.
218
Program Control Transfer Instructions
• CALL
• Types of CALLs
I. Near CALL
II. Far CALL
o When a far call is being executed; SP will be decremented
by 2 and then the contents of the CS register will be copied
onto the stack.
o SP will be decremented by 2 again, and then the offset of
the instruction after CALL instruction will be copied on to
the stack.
o Finally, CS will be get loaded with the base of the
destination segment which contains the procedure and IP
will be get loaded with offset of the first instruction of the
procedure in the destination segment.

219
Program Control Transfer Instructions
• CALL Instruction

220
Program Control Transfer Instructions
• RET Instruction:
 RET: Return from the procedure/subroutine.
 will return execution from a procedure to the next
instruction after the CALL instruction in the calling
program.
 If the procedure is a near procedure, then the return will
be done by replacing the IP register with a word from the
top of the stack.
 If the procedure is a far procedure;
o then IP register will be loaded with the word at the top of
the stack.
o The SP will then be incremented by two.
o The CS register is then get loaded with a word form the
new top of the stack. Then SP is again incremented by 2.
 No flags are affected with RET instruction.
221
SUBROUTINE & SUBROUTINE HANDILING
INSTRUCTIONS
Main
program
Subroutine
A
First Instruction
Call subroutine A
Next instruction

Return
Call subroutine A
Next instruction

222
Program Control Transfer Instructions
• JMP Instruction
 This instruction causes an instruction is to be
fetched from the location specified in the JMP
instruction rather than from the next location
after the JMP instruction.
 The JMP instructions are basically classified as
unconditional jump and conditional jump instructions.
 A Conditional Jump instruction allows the programmer to
make decisions based up on numerical tests.
 The results of the numerical tests are held in the flag bits,
which are then tested by conditional jump instructions.

223
Program Control Transfer Instructions
• JMP Instruction
 The JMP instructions are further classified as short, near, and far
jump instructions.
 Short JUMP
o Allows jumps or branches to memory locations within +127 and -
128 bytes from the address of the instruction following the jump.
 NEAR JUMP
o Allows a jump or branch to memory locations within ±32 Kbytes (or
anywhere in the current code segment) from the address of the
instruction following the jump.
o Only IP is changed, the contents of the CS remains the same.
 Far JUMP
o Allows a jump or branch to any memory location within the real
memory system.
o Destination location is from a different segment.
o Both IP and CS changed.
224
Program Control Transfer Instructions
• JMP Instruction
 The SHORT and NEAR jumps are often called
intrasegment jumps, and the FAR jumps are often called
intersegment jumps.
 NEAR and FAR jumps are further described as either
direct or indirect.
o If the address for the jump is specified directly within the
instruction, then the jump is described as direct.
o If the destination address for the jump is contained in a
register, or memory location, the jump is referred as
indirect.
 A positive displacement usually means jump is ‘ahead’ in
the program, and a negative displacement usually means
jump is ‘backward’ in the program.
225
Program Control Transfer Instructions
• JMP Instruction
Assume the following state of 8086: (CS)=2000H, (IP)=0300H, (SI)=A00H,
(DS)=400H, (DS:A00)=10H, (DS:A01)=B3H, (DS:A02)=22H, (DS:A03)=1AH.
To what address is program control passed if each of the following JMP
instruction is execute?

(a) JMP 85  2000:85  Short jump

(b) JMB 1000H  2000:1000  Near jump
(c) JMP [SI]  2000: B310  Near jump
(d) JMP SI  2000: 0A00  Near jump
(e) JMP FAR [SI]  1A22: B310  Far jump
(f) JMP 3000:1000  3000:1000  Far jump

226
Program Control Transfer Instructions
• JMP Instruction

227
Program Control Transfer Instructions
• JMP Instruction

228
Program Control Transfer Instructions
• JMP Instruction
 Conditional Jumps
 are always short jumps in 8086.
 These instructions will cause a jump to a label given in
the instruction if the desired condition(s) occurs in the
program before the execution of the instruction.
 Test the following flag bits: SF, ZF, CF, PF and OF
o If the condition under test is true, a branch to the
label associated with jump instruction occurs.
o If the condition is false, execution simply goes on the
next instruction.
 The destination must be in the range of -128 bytes to +127
bytes from the address of the instruction after the conditional
transfer instruction.

229
Program Control Transfer Instructions
• JMP Instruction
 Conditional Jumps

230
Program Control Transfer Instructions
• JMP Instruction
 Unsigned Conditional Jumps

231
Program Control Transfer Instructions
• JMP Instruction
 Unsigned Conditional Jumps

232
Program Control Transfer Instructions
• JMP Instruction
 Conditional Jumps
Example 2: Write a program to move a block of 100 consecutive bytes of data
starting at offset address 400H in memory to another block of memory
locations starting at offset address 600H. Assume both block at the same data
segment 3000H. Use conditional jump instruction.
Solution:
MOV AX, 3000H
MOV DS, AX DS=3000H
MOV SI, 0400H
ES=3000H
MOV DI, 0600H
MOV CX, 64H
NXT: MOV AH, [SI] SI=0400H
MOV [DI], AH DI=0600H
INC SI Counter=CX=64H=100byte
INC DI
DEC CX
JNZ NXT
HLT 233
Program Control Transfer Instructions
• JMP Instruction
 Conditional Jumps
Example 3: Write a program to add (50)H numbers stored at memory
locations start at 4000:0100H , then store the result at address 200H in the
same data segment.
Direction Flag=0, CLD
Solution: DS=4000H
MOV AX , 4000H ES=4000
MOV DS , AX SI=0100H
MOV CX , 0050H DI= 0200
MOV SI, 0100H Counter=CX=50H
XOR AX, AX ; OR (MOV AL, 00H)
Again: ADD AX, [BX]
INC SI
DEC CX
JNZ Again
MOV [0200], AX ; OR (MOV [DI] , AX)
NB: Re-read: After CALL & JUMP instructions , Program Memory
234
addressing Modes.
Iteration Control (LOOP) Instructions
• These instructions are used to execute a series of
instructions some number of times.
• The number is specified in the CX register.
• The CX register is automatically decremented by one,
each time after the execution of loop instruction.
• Until CX = 0, execution will jump to a destination
specified by a label in the instruction.
• The destination address for the jump must be in the
range of -128 bytes to +127 bytes from the address of
the instruction after the iteration control instruction.

235
Iteration Control (LOOP) Instructions
• There is one condition for exit from loop, see table
• If the condition is false , execution simply goes onto the
next instruction after the iteration control instruction

Mnemonic Meaning Condition for exit

LOOP Loop CX=0
LOOPE/LOOPZ Loop while equal/ CX= 0 or ZF = 0
Loop while Zero
LOOPNE/LOOPNZ Loop while not CX = 0 or ZF = 1
equal / Loop
while not zero

236
Iteration Control (LOOP) Instructions
Example
Write a program to move a block of 100 consecutive bytes of data starting at
offset address 400H in memory to another block of memory locations starting
at offset address 600H. Assume both block at the same data segment 3000H.
Use LOOP instruction.
Solution:
MOV AX, 3000H
MOV DS, AX
MOV SI, 0400H DS=3000H
MOV DI, 0600H ES=3000H
MOV CX, 64H
NXT: MOV AH, [SI] SI=0400H
MOV [DI], AH DI=0600H
INC SI
Counter=CX=64H=100byte
INC DI
LOOP NXT
HLT
NB: Compare and contrast this program with the one on slide 233
237
STRING MANIPULATION INSTRUCTIONS
 String : Sequence of bytes or words
 is a series of the same type of data items in sequential memory locations
 8086 instruction set includes instruction for string movement, comparison,
scan, load and store.

 REP instruction prefix : used to repeat execution of string instructions

 String instructions end with S or SB or SW. S represents string, SB string

byte and SW string word.

 Offset or effective address of the source operand is stored in SI register and

that of the destination operand is stored in DI register.

 Depending on the status of DF, SI and DI registers are automatically

updated.

o DF = 0 SI and DI are incremented by 1 for byte and 2 for word.

o DF = 1 SI and DI are decremented by 1 for byte and 2 for word.

238
STRING MANIPULATION INSTRUCTIONS

The 8086 instruction set provides following

string instruction.
REP/REPE/REPZ/REPNE/REPNZ

MOVS/MOVSB/MOVSW

LODS/LODSB/LODSW

STOS/STOSB/STOSW

CMPS/COMPSB/COMPSW

SCAS/SCASB/SCASW
239
STRING MANIPULATION INSTRUCTIONS
MOVS/MOVSB/MOVSW instruction
 These instructions copy a byte or word form a location in
the data segment to a location in the extra segment
 SI must contain the offset of the source byte or word in the
data segment
 DI must contain the offset of the destination in the extra
segment.
 For multiple byte or multiple word moves, the number of
elements to be moved is put in CX register. CX is function as
a counter.
 After the byte or word is moved, SI and DI are
automatically adjusted to point to the next source and next
destination.
 If DF = 0, SI and DI will be incremented by 1 after a byte
move, and they will be incremented by 2 after a word move.
240
STRING MANIPULATION INSTRUCTIONS

MOVS/MOVSB/MOVSW instruction
 IfDF = I, SI and DI will be decremented by 1 after a byte
move, and they will be decremented by 2 after a word move.
 MOVSB--- move string as bytes, MOVSW--- move string as
a word
MOVS affects no flag

241
STRING MANIPULATION INSTRUCTIONS
REP/REPE/REPZ/REPNE/REPNZ instruction
 REP isa prefix which is written before one of the string
instructions to repeat execution of it until CX = 0
Mnemonic Meaning Condition for exit
REP Repeat CX=0
REPE/REPZ Repeat while equal/ CX= 0 or ZF = 0
Repeat while Zero
REPNE/ Repeat while not equal/ CX = 0 or ZF = 1
REPNZ Repeat while not zero

242
STRING MANIPULATION INSTRUCTIONS
LODS/LODSB/LODSW instruction
 This instruction copies a byte from a string location
pointed to by SI to AL, a word from string location
pointed to by SI to AX
 LODS does not affect any flag.
 LODSB copies a byte, LODSW copies a word.

243
STRING MANIPULATION INSTRUCTIONS
STOS/STOSB/STOSW instruction
 This instruction copies a byte from AL or a word from AX to
memory location in the extra segment.
 DI is used to hold the offset of the memory location
 After copy DI is automatically incremented or decremented
to point to the next string element in the memory.
 If DF = 0, then DI will automatically be incremented by one
for a byte string or incremented by 2 for a word string.

244
STRING MANIPULATION INSTRUCTIONS
STOS/STOSB/STOSW instruction
 IfDF = 01 then DI will automatically be decremented by one
for a byte string or decremented by 2 for a word string.
 STOSB copies byte and STOSW copies a word.
 STOS doesn’t affect any flag.

245
STRING MANIPULATION INSTRUCTIONS
CMPS/COMPSB/COMPSW instruction
 Can be used to compare a byte in one string with a
byte in another string or a word in one string with a
word in another string.
 SI is used to hold offset of a byte or word in the source
string
 DI is used to hold the offset of a byte or word in the
destination string
 The comparison is done by subtracting the byte or
word pointed to by DI from the byte or word pointed
to by SI
 The AF, CF, OF, ZF, PF and SF flags are affected but
neither operand is affected

246
STRING MANIPULATION INSTRUCTIONS
CMPS/COMPSB/COMPSW instruction
 After the comparison, SI and DI will be automatically incremented or
decremented according to DF. (If DF = 0, SI and DI otherwise )
 CX function as a Counter which is decremented after each comparison is a
counter . This will go until CX = 0

247
STRING MANIPULATION INSTRUCTIONS
SCAS/SCASB/SCASW instruction
 SCAS compares a string byte with a byte in AL or a string
word with word in AX.
 The instruction affects the flags, but it does not change
either the operand in AL(AX) or the operand in the string.
 The string to be scanned must be in the extra segment.
 DI must contain the offset of the byte or word to be
compared
 The AF, CF, OF, ZF, PF and SF flags are affected.

248
STRING MANIPULATION INSTRUCTIONS
CMPS/COMPSB/COMPSW instruction
 After the comparison, SI and DI will be automatically incremented or
decremented according to DF. (If DF = 0, SI and DI otherwise )
 CX function as a Counter which is decremented after each comparison is a
counter . This will go until CX = 0

249
REP

250
MOVS

251
MOVS

252
CMPS

253
SCAS

254
SCAS

255
LODS

256
STOS

257
1. Copying a string (MOV SB)
MOV CX,0003 copy 3 memory locations
MOV SI,1000
MOV DI,2000
L1 CLD
MOV SB
DEC CX decrement CX
JNZ L1
HLT
258
2. Find & Replace

259
REP (Repeat):

This is an instruction prefix.

It causes the repetition of the instruction until CX

becomes zero.
E.g.: REP MOVSB STR1, STR2

 It copies byte by byte contents.

 REP repeats the operation MOVSB until CX becomes zero.

260 260
Flag Manipulation and Processor Control
Instructions
THESE INSTRUCTIONS CONTROL THE
FUNCTIONING OF THE AVAILABLE
HARDWARE INSIDE THE PROCESSOR CHIP
TWO TYPES:

I. FLAG MANIPULATION
II. MACHINE(PROCESSOR ) CONTROL
INSTRUCTIONS

261
Flag Manipulation and Processor Control
Instructions
• FLAG MANIPULATION Instructions
 The flag manipulation instructions directly
modify some of the flags of 8086.
 These instructions modify the carry,
direction and interrupt flags

262
Flag Manipulation and Processor Control
Instructions
• Machine Control Instructions
 These instructions control the bus usage and
execution.
 Don't require any operand

263
Flag Manipulation and Processor Control
Instructions
• Machine Control Instructions

264
Processor Control Instructions
These instructions control the processor itself.

8086 allows to control certain control flags that:

causes the processing in a certain direction

processor synchronization if more than one

microprocessor attached.

265 265
Flag manipulation and Processor Control Instructions

266
 STC
It sets the carry flag to 1.

 CLC

It clears the carry flag to

0.
 CMC
It complements the carry
flag.

267 267
 STD:
It sets the direction flag to 1.

If it is set, string bytes are accessed from higher memory

address to lower memory address.

 CLD:
It clears the direction flag to 0.

If it is reset, the string bytes are accessed from lower

memory address to higher memory address.

268 268
 HLT instruction – HALT processing
The HLT instruction will cause the 8086 to stop fetching and
executing instructions.

NOP instruction
this instruction simply takes up three clock cycles and does
no processing.

LOCK instruction
this is a prefix to an instruction. This prefix makes sure that
during execution of the instruction, control of system bus is not
taken by other microprocessor.

WAIT instruction
this instruction takes 8086 to an idle condition. The
CPU will not do any processing during this.
269 269
Interrupts Instructions
INT instruction: INT type
 This instruction causes the 8086 to call a far
procedure.
 The term type in the instruction refers to a
number between 0-255 which identifies the
interrupt.
 The address of the procedure is taken the
memory whose address is four times the type
270
number.
Interrupts Instructions
INT instruction: INT type

271
Interrupts Instructions
IRET instruction:

 This instruction is used at the end of the interrupt

service routine to return execution to the interrupted
program.
 The 8086 copies return address from stack into IP and
CS register and the stored value of flags back to the flag
register.
 Note: The RET does not copy the flags from the stack
back to the flag register. 272
Interrupts Instructions
IRET instruction:

273
Interrupts Instructions
INTO instruction:
 If the overflow flag (OF) is set, this instruction will
cause the 8086 to do an indirect far call to a procedure
you write to handle overflow condition.
 To do call the 8086 will read a new value for IP from
address 00010H and a new values of CS from address
00012H.

274
INSTRUCTION SET-summary
1.DATA TRANSFER INSTRUCTIONS
Mnemonic Meaning Format Operation

MOV Move Mov D,S (S)  (D)

XCHG Exchange XCHG D,S (S) (D)

LEA Load Effective Address LEA Reg16,EA EA  (Reg16)

PUSH pushes the operand into top of PUSH BX sp=sp-2

stack. Copy 16 bit value to top
of stack

POP pops the operand from top of POP BX Copy top of stack to 16
stack to Des. bit reg
sp=sp+2

IN transfers the operand from IN AL,28

specified port to accumulator
register.

OUT transfers the operand from OUT 28,AL

accumulator to specified
port. 168
275
2. ARITHMETIC INSTRUCTIONS
Mnemonic Meaning Format Operation

SUB Subtract SUB D,S (D) - (S)  (D)

Borrow  (CF)
SBB Subtract with SBB D,S (D) - (S) - (CF)  (D)
borrow
DEC Decrement by one DEC D (D) - 1  (D)
NEG Negate NEG D
DAS Decimal adjust for DAS Convert the result in AL to packed
subtraction decimal format
AAS ASCII adjust for AAS (AL) difference (AH) dec by 1 if
subtraction borrow
ADD Addition ADD D,S (S)+(D)  (D) carry  (CF)

ADC Add with carry ADC D,S (S)+(D)+(CF)  (D) carry  (CF)

INC Increment by one INC D (D)+1  (D)

AAA ASCII adjust for AAA If the sum is >9, AH
addition
is incremented by 1
DAA Decimal adjust for DAA Adjust AL for decimal Packed B1C69D
addition
3. Bit Manipulation Instructions(Logical Instructions)
3.1. Instructions

170
277
3. Bit Manipulation Instructions(Logical Instructions)
3.2. Shift & Rotate Instructions
Mnemonic Meaning Format
SAL/SHL Shift arithmetic Left/ SAL/SHL D, Count
Shift Logical left

SHR Shift logical right SHR D, Count

Shift arithmetic SAR D,

right
SAR Count

Mnemonic Meaning Format

ROL Rotate Left ROL D,Count

ROR Rotate Right ROR D,Count

RCL Rotate Left through Carry RCL D,Count

RCR Rotate right through Carry RCR D,Count

278
4. Branching or PROGRAM
EXECUTION TRANSFER INSTRUCTIONS
• CALL - call a subroutine
• RET - returns the control from procedure to calling
program
• JMP Des – Unconditional Jump
• Jxx Des – conditional Jump (ex: JC 8000)
• Loop Des

279
5. Iteration Control Instructions
• Loop Des
 LOOP
 LOOPE/LOOPZ
 LOOPNE/LOOPNZ

280
6. STRING INSTRUCTIONS
• CMPS Des, Src - compares the string bytes
• SCAS String - scans a string
• MOVS / MOVSB / MOVSW - moving of byte or
word
• REP (Repeat) - repetition of the instruction

281
7. Flag Manipulations
and
PROCESSOR CONTROL INSTRUCTIONS
• STC – set the carry flag (CF=1)
• CLC – clear the carry flag (CF=0)
• STD – set the direction flag (DF=1)
• CLD – clear the direction flag (DF=0)
• HLT – stop fetching & execution
• NOP – no operation(no processing)
• LOCK - control of system bus is not taken by other µP
• WAIT - CPU will not do any processing
• ESC - µP does NOP or access a data from memory for
coprocessor 282
8. Interrupt Instructions
• INTN
• IRET
• INTO

283