verilog

Type of issue: other enhancement

Impact: no functional change

Development Phase: request

Other information
This is more a meta-issue mostly related to the beginners user experience. I think most of these issues are not done by more experienced devs.

If the current behavior is a bug, please provide the steps to reproduce the problem:

1. Start with [chisel-templat

[...] since the increase to 64-bit wide busses, using drop-down lists to choose the bit width and selecting bits is tedious, [...]

By @maehne in #617 (comment)

In C++ instead of using the syntax (void)unused_param, it is customary to simply leave the parameter unnamed. Now that all libraries are C++, we can do this universally and deprecate COCOTB_UNUSED.

Thanks for taking the time to report this.

What would you like added/supported?

// File: dly_warning.sv

// verilator lint_off ASSIGNDLY

module dly_warning (
    input logic a_in,
    input logic [2:0] delaycw,

    output logic a_out
);

timeunit 1ns;
timeprecision 1ns;

time dly;

assign dly = 5 * delaycw;
assign #dly a_out = a_in;     // Warning ASS

Tuo Xie requested the ability to visualize clocking (pins & wires I believe). We should make it easier to visualize subsets of the device routing resource and types of routing nets.

Proposed Behaviour

Add filtering to the rr_nodes displayed (ToggleRR), and to the nets displayed (ToggleNets). I think we should have an option to filter what is shown by node type, node name (segment or pin t