A computer usually have a variety of instruction code formats.

It is the function of the control unit with in the CPU to interpret each instruction code and provide necessary control functions needed to process the instruction. The format of an instruction is usually depicted in a rectangular box symbolizing the bits of the instructions as they appear in memory words or in a control register. The bits of the instruction are divided in to groups called fields. The most common fields found in the instruction formats are as follows: The OPCODE field that specifies the operation to be performed. The address field that specifies the memory address or a processor register. A mode field that specifies the way the operand or effective address is determined. Other special fields are sometimes employed under certain circumstances. Ex: The field that gives the number of shifts in a SHIFT type instruction. The operation code field of an instruction is a group of bits that defines various processor operations , such as add, sub, complement, and shift . The bits that define mode field of an instruction code specify a variety of alternatives for choosing the operands from the given address. The address field an instruction format specified by computer instruction are executed on some data stored in memory or processor register. Operands residing in the memory are specified by their memory address. Operands residing in the processor registers are specified by their register address. A register address is a binary number of k bits that define one of (2 power k) registers in the CPU. The CPU with 16 processor registers Ro through R15 will have a register field of four bits. Ex: The binary number 0101 designates register R5. Computers may have instructions of several different lengths containing varying number of addresses. The number of address fields in the instruction format of a computer depends on the internal organization of its registers. Most computers fall one of the three types of CPU organizations: Single Accumulator organization. General register organization. Stack organization. In an Accumulator organization all operations are performed with an accumulator register. The instruction format in this type of computer uses one address field. The instructions are referred as ONE ADDRESS Instructions The more general instruction format could look like Operation operand Ex: ADD X . This means that add the contents of the memory location X to the contents of an accumulator and store the result in accumulator.

In the general register type organization the instruction format need three addresses fields. The instructions are referred as THREE ADDRESS instructions. Thus the instruction for arithmetic addition is written as General form is as follows Operation Destination,Source1,Source2 .For Ex: ADD R1,R2,R3 ==> R1<-- R2+R3 This means add the contents of source operand register2 with the contents of source operand register3 store the result in the destination register1. The number address fields are reduced from three to two if the destination register is same as one of the source register. Such an instructions are referred as TWO ADDRESS instructions. The general form could be Operation Destination , Source Ex: ADD R1,R2 ==> R1<--R1+R2 This means that add the contents of the source register2 with the contents of destination register1 and store the result in the destination register1. General register type computer employ two or three address fields in their instruction format. Each address field may specify a processor register or a memory word. Ex: ADD R1,X ==> R1<-- R1+ M[X] It has two address fields one for the register and one for the memory address X. In a stack organized computer all operations are performed with stack. The register that holds the address of the top of the stack is called stack pointer register. Two operations are performed with the stack .They are insertion is called PUSH and deletion is called POP. Stack organized instructions are also called ZERO ADDRESS instructions because we are not specifying the address of the operand and by default it refers to the TOP of the stack. The above given formats are compatible with INTEL POWER PC computer. Some computers such as MOTOROLA 68000 adopt the following formats for three address , two address and one address instructions. Three address instruction format for Motorola 68000 Operation Source1,Source2,Destination Two address instruction format for Motorola 68000 Operation Source ,Destination, One address instruction format for Motorola 68000 Operation operand A computer must have instructions capable of performing three of operations. types

Data Manipulation Instructions: These are the instructions that perform arithmetic, logical and shift operations

Arithmetic operations: Name Increment Decrement ADD Subtraction Multiply Divide Add with carry Mnemonic INC DEC ADD SUB MUL Div ADDC Meaning Increment the contents of a register Decrement the contents of a register Add the contents of two registers (or) Contents of a register and memory. Subtract the contents of two registers (or) Contents of a register and memory. Multiply the contents of two registers (or) Contents of a register and memory. Divide the contents of two registers (or) Contents of a register and memory. Add the contents of two registers with carry (or)Contents of a reg and memory with carry Sub the contents of two registers with borrow (or)Contents of a reg and memory with borrow. Meaning Perform 2 complementation on the given number Clear the contents of a register or Memory location Complement the contents of a register. Perform logical AND operation Perform logical OR operation Perform logical XOR operation Clear the carry flag Set the carry flag. Complement the carry flag Set the interrupt flag Disable interrupt flag

Subtract with SUBB carry borrowOperations: Logical Name Negate Clear Mnemonic NEG CLR

Complement COM AND OR Exclusive OR Clear carry Set carry AND OR XOR CLRC SETC

Complement COMC Carry Enable Interrupt Disable Interrupt EI DI

Shift instructions: Name Logical Shift Right Logical Shift Left Arithmetic Shift Left Arithmetic Shift Right Rotate Right Rotate Left Rotate Right Thru Carry Rotate Left Thru Carry Mnemonics SHR SHL SHLA SHRA ROR ROL RORC ROLC

Data transfers instructions: Transfers information data from one location to another with out changing the binary information contents Name Load Mnemonic LD Meaning Transfers data from memory to processor register

ST Transfers data from processor register to Memory Program sequencing and control. Move MOV Transfers data from one register to another IO transfers. Register it has also been used to transfer data between cpu reg and memory (or) between 40)Explain the different addressing modes Two memory locations. Exchange XCH Used to swap the data between two registers (or) between reg and memory vice versa. Input Output PUSH POP IN OUT PUSH POP Data transfers between the processor regis and input or output terminal. Transfers data between processor register and memory stack

Store

Program Control Instructions: These instructions provide decision making capability and change the path taken by the program when executed in the computer. Name Branch Jump Skip Call Return Compare (By Subtraction) Test (By AND ing) Mnemonics BR JMP SKP CALL RET CMP TST

The operation field of an instruction specifies the operation to be performed. This operation must be performed on some data stored in the computer register or memory words .The way the operands are chosen during the program execution depends on the addressing modes of the instruction. The addressing mode specifies the rule for interpret or modifying the address field of the instruction before the operand is actually referenced. The purpose of addressing modes are.--> To give the programming versatility to the user by providing such facilities as pointers to memory , counters for loop control , indexing of data and program relocation. To reduce the number of bits in the addressing field of an instruction. In order to understand the various addressing modes we need to understand the operation cycle of a computer. The control unit divides the instruction cycle in to three phases. Fetch the instruction from memory Decode the instruction Execute the instruction The Program counter that keeps track of the instruction in the program stored in the memory .PC holds the address of the instruction to be executed and is incremented each time an instruction is fetched from the memory. The decoding is done at step 2. Determine the operation to be performed , the addressing mode of the instruction and the location of the operands. The computer then executes an

addressing modes .

instruction and returns to step 1 to fetch the next instruction in the sequence. In some computers the addressing mode of the instruction is specified with a distinct binary code , just like operation code is specified. Some computers use a single binary code that designates both the operation and the mode of instruction. Op code Mode Address

The op code specifies the operation to be performed. The mode field is used to locate the operands needed for the operation. There may or may not be an address field in the instruction. If there is an address field it may be designated as a memory address or a processor register. 1)Immediate Mode : In this mode the operands are specified implicitly in the definition of the instruction. Ex: Complement Accumulator .Here the operand in the accumulator register is implied in the definition of the instruction. All register reference instructions that use accumulator are implied mode instructions. ZERO ADDRESS instructions in the stack organized computer are implied mode instructions. , because the operands are implied to be top of the stack. 2)Immediate Mode: In this mode the operands are specified in the instructions itself. In other words the immediate mode instruction has operand field rather than address field. The operand field contains the actual operand to be used in conjunction with the operation specified in the instruction. Immediate mode instructions are useful for initializing the register to a constant value. 3)Register Mode: In this mode the operands are specified as a part of the processor registers. The particular register is selected from the register field in the instruction. A k- bit field specifies (2 power k) registers. 4)Register Indirect Mode: In this mode the instruction specifies the register in the CPU whose contents give the address of the operand in the memory. In other words the selected register contains the address of an operand rather than the operand itself. Before using the register indirect mode instruction the programmer must ensures that the memory address of the operand is placed in the processor register with the previous instruction. A reference to this register is then equivalent specifying a memory address. The advantage of the register indirect mode instruction is that the address field of the instruction uses fewer bits to select a register than would have been required to specify a memory address directly. 5)Auto Increment (or) Auto Decrement Mode: This is similar to register indirect mode except that the register is incremented or decremented after (or before) its value is used to access memory . When the address stored in the register refers to a table of data in the memory it is necessary to increment or decrement the register after every access to the table. This can be activated by increment or decrement instructions.

EFFECTIVE DDRESS (EA) is defined as the address obtained from the computation dictated by the given addressing mode. The EA is the address of the operand in a computational type instruction. 6)Direct Addressing Mode: In this addressing mode the EA is equal to the address part of the instruction. The operand resides in the memory and its address is given directly by the address field of the instruction. In branch type instructions the address field specifies the actual branch address. 7)Indirect Addressing Mode: In this mode the address field of an instruction gives the address where the EA is stored in the memory. Control fetches the instruction from the memory and uses its address part to access memory again to read the EA. A few addressing modes require that the address field of the instruction to be added to the contents of the specified register in the CPU. The EA address in these modes can be obtained by the following computation: EA= Address part of the instruction + Contents of CPU register 8)Relative Addressing Mode: In this addressing mode the contents of accumulator is added to the address part of the instruction in order to obtain the EA. When the address part of the instruction is added to the contents of the PC the result produces the EA whose position is relative to the next instruction. Ex: PC contains 825. Address part of the instruction contains the number 24. The instruction at location 825 is read from memory during the fetch phase and PC is incremented by one to 826 . The EA calculation for relative addressing mode is 826+ 24=850. This is 24 memory locations away from the address of the next instruction. Relative addressing is often used with branch type instruction when the branch address is in the area surrounding the instruction word itself. It results in shorter address field in the instruction format since the relative address can be specified with a smaller number of bits compared to the number of bits required designate the entire memory address. 9)Indexed Addressing Mode: In this mode the contents of the index register is added to the address part of the instruction to get the EA of the operand. The index register is a special purpose CPU register that contains the index value. The address part of the instruction determines the starting address of the data array in the memory. Each operand in the array is stored in the memory relative to the starting address of the array. The distance between the starting address of the array and the location of the operand in the array is the index value present in the index register. Any operand in the array can be accessed with the same instruction provided that the index register contains the correct index value. The index register can be incremented to facilitate access to the consecutive operands. Some computers dictate one CPU register to function as index register. This register is involved implicitly when the index mode instruction is used. USE: The indexed addressing mode is used to access the array type data structure.

10)Base Register Addressing Mode: In this mode the contents of the base register is added to the address part of the instruction to obtain the EA. This is similar to indexed addressing mode except that the register now is called Base register instead of index register. The difference between the two modes is that the way they are used rather than in the way they are computed. An index register is assumed to hold an index number that is relative to the address part of the instruction. A base register is used to hold a base address and the address part of an instruction gives the displacement relative to this base address. USE: The base register addressing mode is used in the computer to facilitate the relocation of the program in memory. When program and data are moved from one segment of memory to another as required in the multiple program segments , the address value of the instruction must reflect this change of position , with a base register the displacement value of the instruction do not have to be changed. Only the value of the base register required to updating to reflect the beginning of new memory segment. Base register addressing mode is used to access the record type data structure.