Central processing organization

• CPU performs data processing operations in

computer. It consists 3 parts
• Register set: It stores intermediate data used during
execution of instruction.
• ALU: It performs the required micro operations for
executing the instructions.
• Control Unit: It supervises the transfer of information
among the register and instructs the ALU as to which
operation to perform.
Computer architecture is defines as computer structure
and behaviour which uses machine language instruction.
It includes
Instruction format
Addressing mode
Instruction Set
General organization of CPU register
Bus system organization
• A bus system consists
of a set of common
lines, one for each bit
of register through
which binary
information is
transferred at a time.
• The control signal will
determine the
register selected by
bus during each
specific register
transfer.
• The output of register is connected to two MUX to form two buses A and B.
• The selection lines in each MUX select one register.
• The A and B buses form the input to ALU.
• The operation selected in ALU determines the arithmetic and logic micro operation which
is to be performed.
• The result of micro operation is available for output data and also goes to inputs of all
register.
• The register which receives information from output bus is selected by decoder.
• The decoder activates one of the register load input and provides a transfer path between
the data in output bus & input of selected destination register.
• EXM: Perform R1=R2+R3
Control word
• There are 14 binary selection inputs and their combined value specifies
control word.
• It consists 4 fields.
• Three bits contains three bits each.
• One field has five bits.
• The three bits of SELA select a source register for A input of ALU.
• The three bits of SELB select a source register for B input of ALU.
• The SELD select a destination register using decoder and its seven load input.
• The five bits of OPR select one of the operation in ALU.
Types of CPU organization
• There are three types of CPU organization
1. Single accumulator organization: All operations are performed with an implied
accumulator register. The instruction format uses one address field.
2. General register organization: It employ two or three address field in
instruction format. Each address field specify a processor register or memory
word.
3. Stack organization: It supports two instruction PUSH and POP which requires
one address field.
ALU
• It provides arithmetic and logic operations.
• There are four different categories
• Register transfer micro operation: It transfers binary information from one
register to another.
• Shift micro operation: It performs shift operation in register for serial transfer of
data. During shift left, the serial input transfers a bit into rightmost position.
During right shift, the serial input transfers a bit into leftmost position. There are
3 types of shift operation such as
• Logical shift
• Circular shift
• Arithmetic shift
• Arithmetic micro operation: It performs arithmetic operation on numeric
data stored in register such as addition, subtraction, increment, decrement
and shift.
• Logic micro operation: It performs bit manipulation on non numeric data
stored in register such as AND, OR, XOR and compliment. Other logic micro
operations are as follows:
• Selective set
• Selective compliment
• Selective clear
• Mask
• Insert
• Clear
Types of address in computer Instruction

• Three address instruction

• Two address instruction
• One address instruction
• Zero address instruction
Three address instruction
• It use each address field to specify either a processor register or memory
operand.
• Advantage: It results short program when evaluating arithmetic expression.
• Disadvantage: It requires too many bits to specify three address.
• EXM: X=(A+B)*(C+D)
Two address instruction
• It is common in commercial computers.
• It use each address to specify either processor register or memory word.
• The MOV instruction transfers the operands to and from memory and
processor register.
• EXM: X=(A+B)*(C+D)
One address instruction
• It use implied accumulator register for all data manipulation.
• All operations are done between AC register and memory operand.
• T is the address of temporary memory location which stores the intermediate
result.
• EXM: X=(A+B)*(C+D)
Zero address instruction
• It use PUSH and POP instead address field to specify the operand that
communicates with stack.
• Stack is LIFO data structure.
• To evaluate arithmetic expression in stack computer, it is necessary to
convert the expression into polish notation.
• EXM: X=(A+B)*(C+D)
Addressing mode
• It specifies a rule for modifying the address field of instruction before the
operand is referenced.

• Opcode: It specifies the operation to be performed.

• Mode field: It is used to locate the operands needed for the operation.
• Address: It designate a memory address or processor register.
Types of addressing mode
• Implied mode
• Immediate mode
• Register mode
• Register indirect mode
• Auto-increment or auto-decrement mode
• Direct address mode
• Indirect address mode
• Relative address
• Index address mode
• Base address mode
Implied mode
• The operands are specified implicitly in definition of instruction.
• All register reference instructions which use accumulator are implied mode
instruction.
• Zero address instruction in stack computer is implied mode instruction.
Immediate mode
• It has an operand field rather that an address field.
• The operand field contains actual operand to be used in conjunction with
operation specified in instruction.
• It is useful for initializing register to a constant value.
• Zero address instruction in stack computer is immediate mode instruction.
Register mode
• In this, the operands are in register which reside within CPU.
• The particular register is selected from register field in instruction.
Register indirect mode
• The instruction specifies a register in CPU whose contents give the
address of operand in memory.
• Before using this, programmer must ensure that memory address of
operand is placed in processor register with previous instruction.
Auto-Increment or Auto-decrement mode
• It is similar to register indirect mode except the register is
incremented or decremented after its value is used to access
memory.
• Some computers incorporates a special mode that automatically
increments or decrements the content of register after data access.
Direct address mode
• In this, the effective address is equal to the address part of instruction.
• The operand resides in memory and its address is given directly by the
address field of instruction.
Indirect address mode
• The address field of instruction gives the address where effective
address is stored in memory.
• The effective address in this mode can be calculated as
EA=address part of instruction + content of CPU register.
Relative address mode
• The content of program counter is added to the address part of
instruction in order to obtain the effective address.
• The address part of instruction is a signed number which can positive
or negative.
Index addressing mode
• The content of an index register is added to the address part of
instruction to obtain the effective address.
• The index register is special CPU register which contains an index
value.
Base address mode
• The content of base register is added to the address part of
instruction to obtain the effective address.
• It is similar to indexed addressing mode except the register is called a
base register instead index register.
• The base register is special CPU register which contains an base value.
• This mode is used in computers to facilitate the relocation of
programs in memory.
Data Transfer and manipulation
• The most computer instructions can be categorized into 3 types
• Data transfer instruction: It cause transfer of data from one location to another
without changing the binary information content.
• Data manipulation instruction: It perform arithmetic, logic and shift operation.
• Program control instruction: It provide decision making capabilities and change
the path the program when executed in computer.
Data transfer instruction
• Load specifies data transfer from memory to
processor register.
• Store designates a transfer from processor
register to memory.
• Move designates a transfer from one register to
another. It is also for data transfer between two
memory word.
• Exchange swaps information between two
register or memory and memory word.
• Input and output transfer data among
processor register and I/O terminal.
• PUSH and POP transfer data between processor
register and memory stack.
Data manipulation instruction
• It is divided into three basic types
• Arithmetic instruction
• Logical and bit manipulation instruction
• Shift instruction
Arithmetic instruction
Logical and Bit manipulation instruction
Shift instruction
• In some computer, shift instruction has
multiple field format.

• OP: Operation code field

• REG: Register address which specifies the
location of operand
• TYPE: 2 bit field specifying four different
types of shift
• RL: 1 bit field specifying a shift left or right
• COUNT: k bit field specifying upto 2k-1 shift
Program control instruction
• Branch an Jump may be conditional or
unconditional. Unconditional branch causes a
branch to the specified address without any
condition. Conditional branch specifies condition
such as branch is positive or zero.
• Skip does not need any address field, so it is zero
address instruction.
• Call and Return are used in conjunction with
subroutines.
• The compare performs subtraction between the
Test performs logical AND of two operands and
updates certain status bits without retaining the
result or changing the operands.
Status bit condition
• Status bit is known as condition code
bit or flag bit.
• Diagram shows 8-bit ALU with 4-bit
status register.
• Four status bits are C (carry), S (sign),
Z (zero), V (overflow).
• Bit C is set to 1 if end carry C8 is 1. It
is 0 if the carry is 0.
• Bit S is set to 1 if the highest bit F7 is
1. It is 0 if the bit is 0.
• Bit Z is set to 1 if output is zero. Z is
set to 0 if output is not zero.
• Bit V is set to 1 if exclusive-OR of last
two carries is equal to 1 and cleared
to 0 otherwise.
Conditional branch instruction
Subroutine instruction
• Subroutine is self contained sequence of instruction which performs a
given computational task.
• The most common subroutine instructions are
• Call subroutine
• Jump to subroutine
• Branch to subroutine
• Branch and save address
• Return from subroutine
• Recursive subroutine
Program Interrupt
• It refers to the transfer of program control from a currently running program
to another service program.
• It is classified into 3 types
• External interrupt: It is initiated from Input output device, timing device,
circuit monitoring power supply or any other external source.
• Internal interrupt: It is initiated from illegal or erroneous use of an instruction
or data. It is also known as traps.
• Software interrupt: It is initiated by executing an instruction. It can be used
to initiate interrupt procedure at any point in the program.
Difference between Internal and External Interrupt

Internal External
• It is initiated by some exception • It is initiated by an external
condition caused by program. event.
• It is synchronous with program • It is asynchronous with program
• If program is rerun, the internal • It depends on external
interrupt will occur in same conditions that are independent
time. of program being executed at
the time.
Difference between interrupt and subroutine

Interrupt Subroutine call

• It is initiated by internal or • It is initiated by the execution of
external signal. an instruction.
• The address of interrupt service • The address of subroutine call is
program is determined by determined by address field of
hardware. an instruction.
• All information which defines • Only program counter contents
the state of CPU are stored. are stored
Microprocessor organization
• The computer hardware complexity could be organized by two
techniques
• CISC (Complex instruction set computer)
• RISC (Reduced instruction set computer)
CISC
• A computer with large number of instruction is called as CISC.
• EXM: IBM 370 computer
Characteristic:
1. A large number of instruction from 100 to 250
2. Some instruction which perform specialized task and are used
infrequently.
3. A large variety of addressing mode from 5 to 20
4. Variable length instruction format
5. Instruction which manipulate operands in memory
RISC
• It involves an attempt to reduce execution time by simplifying the instruction set of
computer.
• EXM: SuperH, Sparc
• Characteristic:

8. A relative larger number of register in processor unit

9. Use of overlapped register windows to speed-up procedure call and return
10. Efficient instruction pipeline
11. Compiler support for efficient translation of high level language programs into
machine language programs
Peripheral device
• Three types
• Input device: Any device used to enter information and instruction into
computer for storage or processing is said as input device.
• Exm: Keyboard, scanner, mouse, joystick, trackball, optical and magnetic
character reader, microphone, punched card, sensors etc
• Output device: Any device used to deliver the processed data to human
readable form is said as output device. It translates digitized signal.
• Exm: Laser printer, Loudspeaker, Plotter etc
• Input / Output device:
• Exm: Video terminal, modem and network interfaces
• Peripheral device may also be classified as analog and digital.
• It may also be classified as serial and parallel
Input output interface
• It provides a method for transferring information between internal storage
and external input output devices.
• Special hardware components are included in computer system between
CPU and peripheral to synchronize all input and output data transfer are
known as interface unit.
• Two types of interface
• CPU interface: It corresponds to system bus
• I/O interface: It depends input output device
I/O Bus and interface module
• I/O Bus consists
• Data lines
• Address lines
• Control lines
• Each interface decodes the address
and control received from I/O bus,
interprets them for peripheral and
provides signals for the peripheral
controller.
• It also synchronizes the data flow and
supervises the transfer between
peripheral and processor.
• Input output processor (IOP) or Data
channel provides an independent path
for transfer of data between external
device and internal memory.
I/O commands or function code
• It is an instruction that is executed in interface and its attached peripheral
device.
• Four types
• Control command: It is issued to activate the peripheral and to inform it what
to do.
• Status command: It is used to test different status condition in interface and
the peripheral.
• Data input command: It causes the interface to receive data from the
peripheral and place it in buffer register.
• Data output command: It causes the interface to respond by transferring data
from the bus into one of its register.
Isolated v/s Memory mapped I/O
Isolated I/O Memory mapped I/O
• I/O transfer is made through separate read and write • Memory transfer is made through separate read and
line. write lines.
• The I/O transfer read and write control lines are • The memory read and memory write control lines are
enabled during the i/o are enabled during a memory enabled during a memory transfer.
transfer.
• Computer with memory mapped i/o can use memory
• The isolated i/o configuration the CPU has distinct type instructions to access i/o data.
input and output instructions and each instruction is
• Any instruction which references to memory can be
associated with the address of an interface register.
used.
• Limited instructions can be used like IN, OUT, INS,
• Memory mapped I/O devices are treated as memory
OUTS.
locations on the memory map.
• The addresses for Isolated I/O devices are called
• Inefficient I/O operations due to using single bus for
ports.
data and addressing
• Efficient I/O operations due to using separate bus
• Smaller in size
• Comparatively larger in size
• Common internal logic for memory and I/O devices
• Uses complex internal logic
• Faster operations
• Slower operations
Asynchronous data transfer
• Data could be transferred in two different ways
• Parallel: Each bit of message has its own path and the entire message
is transferred simultaneously.
• Serial: Each bit in message is sent in a sequence one at a time.
• Serial transmission can be two types
• Synchronous: Data transfer among registers happen simultaneously
during the occurrence of clock pulse known as synchronous data
transfer.
• Asynchronous: When I/O and CPU are independent and use its own
clock for internal register known as Asynchronous data transfer.
• ADT can be done in two ways
• Use of strobe control
• handshaking
Strobe control
• A single control line transmits the strobe pulse for each time of data transfer
is initiated.
• It can be of two types
• Source initiated
• Destination initiated
• Disadvantages:
• The source cannot identify whether the destination has actually received the
data which was placed in bus or not.
• The destination cannot identify whether the source has actually sent the
data which was placed in bus or not
Source initiated
• Procedure:
• The source first places the data on data
bus.
• There is a delay to ensure that data settles
to a steady value.
• The source then activates the strobe pulse.
• The data on bus and strobe pulse remain in
active state for certain period of time.
• The destination uses the strobe pulse to
transfer the contents of data on bus into
one of its internal register.
• Then source then disables the strobe pulse.
• After some time, the source removes the
data from bus.
Destination initiated
• Procedure:
• The destination activates the strobe
pulse, informing the source to provide
the data.
• The source responds by placing the
requested data on bus.
• The data must be valid and available on
bus for certain time period.
• The destination register can be triggered
for strobe pulse.
• The destination then disables the strobe.
• The source removes the data from bus
after predetermined time period.
Handshaking
• During data transmission, source sends data with control signal which
indicates the presence of data in bus. When destination receiving the data
responds with another control signal to acknowledged receipt of data.
• Two types
• Source initiated
• Destination initiated

• Baud rate: It is the rate at which serial information is transmitted. It is

denoted as data transfer in bits per second.
Source initiated
• Procedure:
• The source initiates the data transfer
process by placing the data in bus and
enabling its data valid signal.
• The data from bus is accepted by
destination
• The destination then activates its data
accepted signal.
• The source then disables its data valid
signal which removes the data in bus.
• The destination then disables its data
accepted signal and shows that it is
ready to accept the new data.
• The system then goes to its initial state.
Destination initiated
• Procedure:
• When destination is ready to accept
the data, it sends control signal ready
for data to source to send the data.
• The source then place the data in bus
and sends the control signal data
valid to destination unit.
• The destination accepts data from
bus then disables the ready for data
signal.
• The source then disables data valid
signal.
• Then source invalidates the data on
data bus.
• Then system goes to its initial state.
Mode of transfer
• The data transfer to and from peripherals may be handled three ways

• Programmed I/O
• Interrupt initiated I/O
• DMA
Programmed I/O
• I/O device does not have direct access to memory.
• When data is available, the device place it in I/O bus and enables its data valid line.
• The interface accepts the data into its data register and enables the data accepted line.
• The device disables the data valid line but it will not transfer another data until the data
accepted line is disabled by interface.
• It is useful in slow low speed computers.
• It is an inefficient data transfer technique because of the difference in data transfer rate
between CPU and I/O.
Flowchart for CPU program to input data

• A program checks the flag in status

register to determine if the data has
been placed in data register by I/O
device. It also place the content into
CPU register and checks the flag bit.
• If flag bit is 1, then CPU reads the data
from data register using I/O read. Then
the CPU transfers the data to memory
using I/O write.
• Then flag bit is cleared to 0 either by
CPU or Interface.
• Once flag is cleared, the interface
disable the data accepted line and
device can send the next data.
Interrupt initiated I/O
• In this, computer does not check the flag. It continues to perform its task.
• Whenever any peripheral wants to communicate, it sends the interrupt signal
to CPU.
• CPU then responds to that interrupt, store the return address and branch to
the address of the subroutine.
• There are two ways of choosing the branch address:
• Vectored Interrupt
• Non-vectored Interrupt
• In vectored interrupt, the source that interrupt the CPU provides the branch
information. This information is called interrupt vectored.
• In non-vectored interrupt, the branch address is assigned to the fixed address
in the memory.
Priority Interrupt
• There are number of IO devices attached to the computer.
• They are all capable of generating the interrupt.
• When the interrupt is generated from more than one device, priority
interrupt system is used to determine which device is to be serviced first.
• Devices with high speed transfer are given higher priority and slow devices
are given lower priority.
• Establishing the priority can be done in two ways:
• Using Software
• Using Hardware
Using software or Polling

•A pooling procedure is used to identify highest priority.

•There is one common branch address for all interrupts.
•Branch address contain code to poll the interrupt sources in
sequence. The highest priority is tested and served.
•The disadvantage is that time required to poll them can exceed the
time to serve them in large number of IO devices.
Using Hardware

• Hardware priority system function as an overall manager.

• It accepts interrupt request and determine the priorities.
• To speed up the operation each interrupting devices has its own interrupt
vector.
• No polling is required, all decision are established by hardware priority
interrupt unit.
• It can be established by serial or parallel interrupt lines.
Serial or Daisy Chaining
Priority
• Device with highest priority is placed
first.
• Device that wants to communicate,
sends the interrupt request to the
CPU.
• CPU then sends the INTACK signal
which is applied to PI(priority in) of
the first device.
• If it has requested, it places its
VAD(vector address) on the bus. And
it block the signal by placing 0 in
PO(priority out)
• If not it pass the signal to next device
through PO(priority out) by placing 1.
• This process is continued until
appropriate device is found.
• The device whose PI is 1 and PO is 0 is
the device that send the interrupt
request.
Parallel Priority Interrupt
• It consist of interrupt register whose bits are set separately by the interrupting
devices.
• Priority is established according to the position of the bits in the register.
• Mask register is used to provide facility for the higher priority devices to interrupt
when lower priority device is being serviced or disable all lower priority devices
when higher is being serviced.
• Corresponding interrupt bit and mask bit are performed AND operation and
applied to priority encoder.
• Priority encoder generates two bits of vector address.
• Another output from it sets IST(interrupt status flip flop).
Priority Encoder:
Priority encoder is a circuit that implements the priority function.
If two or more inputs arrive at the same time, the input having highest
priority will take precedence.
DMA (Direct memory Access)
• DMA controller uses different bus and transfer the data directly between I/O
devices and memory.
• The buses can be disable by using two special control signal
• BR: When BR is active, the CPU terminates the current execution, place the
address bus and data bus, and activates the read and write lines.
• BG: CPU activates BG output to transfer the data between I/O device and
memory.
• DMA Transfer can be perform in two ways:
• Burst Transfer
• Cycle Stealing
• In burst transfer, a number of memory word is transfer in a
continuous burst. It is required for fast device such as magnetic disk.
• In cycle stealing, one data word is transfer at a time.
DMA Controller
• It communicates with CPU through data bus and control lines.
• DMA communicates with I/O device through request and acknowledge lines by using
handshaking procedure.
• It has three registers: Address register, Word count register and control register.
• Address register contain address which specify the location of memory to read or write.
• Word count register holds the number of words to be transferred.
• Control Register specify the mode of transfer.
• When CPU wants to select register in DMA controller, it does through address bus by enabling
DS and RS inputs
• When BG=0 CPU communicates with DMA register for read or write operation.
• When BG=1 DMA communicates directly with the memory.
• DMA first initializes by CPU and continues to transfer data.
• CPU initialize the DMA by sending the following information through the data bus:
• Starting address of memory block for read or write.
• The word count or number of words to read or write.
• Control to specify mode such as read or write.
• Control to start DMA
• Once DMA is initialized, CPU stops communicating with DMA only when it receives interrupt
signal or if it wants to check how many words has been transferred.
DMA Transfer
• First I/O device sends a DMA request.
• DMA controller activates BR line informing CPU to disable the buses.
• The CPU responds with its BG informing DMA that its buses are disabled.
• The DMA then puts current address register value into address bus, initiates RD or WR signals,
sends DMA acknowledge to I/O device.
• When I/O device receives acknowledge, it puts a word in data bus for write and receives a word
from data bus for read.
• For each word which is transferred, the DMA increments its address register and decrements its
word count register.
• If word count does not reach zero, DMA checks the request line coming from I/O.
• The data transfer process continues until entire block is transferred.
• If I/O device speed is slower, the DMA disables the BR line.
• When word count register reaches zero, the DMA stops any further transfer and removes its
BR.
• If there is an interrupt, CPU is informed about termination of process.
• When CPU responds to interrupt, it reads the content of word count register.
• When content of word count register is zero, it indicates data transfer is successful.
Input output processor (IOP)
• It is classified as a processor with
direct memory access capability
which communicates with I/O
devices.
• In this, computer consists memory
unit, CPU and number of IOP.
• It fetch and execute its own
instruction.
• IOP instructions are specially
designed to facilitate I/O transfer.
• It also performs other tasks like
arithmetic, logic and branching.
• CPU is master and IOP is a slave
processor.
• The instruction that are read from
memory by IOP known as command.
CPU-IOP communication
• The CPU send an instruction to test the IOP path.
• The IOP path responds by inserting a status word in memory which
indicates the condition of IOP and I/O device such as
1. IOP overload condition
2. Device busy with another transfer
3. Device ready for I/O transfer
• If everything is OK, CPU sends the instruction to start I/O transfer
• The IOP access the memory for IOP program and CPU continues
with another program.
• The IOP conducts I/O transfers using DMA and prepares the status
report.
• When I/O transfer is completed, IOP terminates the execution of its
program and sends an interrupt request to CPU.
• The CPU responds to interrupt by issuing instruction to read status
from IOP.
• Then IOP responds by placing the content of its status report into
specified memory. The status report indicates whether transfer has
been completed or any error occurred.
• By seeing the status word, the CPU determines whether the I/O
operation is completed without error or not.