‘The SAP (Simple-As-Possible) computer has been designed for you, the beginner. The main purpose of SAP is to introduce all the crucial ideas behind computer operation without burying you in unnecessary detail. But even a simple computer like SAP covers many advanced concepts To avoid bombarding you with too much all at once, we will examine three different generations of the SAP com- puter. 'SAP-1 is the first stage in the evolution toward modern computers. Although primitive, SAP-1 is a big step for a beginner. So, dig into this chapter, master SAP-1, its architecture, its programming, and its circuits. Then you will be ready for SAP-2 10-1 ARCHITECTURE Figure 10-1 shows the architecture (structure) of SAP-1, a bus-organized computer. All register outputs fo the W bus are three-state; this allows orderly transfer of data. Al other register outputs are two-state; these outputs continuously drive the boxes they are connected to, ‘The layout of Fig. 10-1 emphasizes the registers used in SAP-L. For this reason, no attempt has been made to keep all control circuits in one block called the control unit, all input-output circuits in another block called the VO unit, etc Many of the registers of Fig. 10-1 are already familiar from earlier examples and discussions, What follows is brief description of each box; detailed explanations come later. Program Counter The program is stored at the beginning of the memory with the first instruction at binary address 0000, the second instruction at address 0001, the third at address 0010, and so on. The program counter, which is part of the control unit, counts from 0000 to LILL. Its jab is to send to the ‘memory the address of the next instruction to be fetched and executed. It does this as follows 140 ‘The program counters reset to 0000 before each computer run, When the computer run begins, the program counter sends address 0000 to the memory. The program counter is then incremented to get 0001. After the first instruction is fetched and executed, the program counter sends address (0001 to the memory. Again the program counter is inere- ‘mented. A iter the second instruction i fetched and executed, the program counter sends address 0010 to the memory. In this way, the program counter is keeping track of the next instruction to be fetched and executed The program counter is like someone pointing a finger ata list of instructions, saying do this first, do this second, do this third, etc. This is why the program counter is sometimes called a pointer; it points to an address in memory where something important is being stored. Input and MAR Below the program counter is the input and MAR block. It includes the address and data switch registers discussed in Sec, 9-4, These switch registers, which are part of the input unit, allow you to send 4 address bits and 8 data bits to the RAM. As you recall, instruction and data words ane written into the RAM before a computer run. ‘The memory address register (MAR) is part of the SAP- 1 memory. During a computer run, the address in the program counter is latched into the MAR. A bit later, the MAR applies this 4-bit address to the RAM, where a read ‘operation is performed. ‘The RAM The RAM isa 16 x 8 static TTL RAM. As discussed in Sec. 9-4, you can program the RAM by means of the address and data switch registers. This allows you to store ‘program and data in the memory before a computer run ‘During a computer run, the RAM receives 4-bit addresses fromthe MAR and read operation is performed. In this way. the instruction of data word stored in the RAM is placed fon the W bus for use in some other part of the computer.ax—h tan - Acar am —| 2 - v CuK pa s saber ws LE : sat coi ceux —p ee” 2 oom j— cK cart — | f- 4 TU Wy y —~ cin Corin ELE AEs Sully 1041 SAP architecture Instruction Register ‘The instruction register is part of the control unit. To fetch an instruction from the memory the computer does a memory read operation. This places the contents of the addressed ‘memory location on the W bus. At the same time, the instruction register is set up for loading on the next positive clock edge. ‘The contents of the instruction register are split into two nibbles. The upper nibble is a two-state output that goes directly to the block labeled ““Controlier-sequencer.”” The lower nibble is a three-state output that is read onto the W bus when needed. Controller-Sequencer ‘The lower left block contains the controller-sequencer Before each computer run, a CLR signal is sent to the program counter and a CLR signal tothe instruction register. ‘This resets the program counter to 0000 and wipes out the last instruction in the instruction register. ‘A clock signal CLK is sent to all buffer registers; this synchronizes the operation of the computer, ensuring that things happen when they are supposed to happen. In other words, all register transfers occur on the positive edge of 4 common CLK signal. Notice that a CER signal also goes to the program counter. ‘The 12 bits that come out of the controller-sequencer form a word controlling the rest of the computer (like a supervisor telling others what to do.) The 12 wires carrying the control word are called the control bus. ‘The control word has the format of CON = CyBDyCE TELE, SuBuLpho. This word determines how the registers will react to the next positive CLK edge. For instance, a high E> and a low Chapter 10 sap-1 141Ty mean thatthe contents of the program counter are latched into the MAR on the next positive clock edge. As another example, a low CE and a low Ly mean that the addressed RAM word will be transferred to the accumulator on the next positive clock edge. Later, we will examine the timing diagrams to see exactly when and how these data transfers take place. Accumulator ‘The accumulator (A) is a buffer register that stores inter- mediate answers during a computer run. In Fig. 10-1 the accumulator has two outputs. The two-state output gors directly (0 the adder-subtracter. The three-state output goes to the W bus. Therefore, the 8:bit accumulator word continuously drives the adder-subtracter; the same word appears on the W bus when E, is high. ‘The Adder-Subtracter SAP-1 uses a 2's-complement adder-subtracter. When Si is low in Fig. 10-1, the sum out of the adder-subtracter is S=A+B When S, is high, the difference appears A=AGB (Recall that the 2's complement is equivalent to a decimal sign change.) The adder-subtracter is asynchronous (unclocked); this ‘means that its contents can change as soon as the input words change. When Ey is high, these contents appear on the W bus. B Register The B register is another butter repister. It is used in arithmetic operations, low Zy and positive clock edge load the word on the W bus into the B register. The wo state output of the B register drives the adder-subtrater, supplying the number to be added or subtracted from the contents of the accumulator Output Register Example 8+ discussed the output register. At the end of computer run, the accumulator contains the answer to the problem being solved. At this point, we need to transfer the answer tothe outside world, This is where the ouput resister is used. When Ey is high and Ly is low, the next positive clock edge Toads the accumulator word into the output register. The ouipat register is often called an output port because processed data can leave the computer through this register 142 digital computer Electronics In microcomputers the output ports are connected to inter: face circuits that drive peripheral devices like printers, ccathode-ray tubes, teletypewriters, and so forth. (Am inter- face circuit prepares the data to drive each device.) Binary Display ‘The binary display is a row of cight light-emitting diodes (LEDs), Because each LED connects to one flip-flop of the ‘output por, the binary display shows us the contents of the ‘output port. Therefore, alter we've transferred an answer from the accumulator to the output port, we can see the answer in binary form. ‘Summary ‘The SAP-1 control unit consists of the program counter, the instruction register, and the controller-sequencer that produces the control word, the clear signals, and the clock signals. The SAP-1 ALU consists of an accumulator, an adder-subtracter, and a B register. The SAP-I memory has the MAR and a 16 x 8 RAM. The I/O unit includes the input programming switches, the output port, and the binary display. 10-2 INSTRUCTION SET A computer is a useless pile of hardware until someone programs it. This means loading step-by-step instructions into the memory before the start of a computer run. Before ‘you can program a computer, however, you must learn its instruction set, the basic operations it can perform. The 'SAP-1 instruction set follows. LDA ‘As described in Chap. 9, the words in the memory ean be symbolized by Ry, R,, Bz, etc. This means that Ry is stored at address OH, Ry at address 1H, Ry at address 2H, and so LDA stands for “load the accumulator."” A complete LDA instruction includes the hexadecimal address of the data to be loaded. LDA 8H, for example, means “load the accumulator with the contents of memory location SH.” Therefore, given Ry = 1111 0000 the execution of LDA 8H results in = 1111 0000 ‘Similarly, LDA AH means ‘load the accumulator with the contents of memory location AH," LDA FH means “load the accumulator with the contents of memory location FHL" and so on,ADD ADD js another SAP-I instruction. A complete ADD instruction includes the address of the word to be added For instance, ADD 9H means “add the contents of memory location 9H to the accumulator contents”; the sum replaces the original contents of the accumulator. Here's an example. Suppose decimal 2 is in the accu: ‘mulator and decimal 3 is in memory location 9H, Then A = 00000010 Ry = 00000011 During the execution of ADD 9H, the following things hhappen. First, Ry is loaded into the B register to get B= 0000 0011 and almost instantly the adder-subtracter forms the sum of Aand B SUM= 0000 0101 Second, this sum is loaded into the accumulator 10 get ‘A = 9000 0101 The foregoing routine is used for all ADD instructions the addressed RAM word goes to the B register and the adder-subtracter output to the accumulator. This is why the execution of ADD 9H adds R, to the accumulator contents, the execution of ADD FH adds R- to the accumulator contents, and so on, SUB SUB js another SAP-1 instruction. A complete SUB in- struction includes the address of the word to be subtracted, For example, SUB CH means “subtract the contents of ‘memory location CH from the contents of the accumulator" the difference out of the adder-subtracter then replaces the original contents of the accumulator, For a concrete example, assume that decimal 7 is in the accumulator and decimal 3 is in memory location CH. Then ‘The execution of SUB CH takes place as follows. First, Re is loaded into the B register to get B 0000 0011 and almost instantly the adder-subtracter forms the differ- ence of A and B: DIFF = 0000 0100 Second, this difference is loaded into the accumulator and A = 0000 0100 ‘The foregoing routine applies to all SUB instructions; the addressed RAM word goes to the B register and the adder-subtracter output to the accumulator. This is why the execution of SUB CH subtracts Re from the contents of the accumulator, the execution of SUB EH subtracts Ry from the accumulator, and so on, our The instruction OUT tells the SAP-1 computer to transfer the accumulator contents to the output port. After OUT has been executed, you can see the answer to the problem being solved. OUT is complete by itself; that is, you do not have to include an address when using OUT because the instruction does not involve data in the memory. HLT HLT stands for halt, This instruction tells the computer to stop processing data. HLT marks the end of a program, similar to the way a period marks the end of a sentence. ‘You must use a HLT instruction at the end of every SAP- 1 program; otherwise, you get computer trash (meaningless answers caused by runaway processing). HLT is complete by itself; you do not have to inelude a RAM word when using HLT because this instruction does ‘not involve the memory. Memory-Reference Instructions LDA, ADD, and SUB are called memory-reference instruc- tions because they use data stored in the memory. OUT and HLT, on the other hand, are not memory-reference instructions because they do not involve data stored in the memory Mnemonics LDA, ADD, SUB, OUT, and HLT are the instruction set for SAP-1, Abbreviated instructions like these are called ‘mnemonics (memory aids). Mnemonics are popular in computer work because they remind you of the operation ‘that will take place when the instruction is executed, Table 10-1 summarizes the SAP-1 instruction set ‘The 8080 and 8085 ‘The 8080 was the first widely used microprocessor. It has ‘72 instructions. The 8085 is an enhanced version of the 8080 with essentially the same instruction set, To make SAP practical, the SAP instructions will be upward com- Chapter 10 saps 143‘TABLE 10-1. SAP-1 INSTRUCTION SET Mnemonic Operation LDA Load RAM data into accumulator ADD Add RAM data to accumulator SUB Subtract RAM data from accumulator OUT Load accumulator data into output register HLT __ Stop processing patible with the 8080/8085 instruction set. In other words, the SAP-I instructions LDA, ADD, SUB, OUT, and HLT are 8080/8085 instructions. Likewise, the SAP-2 and SAP- 3 instructions will be part of the 8080/8085 instruction set Learning SAP instructions is getting you ready for the 8080 and 8085, two widely used microprocessors. EXAMPLE 10-1 Here's a SAP-I program in mnemonic form: Address Mnemonics oH LDA 9H 1H ADD AH, 2H ADD BH 3H SUB CH 4H ouT SH HLT ‘The data in higher memory is Address Data oH FFH 7H FFH SH FFH oH on AN on BH O3H cH oan DH FFH EH FFH FH FEH ‘What does each instruction do? SOLUTION The program is in the low memory, located at addresses OH to SH. ‘The first instruction loads the accumulator with 144 digitat Computer Electronics the contents of memory location 9H, and so the accumulator ‘contents become A= 01H “The second instruction adds the contents of memory location AH to the accumulator contents to get a new accumulator total of A = 01H + 02H = 03H Similarly, the third instruction add the contents of memory location BH A = 03H + 03H = 06H The SUB instruction subtracts the contents of memory location CH to get A = 06H — 04H = 02H The OUT instruction loads the accumulator contents into the output port: therefore, the binary display shows (0000 0010 ‘The HILT instruction stops the data processing, 10-3 PROGRAMMING SAP-1 To load instruction and data words into the SAP-1 memory we have to use some kind of code that the computer can interpret. Table 10-2 shows the code used in SAP-1, The ‘number 0000 stands for LDA, 0001 for ADD, 0010 for SUB, 1110 for OUT, and 1111 for HLT. Because this code tells the computer which operation to perform, itis called ‘an operation code (op code). AAs discussed earlier, the address and data switches of Fig. 9-7 allow you to program the SAP-1 memory. By design, these switches produce a 1 in the up position (U) TABLE 10-2. SAP-1 OP CODE Mnemonic Op code LDA 0000 ADD 0001 SUB 010 our 1110 HLT ninand a 0 in the down position (D). When programming the data switches with an instruction, the op code goes into the upper nibble, and the operand (the rest of the instruction) into the lower nibble. For instance, suppose we want to store the following instructions: Address Instruction OH = LDAFH 1H ADDEH 2H HLT First, convert cach instruction to binary as follows: LDA FH = 0000 1111 ADD EH = 0001 1110 HLT = 1111 XXXX In the first instruction, 0000 is the op code for LDA, and 1111 is the binary equivalent of FH. In the second instruc- tion, 0001 is the op code for ADD, and 1110 is the binary equivalent of EH. In the third instruction, 1111 is the op code for HLT, and XXXX are don’t cares because the HLT is not a memory-reference instruction, Next, set up the address and data switches as follows: Address Data DppD PPD UUUU DbpU popu LUUD DDUD — UUUUXXXX ‘After each address and data word is set, you press the write button. Since D stores a binary O and U stores a binary 1, the first three memory locations now have these contents Address Contents 0000 0000 1111 oor 0001 1110 010 ILL XXX ‘A final point, Assembly language involves working with mnemonics when writing a program. Machine language involves working with strings of Os and 1s, The following examples bring out the distinction between the two lan- guages. EXAMPLE 10-2 Translate the program of Example 10-1 into SAP-1 machine language. SOLUTION Here is the program of Example 10-1: Address Instruction. oH LDA oH 1H ADD AH 2H ADD BH 3H SUB CH 4H our si HLT ‘This program is in assembly language as it now stands. To get it into machine language, we translate it to Os and 1s as follows: Address Instruction 0000 (0000 1001 001 0001 1010 oo10 0001 1011 001 0010 1100 100 1110 XXXX, ono TIL XXXX, Now the program is in machine language Any program like the foregoing that's written in machine language is called an object program. The original program with mnemonics is called a source program. In SAP-1 the ‘operator translates the source program into an object program when programming the address and data switches. A final point. The four MSBs of a SAP-1 machine- language instruction specify the operation, and the four LSBs give the address. Sometimes we refer to the MSBs as the instruction field and to the LSBs as the address field. Symbolically Instruction = XXXX XXXX TF Instruction field! Address field EXAMPLE 10-3 How would you program SAP-1 to solve this arithmetic problem? 16 + 20 +24 ~ 32 ‘The numbers are in decimal form. SOLUTION One way is t0 use the program of the preceding example, storing the data (16, 20, 24, 32) in memory locations 9H Chapter 10 sap-1 145fo CH. With Appendix 2, you can convert the decimal data into hexadecimal data to get this assembly-language version: Address Contents oH LDA 9H 1H ADD AH 2H ADD BH 3H. SUB CH 4H ouT SH HLT oH XX 7H XX 3H XX oH 10H AH 1H BH 18H cH 20H The machine-language version is Address Contents (0000 (0000 1001 001 0001 1010 010 0001 1011 ool (0010 1100 0100 L110 XXXX o1ol LIL XXXXx 110 XXXX XXXX, out XXXX XXXX 1000 XXXX XXXX 1001 ‘9001 0000 1010 0001 0100 1011 0001 1000 1100 0010-0000 Notice that the program is stored ahead of the data. In other words, the program is in low memory and the data in high memory. This is essential in SAP-1 because the program counter points to address 0000 forthe first instruc- tion, 0001 for the second instruction, and so forth. EXAMPLE 10-4 Chunk the program and data of the preceding example by converting to hexadecimal shorthand, SOLUTION Address Contents oH 09H 1H 1AH 2H IBH 146 Digital Computer Electronics 3H 2cH 4H EXH SH XH oH XXH_ TH XXH SH XXH oH 10H AH 14H BH 18H cH 20H ‘This version of the program and data is still considered ‘machine language. Incidentally, negative data is loaded in 2's-complement form. For example, —03H is entered as FDH. 10-4 FETCH CYCLE ‘The control unit is the key to a computer’s automatic ‘operation, The control unit generates the control words that fetch and execute each instruction, While each instruction is fetched and executed, the computer passes through different timing states (T° states), periods during which register contents change. Let's find out more about these T. states, Ring Counter Earlier, we discussed the SAP-1 ring counter (see Fig 8-16 for the schematic diagram). Figure 10-2a symbolizes the ring counter, which has an output of T= TITTY, ‘Ac the beginning of a computer run, the ring word is T = 000001 Successive clock pulses produce ring words of T T T = 001000 T = 010000 T = 100000 ‘Then, the ring counter resets to 000001, and the cycle repeats. Each ring word represents one T' state Figure 10-2b shows the timing pulses out of the ring counter. The initial state T, starts with a negative clock edge and ends with the next negative clock edge, During this T state, the 7; bit out of the ring counter is high, During the next state, Tis high; the following state has a high 7s; then a high Ty; and so on, As you can see, theD— ck a CLR cur | bitiebiichiachtatsitlechlicd x t * Fig, 10-2 Ring counter: (a) symbol (b) clock and timing signals ring counter produces six states. Each instruction is fetched and executed during these six T states. Notice that a positive CLK edge occurs midway through each T state. The importance of this will be brought out later. Address State The T, state is called the address state because the address in the program counter (PC) is transferred to the memory address register (MAR) during this state. Figure 10-34 shows the computer sections that are active during this state (active parts are light; inactive parts are dark). During the address state, E, and Ly are active; all other control bits are inactive. This means that the controller- sequencer is sending out a control word of CON = CyE,LyCE =0101 SpE Lalo ool LEL4E rito during this state 1 Increment State Figure 10-36 shows the active parts of SAP-I during the T, state. This state is called the increment state because the program counter is incremented. During the increment state, the controller-sequencer is producing a control word of GE DyCE GEL, =lotd dr CON Spb ool caEs To As you see, the C, bit is active. Memory State ‘The T tae called the memory state because the addressed RAM instruction is transferred from the memory to the instruction register. Figure 10-3c shows the active parts of SAP-1 during the memory state. The only active control bits during ths state are CE and Z,, and the word out of the contollr-sequencer is CON = C)BpDyCE Ty i) EC,E, SuE Lalo 110 0011 Chapter 10 sap1 147= eke con TW ‘con a Fig, 10-3 Fetch cycle: (a) 7 state; (b) T; state: (e) T state Fetch Cycle The address, increment, and memory states are called the {fetch eyele of SAP-1. During the address state, Ep und Ly ‘are active; this means that the program counter sets up the MAR via the W bus. As shown earlier in Fig. 10-25, a positive clock edge occurs midway through the address state; this loads the MAR with the contents of the PC. Cp is the only active control bit during the increment state, This sets up the program counter to count positive clock edges, Halfway through the increment state, 2 postive clock edge hits the program counter and advances the count byl During the memory state, CE and Z, are active, Therefore, the addressed RAM word sets up the instruction register via the W bus. Midway through the memory state, a positive clock edge loads the instruction register with the addressed RAM word, 10-5 EXECUTION CYCLE The next three states (Ty, Ts, and T,) ate the execution cycle of SAP-1. The register transfers during the execution cycle depend on the particular instruction being executed For instance, LDA 9H requires different register transfers than ADD BH. What follows are the control routines for different SAP-1 instructions, LDA Routine For a conerete discussion, let’s assume that the instruction register has been loaded with LDA 911 IR = 0000 1001 During the 7, state, the instruction field 0000 goes to the controller-sequencer, where it is decoded; the address field 1001 is loaded into the MAR. Figure 10-4a shows the 148 Digital Computer Electronics active parts of SAP-1 during the 7, state, Note that Band Taare active; all other control bits are inactive. During the T, state, CE and Z, go low. This means that the addressed data word in the RAM will be loaded into the accumulator on the next positive clock edge (see Fi, 10-40). 7, is a no-operation state. During this tind execution state, all egisers are inactive (Fig. 10-4c). This means that the controtler-sequencer is sending out a word whose bits are all inactive. Nop (pronounced no op) stands for “no operation.” The T, state of the LDA routine isa nop. Figure 10-5 shows the timing diagram forthe fetch and LDA routines, During the T; state, Ep and Ly are active: the positive clock edge midway through this state will transfer the address in the program counter to the MAR. During the T; state, Cis active and the program counter is incremented on the positive clock edge. During the Ts state, CE and L, are active; when the postive clock edge occurs, the addressed RAM word is tansferred to the instruction register. The LDA execution starts with the Ty, state, where Ly and E; are active: on the positive clock, cede the adress fel in the instruction register is transferred to the MAR. During the 7, state, CE and Ly are active; this means thatthe addressed RAM data word is transferred to the accumulator on the positive clock edge. As you know, the T, state of the LDA routine is a nop. ADD Routine Suppose at the end of the fetch cycle the instruction register contains ADD BH. IR = 0001 1011 During the 7, stat the instruction field goes to the controller- sequencer and the address field to the MAR (see Fig. 10-6a). During this state E, and Ly are active. Control bits CE and Ly are active during the Ts state ‘This allows the addressed RAM word to set up the B©: (a) T, state; (b)T; state; (c)T, state a cox Fig. 10-5 Fetch and LDA timing diagram, He peal re: Lf SH =a 1 eS w con 9) T. con a Fig. 10-6 ADD and SUB routines: (a) 7, sate; (b) Ts state: (e) T, sate fo Chapter 10 SAP-1 149register (Fig. 10-65). As usual, loading takes place midway through the state when the positive clock edge hits the CLK input of the B register During the Ts state, By and Z, ate actives therefore, the fadder-subtracter sets up the accumulator (Fig. 10-6c) Halfway through this state, the positive clock edge loads the sum into the accumulator. Incidentally, setup time and propagation delay time prevent racing of the accumulator during this final execution state, When the positive clock edge hits in Fig. 10-6c, the accumulator contents change, forcing the adder-subtracter contents t0 change. The new contents return to the accu- ‘mutator input, but the new contents don’t get there until two propagation delays alter the positive clock edge (one for the accumulator and one for the adder-subtracter). By then it's too late to set up the accumulator. This prevents ‘accumulator racing (loading more than once on the same clock edge). Figure 10-7 shows the timing diagram for the fetch and ADD routines. The fetch routine is the same as before: the TT, state loads the PC address into the MAR; the T) state increments the program counter; the T; state sends the addressed instruction to the instruction register. During the 7, state, E,and Ty are active; on the next positive clock edge, the’ address field in the instruction register goes to the MAR. During the T, state, CE and Ly tne active therefore, the addressed RAM word is loaded into the B register midway through the sate. During th Te state, E,, and L, are active; when the positive clock edge hits the sum out of the adder-subtracter is stored inthe accumulator SUB Routine ‘The SUB routine is similar to the ADD routine. Figure 10-6a and b show the active parts of SAP-1 during the T, and T, states. During the 7, state, a high Sy is sent to the adder-subtracter of Fig. 10-6c. The timing diagram is almost identical to Fig, 10-7. Visualize Sy low during the 7, to T, states and Sy high during the T, state OUT Routine ‘Suppose the instruction register contains the OUT instruction at the end of a fetch cycle. Then IR = 1110 XXXX Jenctlenebenatereaten teri] The imsrcion fel ges 10 the consoller sequencer for Bene Then ie Somaursequnet sen othe LI @ Ly Po z iy} ' I £y ' I i ! Fig. 10-9 Fetch and OUT timing diagram. HLT HLT does not require a control routine because no registers are involved in the execution of an HLT instruction. When the IR contains the instruction field 1111 signals the controller-sequencer to stop processing data. The controller-sequencer stops the ‘computer by turning off the clock (circuitry discussed later), Machine Cycle and Instruction Cycle SAP-I has six T states (three fetch and three execute). These six states are called a machine cycle (sce Fig. 10-10a). It takes one machine eycle (o fetch and execute each instruction. The SAP-I clock has a frequency of 1 KHz, equivalent to a period of I ms. Therefore, it takes 6 mis for a SAP-I machine cycle. SAP-2is slightly different because some of its instructions take more than one machine cycle to fetch and execute. Figure 10-10b shows the timing for an instruction that requires two machine cycles. The frst three T states are the fetch cycle; however, the execution cycle requires the next nine T states. This is because a two-machine-cycle instruction is more complicated and needs those extra T states to complete the execution, ‘The number of T states needed to fetch and execute an instruction is called the instruction cycle. In SAP-1 the instruction cycle equals the machine cycle. In SAP-2 and other microcomputers the instruction cycle may equal two (or more machine cycles, as shown in Fig, 10-106, ‘The instruction cycles for the 8080 and 8085 take from ‘one to five machine cycles (more on this later) EXAMPLE 10-5 ‘The 8080/8085. progean ing manual says that it takes IR = ILL Xxx thirteen T states to fetch and execute the LDA instruction, cu nlalalnlnln J Fetch af Execute a % nln nln ninun|n| Fig. 10-10 (a) SAP-1 instruction cycle; (D) instruction eyele with two michine cycles, Chapter 10 sap1 151If the system clock has a frequency of 2.5 MHz, how long is an instruction cycle? SOLUTION ‘The period of the clock is 1 “25 MHz 400s f Therefore, each T state lasts 400 ns. Since it takes thirteen T states to fetch and execute the LDA instruction, the instruction cycle lasts for 13 x 400 ns = 5,200 ns = 5.2 ps EXAMPLE 10-6 Figure 10-11 shows the six T states of SAP-1. The positive clock edge occurs halfway through each state. Why is this important? SOLUTION SAP-L is a bus-organized computer (the common type nowadays), This allows its registers to communicate via the W bus. But reliable loading of a register takes place ‘only when the setup and hold times are satisfied. Waiting half a cycle before loading the register satisfies the setup time; waiting half a cycle after loading satisfies the hold time. This is why the positive clock edge is designed to strike the registers halfway through each T state (Fig, 10-11). ‘There's another reason for waiting half a eycle before loading a register. When the ENABLE input of the sending register goes active, the contents of this register are suddenly dumped on the W bus. Stray capacitance and lead inductance prevent the bus lines from reaching their correct voltage levels immediately. In other words, we get transients on the W bus and have to wait for them to die out to ensure valid data at the time of loading. ‘The hatf-cycle delay before clocking allows the data to setle before loading, 1 4 10-6 THE SAP-1 MICROPROGRAM We will soon be analyzing the schematic diagram of the SAP-I computer, but first we need to summarize the execution of SAP-1 instructions in a neat table called a mmicroprogram Microinstructions The controller-sequencer sends out control words, one during each T state of clock cycle. These words are like ditections telling the rest of the computer what to do, Because it produces a small step in the data processing, each control word is called a microinstruction. When looking at the SAP-I block diagram (Fig, 10-1), we can visualize a steady stream of microinstructions flowing out of the controller-sequencer to the other SAP-I circuits Macroinstructions The instructions we have been programming with (LDA, ADD, SUB, . ..) are sometimes called macroinstructions to distinguish them from microinstructions. Each SAP-1 ‘macroinstruction is made up of three microinstructions. For example, the LDA macroinstruction consists of the mi- croinstructions in Table 10-3. To simplify the appearance ‘of these microinstructions, we can use hexadecimal chunk- ing as shown in Table 10-4. Table 10-5 shows the SAP-I microprogram, a listing of ‘each macroinstruction and the microinstructions needed to carry it out. This table summarizes the execute routines for the SAP-1 instructions. A similar table can be used with more advanced instruction sets. 10-7 THE SAP-1 SCHEMATIC DIAGRAM In this section we examine the complete schematic diagram for SAP+I, Figures 10-12 to 10-15 show all the chips, wires, and signals. You should refer to these figures throughout the following discussion. Appendix 4 gives additional details for some of the more complicated chips. ye smote Fig, 10-11 Positive clock edges occur midway through T states. 152 igitat Computer ElectronicsTABLE 10-3 Macro State CyB, L,,CE WA 7% 0001 Tr 0010 Tr 0011 TABLE 10-4 ‘Macro State CON Active LDA oT Program Counter Chips C1, C2, and C3 of Fig. 10-12 are the program counter. Chip C1, a 74L8107, is a dual JK master-slave flip-flop, that produces the upper 2 address bits. Chip C2, another 74.8107, produces the lower 2 address bits. Chip C3 is a 74,126, a quad three-state normally open switeh; it gives the program counter a three-state output. At the start of a computer run, a low CLR resets the program counter to 0000. During the T; state, a high E> places the address on the W bus. During the 7 state, high Cpis applied to the program counter; midway through this state, the negative CLK edge (equivalent to positive CLK edge) increments the program counter. ‘The program counter is inactive during the P10 T, states. SuEpTaLo oo1d oo1d corn MAR Chip C4, a 74.8173, is a 4-bit buffer register; it serves as the MAR. Notice that pins 1 and 2 are grounded; this converts the three-state output to a (wo-state output. In other words, the output of the MAR is not connected to the W bus, and so there's no need to use the three-state output. 2-to-1 Multiplexer Chip C5 is a 7418157, a 2-to-1 nibble multiplexer. The left nibble (pins 14, 11, 5, 2) comes from the address switch register (S,). The right nibble (pins 13, 10, 6, 3) comes from the MAR. The RUN-PROG switch (S.) selects the nibble to reach to the output of C5. When 8; is in the PROG position, the nibble out of the address switch register is selected. On the other hand, when Sis the RUN position, the output of the MAR is selected, 16 x 8RAM Chips C6 and C7 are 741895. Each chip is a 16 * 4 static RAM. Together, they give us a 16 x 8 read-write memory. Sy is the data switch register (8 bits), and S, is the read- write switch (a push-button switch), To program the mem cory, $2 is put in the PROG position; this takes the CE input low (pin 2), The address and data switches are then set to the correct address and data words. A momentary push of the read-write switch takes WE low (pin 3) and loads the memory. After the program and data are in memory, the RUN: PROG switch (S,) is put in the RUN position in preparation for the computer run, Instruction Register Chips C8 and C9 are 74LS173s. Each chip isa 4-bitthree- state bufier register. The two chips are the insruction register. Grounding pins | and 2 of C8 converts the three- state output toa two-state output, Ill. Ths nibble goes tote instruction decoder inthe contoller-sequencer. Signa , controls the output of C9, the lower nibble in the instruction register. When E, is los, this nibble is placed on the W bus Chapter 10 sap-1 153¥3LNN09 wyusous Lo wise Digital Computer Electronics 154soto usu pus “AoUIDU “ZgUNOD uMROMd aVS THOT “Bd 155 yausiozy NOHONISNI z Chapter 10. SAP-1 aayeaswe 9 szisee wouovu.ans yaaaay szistve crise voLwinwnooy ae ‘eaistee 156 Digital Computer Electronicsue oisengns-19ppe “sions PUP Y E1-01 “Bia 157 a9 Chapter 10 SAP.1 existe ez uausiosu Andino euiswe zo caste 0x0 wausiogy 6Accumulator Chips C10 and C11, 74L$173s, are the accumulator (see Fig. 10-13). Pins I and 2 are grounded on both chips to produce a two-state output for the adder-subtracter. Chips CI2 and C13 are 74LS126s; these three-state switches place the accumulator contents on the W bus when E, is hi Adder-subtracter Chips C14 and CIS are 74LS86s. These EXCLUSIVE-OR ‘gates are a controlled inverter. When Sy is low, the contents Of the B register are transmitted. When Sy is high, the 1's ‘complement is transmitted and a 1 is added to the LSB to form the 2's complement. Chips C16 and C17 are 74LS83s. These 4-bit full adders combine to produce an 8-bit sum or difference. Chips C18 and C19, which are 741.1265, convert this 8-bit answer into a three-state output for driving the W bus. B Register and Output Register Chips C20 and C21, which are 74LS173s, form the B register, It contains the data to be added or subtracted from the accumulator. Grounding pins 1 and 2 of both chips produces a two-state output for the adder-subtracter Chips C22 and C23 are 74LS1738 and form the output register, It drives the binary display and lets us see the processed data Clear-Start Debouncer In Fig. 10-14, the clear-stare debouncer produces two ‘outputs: CLR for the instruction register and CLR for the program counter and ring counter. CLR also goes to C29, the clock-start flip-flop. Sis a push-button switch. When depressed, it gors to the CLEAR positon, generating a high CLR and a low CLR. When 5; s released, it returns to the START position, producing a low CLR and a high CTR. Notice that half of 24s used forthe clearstart debouncer and the other half forthe single-step debouncer. Chip C24 is a 7400, a quad 2-input NAND gate Single-Step Debouncer ‘SAP-I can run in either of two modes, manual or automatic. In the manual mode, you press and release S, to generate ‘one clock pulse. When S, is depressed, CLK is high; when released, CLK is low. In other words, the single-step debouncer of Fig. 10-14 generates the T states one at a time as you press and release the button. This allows you to step through the different T states while troubleshooting for debugging. (Debugging means looking for errors in your program. You troubleshoot hardware and debug software.) 158 Digital Computer Electronics Manual-Auto Debouncer Switch S; isa single-pole double-throw (SPDT) switch that can remain in either the MANUAL position or the AUTO position, When in MANUAL, the single-step button i active. ‘When in AUTO, the computer runs automatically. Two of the NaND gates in C26 are used to debounce the MANUAL AUTO switch. The other two NAND C26 gates are part of a NAND-NAND network that steers the single-step clock or the ‘automatic clock to the final CLK and CLR outputs. Clock Buffers The output of pin 11, C26, drives the clock buffers. As you see in Fig, 10-14, two inverters are used to produce the final CLK output and one inverter to produce the CLK ‘output. Unlike most of the other chips, C27 is standard "TTL rather than a low-power Schottky (see SAP-1 Parts List, Appendix 5). Standard TTL is used because it can rive 20 low-power Schottky TTL loads, as indicated in Table 4-5, Ifyou check the data sheets of the 74LS107 and 74LS173 for input currents, you will be able to count the following low-power Schottky (LS) TTL loads on the clock and clear signals: CLK = 19 LS loads CLK = 21S loads CLR = ILS load CLR = 20S loads This means that the CLK and CLK signals out of C27 (standard TTL) are adequate to drive the low-power Schottky TTL loads. Also, the CLR and CER signals out of C24 (standard TTL) can drive their loads. Clock Circuits and Power Supply Chip C28 is a 555 timer. This IC produces a rectangular 2-kHz output with a 75 percent duty cycle. As previously discussed, a start-the-clock flip-flop (C29) divides the signal down to | kHz and at the same time produces a 50 percent duty cycle. ‘The power supply consists of a full-wave bridge rectifier ‘working into 2 capacitor-input filter. The de voltage across the 1,000-F capacitor is approximately 20 V. Chip C30, an LM34OT-S, is a voltage regulator that produces a stable output of +5 Instruction Decoder Chip C31, a hex inverter, produces complements of the op-code bits, Iyloely (See Fig. 10-15). Then chips 33, and C34 decode the op code to produce five output signals: LDA, ADD, SUB, OUT, and HLT. Remember:Ss A starr sinaLe sre 51 MANUAL wanuaus nore Ce aur0 ar ca ctock cncurr aoa Power 4 SUPPLY | Fig, 10-14 Power supply, clock, and clear circuits only one of these is active ata time. (HLT is active lows all the others ate active high.) ‘When the HLT instruction is in the instruction register, bits Ijosls are LLL and HLT is low. This signal returns to C25 (single-step clock) and C29 (automatic clock). In either MANUAL oF AUTO mode, the clock stops and the computer run ends 220 uF Ring Counter ‘The ring counter, sometimes called state counter, consists of thre chips, C36, C37, and C38, Each ofthese chips 5 8 7ALSIO7, a dual JK master-slave flip-flop. This counter is reset when the clear-start button (S.) is pressed. The Qs Aipop i inverted so that its output pin 6, C38) drives Chapter 10 sap-1 159‘qn jonuos pur “iaqunn® Huts “soposop uononsisuy SE-0F “BL i th tt) Lea orepsra] era | lenges] lop] ep] ee] loorm sem eyo | XIULVW OUANOD RINNOD ONY re, and Ty The op code in the instruction register controls the ‘execution eyele. If an ADD instruction has been fetched. the Dla bits are 0001, These op-code bits drive the auddress ROM, producing an output of 0110 (Table 10-7) ‘This starting adress isthe input to the presettable counter. When 7; is high, the next negative clock edge loads 0110 into the presttable counter. The counter is now preset, and counting can resume at the starting address of the ADD routine. The counter output is O110 during the 7, state, O111 during the 7; state, and 1000 during the 7, state. When the 7; state begins, the leading edge of the 7; signal i differentiated to produce « narrow positive spike which resets the counter to 0000, the starting address of the fetch routine, A new machine eyele then begins.Control ROM ‘The control ROM stores the SAP-1 microinstructions, During the fetch cycle, it receives addresses 0000, 0001, and 0010. Therefore, its outputs are SEH BESH 263H ‘These microinstructions, listed in Table 10-6, produce the address state, increment state, and memory state If an ADD instruction is being executed, the control ROM receives addresses 0110, O11, and 1000 during the execution cycle. Its outputs are 1A3H 2E1H 3C7H ‘These microinstructions carry out the addition as previously discussed. For another example, suppose the OUT instruction is being executed. Then the op code is 1110 and the starting address is [100 (Table 10-7). During the execution cycle, the counter output is 1100, 1101, and 1110. The output of the control ROM is 3F2H, 3E3H, and 3E3H (Table 10-6), ‘This routine transfers the accumulator contents to the output port Variable Machine Cycle ‘The microinstruction 3E3H in Table 10-6 a nop. It occurs, once in the LDA routine and twice in the OUT routine. These nops are used in SAP-I to get a fixed machine cycle for all instructions. In other words, each machine cycle takes exactly six T states, no mater what the instruction In some computers a fixed machine eyele is an advantage But when speed is important, the nops are a waste of time and can be eliminated One way to speed up the operation of SAP-I is to skip any TT state with a nop. By redesigning the circuit of Fig 10-16 we can eliminate the nop states. This will shorten the machine cycle of the LDA instruction to five states (71, T,, Ts, Ty, and T). It also shortens the machine cycte of the OUT instruction to four T states (T,, Ts. T,, and T,). Figure 10-17 shows one way to get variable machine eyele. With an LDA instruction, the action is the same as before during the 7; to T, states. When the 7, state begins, the control ROM produces an output of 3E3H (the nop microinstruction). The NAND gate detets this nop instantly and produces a low output signal NOP. NOP is fed back to the ring counter through an aND gate, as shown in Fig 10-18. This resets the ring counter to the 7; state, and a new machine eycle begins. This reduces the machine cycle of the LDA instruction from six sates to five Presttble cur Mierlnsetion ig. 10-17 Variable machine cycle. Ring counter fp cu Fig. 10.18 With the OUT instruction, the first nop occurs in the Ts state. In this case, just after the T, state begins, the control ROM produces an output of 3E3H, which is detected by the NAND gate. The low NOP signal then resets the ring counter to the 7, state. In this way, we have reduced the ‘machine cycle of the OUT instruction from six states t0 four, Chapter 10 sap-1 163‘Variable machine cycles are commonly used with miero- processors. In the 8085, for example, the machine take from two to six T states because all unwanted nop states are ignored. Advantages One advantage of microprogramming is the elimination of the instruction decoder and control matrix; both of these become very complicated for larger instruction sets. In other words, it’s a lot easier to store microinstructions in a ROM than it is to wire an instruction decoder and control matrix. Furthermore, once you wire an instruction decoder and control matrix, the only way you can change the instruction set is by disconnecting and rewiring. This is not necessary with microprogrammed control; all you have to do is change the control ROM and the starting-address ROM. This is a big advantage if you are trying to upgrade equipment sold earlier. Summary In conclusion, most modern microprocessors use micropro- grammed control instead of hardwired control, The micro- programming tables and circuits are more complicated than those for SAP-I, but the idea isthe same. Microinstructions are stored in a control ROM and accessed by applying the address of the desired microinstruction. GLOSSARY address state The T, state, During this state, the address in the program counter is transferred to the MAR. ‘accumulator The place where answers to arithmetic and logic operations are accumulated. Sometimes called the A register. assembly language The mnemonics used in writing @ program B register An auxiliary register that stores the data to be added or subtracted from the accumulator ‘fetch eycle The first part of the instruction cycle. During the fetch cycle, the address is sent to the memory, the program counter is incremented, and the instruction is transferred from the memory to the instruction register. increment state The T; state. During this state, the pro- ‘gram counter is incremented. instruction eyele All he states needed to fetch and execute an instruction, instruction register The register that receives the instruc- tion from the memory instruction set The instructions a computer responds to. LDA Mnemonic for load the accumulator. ‘machine cycle All the states generated by the ring counter. ‘machine language The strings of Os and Is used in a program. ‘macroinstruction set (One of the instructions inthe instruction MAR Memory address register. This register receives the address of the data to be accessed in memory. The MAR supplies this address to the memory, memory-reference instruction An instruction that calls for a second memory operation to access data. ‘memory state The T, state. During this state, the instruc- tion in the memory is transferred (o the instruction register. microinstruction A control word out of the controller- sequencer. The smallest step in the data processing. nop No operation. A state during which nothing happens. ‘output register ‘The register that receives provessed data from the accumulator and drives the output display of SAP- 1, Also called an output por. object program A program written in machine language. opcode Operation code. That part ofthe instruction which tells the computer what operation to perform. program counter A register that counts in binary. Its contents are the address of the next instruction to be fetched from the memory. RAM Random-access memory. A better name is read- write mémory. The RAM stores the program and data needed for a computer run. source program program written in mnemonics. SELF-TESTING REVIEW. Read each of the following and provide the missing words. ‘Answers appear at the beginning of the next question, 1, The —____ counter, which is part of the con- {rol unit, counts from 0000 to 1111. It sends to the memory the of the next instruction 164 Digital Computer Electronics (program, address) The MAR, or —____ reg- ister, latches the address from the program counter A Dit later, the MAR applies this address to the where a read operation is performed. (memory-address, RAM) The instruction register is