Scribd
Upload
46 views

MIcroprocessor Design On PC Input and MAR RAM

The document describes the design of the SAP-1 microprocessor, a basic educational model. It contains 16 bytes of RAM, an accumulator architecture with registers like the accumulator, B register, and instruction register. It has a 4-bit program counter, 8-bit adder/subtractor, and uses a 6-cycle controller. The purpose is to demonstrate the basic functioning of a microprocessor through simple instructions and interactions with memory and I/O.

Uploaded by

vester sampana
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
46 views

MIcroprocessor Design On PC Input and MAR RAM

The document describes the design of the SAP-1 microprocessor, a basic educational model. It contains 16 bytes of RAM, an accumulator architecture with registers like the accumulator, B register, and instruction register. It has a 4-bit program counter, 8-bit adder/subtractor, and uses a 6-cycle controller. The purpose is to demonstrate the basic functioning of a microprocessor through simple instructions and interactions with memory and I/O.

Uploaded by

vester sampana
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
You are on page 1/ 33

MICROPROCESSOR DESIGN

(SAP)-1

• Engr. Mariscel Lived De Guzman


• Engr. Mel-John Catanaoan
• Engr. Robert Justin Chavez
INTRODUCTION

• SAP-1 computer is a very basic model of a microprocessor.


• SAP-1 design contains the basic necessities for a functional
microprocessor.
• Its primary purpose is to develop a basic understanding of
how a microprocessor works, interacts with memory and
other parts of the system like input and output. The
instruction set is very limited and is simple.
MAIN FEATURES

• One output device with 8 LEDs


• 16 bytes of RAM.
• 5 instructions
• 3 with 1 operand
• 2with implicit operands. ,
• Accumulator Architecture
• Accumulator,
• B Register,
• Instruction Register (IR)
• Out Register
• Memory Address Register (MAR)
ARCHITECTURE

• A single 8-bit "W“ bus for address and data transfer


 4-bit program counter, only counts up, it starts
counting from 0 and counts up to 15.
 4-bit Memory Address Register (MAR).
 16 Byte Memory.
• 8-bit (1 Byte) Instruction Register (IR).
• 6-cycle controller with 12-bit microinstruction word.
• 8-bit Accumulator.
• 8-bit BRegister.
• 8-bit adder/subtractor.
• 8-bit Output Register.
• Block
Diagram
PROGRAM COUNTER

• Instructions to be executed are placed at the starting addresses


of memory, e.g. the first instruction of a program will be placed
at binary address 0000, the second at address 0001.
• Now to execute one instruction, first step is to generate the
address at which this instruction is placed in memory.
• So this address is generated by (4-bit) Program Counter, that
counts from 0000 to 1111 (for total of 16 memory locations)
• If the value of program counter is 0100, then the instruction at
address 4 will be executed next.
• Program counter is like a pointer register; it points to the
address of next instruction to be executed.
INPUT AND MEMORY ADDRESS
REGISTER (MAR)
• The MAR stores the (4-bit) address of data and instruction
which are placed in memory.
• When SAP-1 is Running Mode, the (4-bit) address is
generated by the Program Counter which is then stored
into the MAR through W bus.
A bit later, the MAR applies this 4-bit address to the
RAM, where data or instruction is read from RAM.
RANDOM ACCESS MEMORY (RAM)

• In the design, the RAM is a 16 x 8 static TTL RAM.


• It means there are 16 memory locations (from 0 to 15)
and each location contains an 8-bit of data/instruction.
• The RAM can be programmed by means of the switches to be
used for address and data.
• This allows you to store a program and data in the
memory before a computer run.
RANDOM ACCESS MEMORY (RAM)

During a computer run, the RAM receives 4-bit addresses


from the MAR and a read operation is performed,
in this way, the instruction or data stored in the RAM is
placed on the W bus for use in some other part of the
computer.
ADDER/SUBTRACTOR

• SAP-1 uses a 2's complement adder-subtractor. When


input Su is low (logic 0), the sum is:
S =A+B

• When Su is high (logic 1), the sum is:


• S = A + B’ + 1
• The Adder-subtractor is asynchronous and its contents
change as soon as the input changes.

• When EU is high, these contents appear on the W bus.


ACCUMULATOR

• To add/sub two 8-bit numbers A and B, the


accumulator register stored the number A.
o The Accumulator has two outputs.
o One output goes to the adder/subtractor
• The other goes to the W through tri-state buffers.
• It also stores the (answer of two values) output of
adder/subtractor through w-bus, when LA is low.
• It’s value is appeared on w-bus when EA is high,
which can then be read by output register.
B REGISTER

• To add/sub two 8-bit numbers A and B, the B


register stored the number B.
• It supplies the number to be added or subtracted
from the contents of accumulator to the
adder/subtractor.
• When data is available at W-bus and Lb goes low,
at the positive clock edge, B register loads that
data.
OUTPUT REGISTER

• At the end of an arithmetic operation the


accumulator contains the word representing the
answer,
• Then answer stored in the accumulator register is
then loaded into the output register through W-
bus.
• This is done in the next positive clock edge when
EA is high and LOis low.
• Now this value can be displayed to the outside
world with the help of LEDs or 7 Segments.

You might also like