Basic Computer Organisation and Design

Title: Chapter Five - Basic Computer Organization and Design

Introduction:
- This chapter introduces a basic computer and outlines how its operation can
be specified using register transfer statements.
- The computer's organization is defined by its internal registers, timing and
control structure, and the set of instructions it uses.
- The basic computer presented in this chapter is relatively small compared to
commercial computers but serves as a simple example for demonstrating the
design process.

Internal Organization of Digital Systems:

- The internal organization of a digital system is defined by the sequence of
microoperations it performs on data stored in its registers.
- General-purpose digital computers can execute various microoperations and
be instructed with specific sequences of operations through programs.
- A program is a set of instructions that specify the operations, operands, and
processing sequence.
- The data-processing task can be modified by changing the program
instructions or the data itself.

Computer Instructions:
- A computer instruction is a binary code that specifies a sequence of
microoperations for the computer.
- Instruction codes, along with data, are stored in memory.
- The computer reads each instruction from memory and places it in a control
register.
- The control unit interprets the binary code of the instruction and executes it
by issuing a sequence of microoperations.
- Each computer has its own unique instruction set, and the ability to store and
execute instructions is the fundamental property of a general-purpose
computer.

Structure of an Instruction Code:

- An instruction code is a group of bits that instruct the computer to perform a
specific operation.
- It is typically divided into parts, with each part having its interpretation.
- The operation part of an instruction code defines operations such as addition,
subtraction, multiplication, shifting, and complementing.
- The number of bits required for the operation code depends on the total
number of available operations in the computer.
- Example: A computer with 64 distinct operations might use a six-bit operation
code, with a specific bit configuration for each operation.

Relationship Between Operations and Microoperations:

- An operation is part of an instruction stored in computer memory,
represented as a binary code.
- The control unit receives the instruction, interprets the operation code, and
issues control signals to initiate microoperations in internal computer registers.
- For each operation code, the control unit specifies a sequence of
microoperations needed for implementing the operation.
- An operation code is sometimes referred to as a macrooperation as it
specifies a set of microoperations.

Instruction Code Format:

- The operation part of an instruction code specifies the operation to be
performed.
- The instruction code must also specify where the operands are located
(registers or memory) and where the result should be stored.
- Memory words are specified by their addresses, and processor registers are
specified using binary codes.
- Different computers may have various instruction code formats designed by
computer architects to suit the computer's architecture.

Stored Program Organization:

- One simple way to organize a computer is with one processor register and an
instruction code format consisting of two parts: operation and address.
- The memory address in the instruction tells the control unit where to find an
operand in memory.
- The operand is read from memory and combined with the data in the
processor register for processing.

End of Chapter Summary:

- The chapter discusses the fundamental concepts of computer organization,
instruction codes, and the relationship between operations and
microoperations.
- It also introduces the concept of a stored program organization where
instructions and data are stored in memory for the computer to execute.
Section 5-1: Instruction Codes

In this section, the text discusses the organization of instructions and data in
memory and the format of instruction codes. It also introduces the concepts of
immediate, direct, and indirect addressing modes.

1. **Memory Organization**:
- Memory is divided into two sections: one for instructions and one for data.
- The memory unit used has a capacity of 4096 words, requiring 12 bits to
specify an address (2^12 = 4096).
- Each instruction code is stored in a 16-bit memory word, providing space for
both the operation code (opcode) and the address of an operand.
- The control unit reads a 16-bit instruction from the program portion of
memory and uses the 12-bit address part of the instruction to fetch a 16-bit
operand from the data portion of memory.
2. **Instruction Code Format**:
- Each instruction code has two parts: an opcode and an address.
- Opcode: Specifies one of 16 possible operations using 4 bits.
- Address: Specifies the memory address of an operand using 12 bits.
- The control unit executes the operation based on the operation code.

3. **Single-Processor Register (Accumulator)**:

- Computers with a single processor register typically name it the
"accumulator" (AC).
- Operations are performed by combining the memory operand with the
content of the accumulator (AC).

4. **Instructions Without Memory Operands**:

- Some operations do not require operands from memory, such as clearing
the accumulator, complementing the accumulator, or incrementing the
accumulator.
- In such cases, the remaining bits in the instruction (bits 0 through 11) that
are not used for specifying a memory address can be utilized for other
purposes or operations.

5. **Indirect Addressing**:
- There are scenarios where the address bits of an instruction code are not
used as an address but represent the actual operand.
- Three addressing modes are introduced: immediate operand, direct
address, and indirect address.
- Immediate Operand: The address bits represent the operand itself.
- Direct Address: The address bits specify the memory location of the
operand.
- Indirect Address: The address bits designate a memory word that contains
the address of the operand.
- A mode bit (I) is used to distinguish between direct (I = 0) and indirect (I = 1)
addressing.

6. **Instruction Code Format with Indirect Addressing**:

- The instruction code format includes a 3-bit operation code, a 12-bit
address, and an indirect address mode bit (I).
- The I bit determines whether the instruction has a direct or indirect
address.
- Examples of both direct and indirect address instructions are given, and
their execution is explained.
- Indirect address instructions require two memory references: one to read
the operand's address and another to fetch the operand itself.
- The effective address is the address of the operand in computation-type
instructions or the target address in branch-type instructions.

7. **Usage of Addressing Modes**:

- The presented computer in this chapter uses direct and indirect addressing
modes.
- The memory word holding the address of an operand in an indirect address
instruction serves as a pointer to an array of data.
- In commercial computers, this pointer can be placed in a processor register
for efficiency.

This section provides a detailed overview of memory organization and

addressing modes in the context of instruction codes. It also highlights the
execution process of instructions with different addressing modes.
In Section 5-2, the text discusses the configuration of computer registers and
their functions within a basic computer. It also introduces the concept of a
common bus system for efficient data transfer between registers and memory.

1. **Memory and Instruction Sequencing**:

- Computer instructions are stored in consecutive memory locations and
executed sequentially.
- A counter is needed to calculate the address of the next instruction after
the current one is executed.
- A register in the control unit stores the instruction code after it is read from
memory.

2. **Registers in the Basic Computer**:

- The basic computer is equipped with several registers, each serving a
specific purpose.
- Table 5-1 provides a list of registers, their names, functions, and the
number of bits they contain.

3. **Memory Capacity and Instruction Format**:

- The memory unit has a capacity of 4096 words, with each word containing
16 bits.
- Instructions use 12 bits to specify the address of an operand, leaving 3 bits
for the operation code and 1 bit to specify direct or indirect addressing.

4. **Key Registers**:
- Data Register (DR): Holds the operand read from memory.
- Address Register (AR): Contains the memory address.
- Accumulator (AC): A general-purpose processing register.
- Instruction Register (IR): Holds the instruction code.
- Temporary Register (TR): Used for holding temporary data during
processing.
- Program Counter (PC): Stores the address of the next instruction to be
executed.
- Input Register (INPR) and Output Register (OUTR): Used for input and
output operations, respectively.
5. **Address Handling**:
- AR and PC both have 12 bits since they store memory addresses. The most
significant bits are set to 0 when transferring data to these registers.
- INPR and OUTR deal with 8-bit characters.

6. **Common Bus System**:

- To efficiently transfer information between registers and memory without
an excessive number of wires, a common bus system is used.
- The common bus connects the outputs of seven registers and the memory
to the inputs of other registers and memory.
- Selection variables (S2, S1, and S0) determine which register's output is
placed on the bus.
- Registers have control inputs (LD, INR, CLR) to load data, increment values,
or clear contents.
- The common bus enables parallel data transfer between registers and
memory.

7. **Adder and Logic Circuit**:

- The accumulator (AC) receives input from an adder and logic circuit.
- This circuit allows AC to perform operations like addition and logic
operations by taking inputs from AC, DR, and INPR.
- The result of an addition is transferred to AC, and the carry-out is sent to a
flip-flop (E).

8. **Simultaneous Operations**:
- Multiple microoperations can be executed in parallel during the same clock
cycle.
- This efficiency is achieved by placing the content of one register onto the
bus and enabling the load input of another register or executing an operation
in the adder and logic circuit simultaneously.
This section provides a detailed overview of the registers used in a basic
computer and how they are interconnected using a common bus system for
efficient data transfer and processing.
The basic computer introduced in this chapter utilizes three different
instruction code formats, each consisting of 16 bits. These formats are
designed to handle various types of instructions, including memory-reference,
register-reference, and input-output instructions. Here are more detailed
explanations of each of these instruction formats:

**Memory-Reference Instruction Format (Opcode 000-110):**

- This format is used for instructions that involve memory operations, such as
loading data from memory or storing data into memory.
- The instruction consists of 16 bits, with the first three bits representing the
opcode (operation code).
- The remaining 13 bits are used to specify the memory address (12 bits) and
the addressing mode I (1 bit). The I bit indicates whether the address is direct (I
= 0) or indirect (I = 1).

**Register-Reference Instruction Format (Opcode 1110):**

- This format is dedicated to instructions that operate on or test the content of
the AC (accumulator) register.
- The instruction code begins with the fixed opcode "1110" (binary), which
corresponds to hexadecimal "E."
- The remaining 12 bits of the instruction are used to specify the operation or
test to be performed on the AC register.
- Since these instructions don't require memory operands, all 12 bits are
dedicated to the operation code.

**Input-Output Instruction Format (Opcode 1111):**

- This format is reserved for input-output (I/O) instructions that interact with
external devices.
- The instruction code starts with the fixed opcode "1111" (binary), which
corresponds to hexadecimal "F."
- The remaining 12 bits are used to specify the type of I/O operation or test to
be performed.
- Similar to register-reference instructions, input-output instructions do not
involve memory references, so all 12 bits are used for the operation code.

**Instruction Recognition:**
- The computer's control unit recognizes the type of instruction based on the
values in specific bit positions within the instruction.
- For memory-reference instructions, the control unit examines the bits in
positions 12 through 15 to determine whether the instruction uses direct or
indirect addressing (based on the I bit).
- If the opcode is "111" (binary) in positions 12 through 14, the control unit
identifies the instruction as either register-reference or input-output based on
the value of the I bit (position 15).
- Register-reference instructions are distinguished by a "0" in bit position 15,
while input-output instructions have a "1" in bit position 15.
- The control unit then interprets the remaining bits according to the specific
instruction format.

**Number of Instructions:**
- Despite having only three bits for the opcode in memory-reference
instructions, the computer supports a total of 25 distinct instructions.
- This is achieved by using the remaining 12 bits in memory-reference
instructions and all 12 bits in register-reference and input-output instructions
for specifying various operations, tests, and I/O operations.

The instructions are represented using a symbol designation, typically a three-

letter word, making it easier for programmers and users to work with.
Additionally, the hexadecimal code is provided, which represents the
equivalent hexadecimal value of the binary instruction code. This hexadecimal
representation simplifies the presentation and reduces the length of the
instruction codes for reference.
In the provided section, various aspects of computer instructions and their
organization are discussed. Here are the key points and details:

**Computer Instruction Formats:**

1. The basic computer uses three instruction code formats, each consisting of
16 bits.
2. The operation code (opcode) takes up three bits, and the remaining 13 bits'
meaning depends on the specific opcode.
3. Memory-reference instructions use 12 bits for specifying an address and one
bit for addressing mode I (0 for direct and 1 for indirect).
4. Register-reference instructions have the opcode 111 with a 0 in the leftmost
bit (bit 15), using the other 12 bits for specifying operations on the AC register.
5. Input-output instructions also have the opcode 111 but with a 1 in the
leftmost bit, using the remaining 12 bits to specify input-output operations.

**Instruction Set Completeness:**

1. The instruction set of a computer should be complete, allowing users to
construct machine language programs for any computable function.
2. A complete set includes:
- Arithmetic, logical, and shift instructions.
- Instructions for moving data between memory and processor registers.
- Program control instructions, including status condition checks.
- Input and output instructions for communication with external devices.
3. The basic computer's instruction set (as listed in Table 5-2) provides these
capabilities, albeit with some limitations. Complex operations like subtraction
and multiplication can be achieved through combinations of simpler
instructions.

**Efficiency of Instruction Set:**

1. While the basic computer's instruction set is complete, it may not be
efficient for all purposes.
2. More efficient instruction sets include operations like subtraction,
multiplication, OR, and exclusive-OR as direct instructions, making them faster
and more convenient.
3. The basic computer's instruction set is designed for simplicity and
educational purposes, but practical computers include a broader range of
instructions for efficiency.

The section provides an overview of the basic computer's instruction formats,

completeness of its instruction set, and considerations for efficiency. The
functions of each instruction and their microoperations are discussed in
subsequent sections, which delve into the internal organization of the control
unit.
Certainly, here are detailed notes on the concept of timing and control in a
computer's operation:

**Timing and Control in Computer Operation:**

1. Timing in a computer is crucial for coordinating the activities of various

components, including registers, memory, and the execution of instructions. It
ensures that operations occur in the correct sequence and at the right
moment.

2. A master clock generator generates clock pulses that serve as a timing

reference for the entire computer system. These clock pulses have a regular
and consistent frequency and are used to synchronize various actions.

3. Clock pulses are applied to all flip-flops and registers within the computer
system. However, a clock pulse alone does not change the state of a register
unless the register is enabled by a control signal.
4. Control signals, generated by the control unit, determine which registers or
components should respond to the clock pulses at a given time. These control
signals are responsible for directing the flow of data and operations within the
computer.

**Types of Control Organization:**

5. There are two primary types of control organization in computers:

hardwired control and microprogrammed control.

a. **Hardwired Control:** In hardwired control, the control logic is

implemented using digital circuits such as gates, flip-flops, and decoders. It is
designed to optimize the computer's operation for speed.

b. **Microprogrammed Control:** In microprogrammed control, control

information is stored in a control memory. The control memory is programmed
to initiate specific sequences of microoperations. It offers flexibility and ease of
modification compared to hardwired control.

**Control Unit in the Basic Computer:**

6. In the basic computer described, a hardwired control unit is used. The

control unit consists of several components, including decoders, a sequence
counter, and control logic gates.

7. When an instruction is read from memory, it is stored in the instruction

register (IR). The IR contains the instruction's operation code, addressing mode
(I bit), and other bits.

8. The operation code (bits 12-14) is decoded using a 3-to-8 decoder, resulting
in eight possible decoder outputs (D0 through D7). These outputs correspond
to different operation codes and help determine the instruction's purpose.
9. The sequence counter (SC), a 4-bit counter, counts in binary from 0 to 15. Its
outputs are decoded into 16 timing signals (T0 through T15) that control
various aspects of the computer's operation.

**Timing Control Flow:**

10. The sequence counter (SC) can be incremented or cleared synchronously.

Typically, it is incremented to provide a sequence of timing signals.
Occasionally, it is cleared to 0, triggering the next active timing signal.

11. The timing diagram illustrates the relationship between control signals and
clock transitions. The sequence counter responds to positive clock transitions.

12. Initially, the sequence counter is cleared to 0, activating the first timing
signal (T0). With each positive clock transition, SC is incremented unless it is
cleared, leading to the sequential activation of timing signals (T0, T1, T2, T3,
T4, and so on).

13. This sequence of timing signals orchestrates the various operations and
microoperations within the computer, ensuring that instructions are executed
in the correct order and at the right times.

In summary, timing and control in a computer system are essential for

orchestrating the activities of its components. Control signals, generated by
the control unit, determine which operations occur during each clock cycle,
and the timing signals coordinate the sequence of actions. Different control
organizations, such as hardwired control and microprogrammed control, can
be employed to achieve these objectives.
Certainly, here are detailed notes on the timing and control aspects discussed
in the provided text:
**Clearing Sequence Counter (SC):**
- The timing diagram (Fig. 5-7) illustrates how the sequence counter (SC) is
cleared when the condition D3T4 is met, meaning that output D3 from the
operation decoder becomes active at the end of timing signal T2.
- When timing signal T4 becomes active, an AND gate that implements the
control function D3T4 also becomes active. This signal is then applied to the
CLR (clear) input of SC.
- During the next positive clock transition (marked as T4 in the diagram), SC is
cleared to 0. This action results in timing signal T0 becoming active instead of
T5, which would have been active if SC were incremented instead of cleared.

**Memory Read/Write Timing:**

- Memory read or write cycles are initiated with the rising edge of a timing
signal. It's assumed that the time required for a memory read or write cycle is
less than the clock cycle time.
- The assumption is that by the time the next clock cycle's positive transition
occurs, a memory read or write cycle initiated by a timing signal will have been
completed. At that point, the memory word can be loaded into a register.
- It's important to note that this timing relationship is not universally valid, as
in many computers, memory cycle times are longer than processor clock cycle
times. In such cases, wait cycles are required to accommodate the difference
between memory and processor speeds.
- For the purposes of discussion in the basic computer, it's assumed that wait
periods are not necessary.

**Understanding Register Transfer Timing:**

- To fully understand the operation of the computer, it's essential to grasp the
timing relationship between clock transitions and timing signals.
- For example, consider the register transfer statement: "T0: AR ← PC."
- This statement specifies that the content of the program counter (PC) should
be transferred into the address register (AR) if timing signal T0 is active.
- Timing signal T0 remains active throughout an entire clock cycle interval.
- During this time, the content of PC is placed onto the bus using appropriate
control signals (S2S1S0) and the LD (load) input of AR is enabled.
- However, the actual transfer of data from PC to AR does not occur until the
end of the clock cycle when the clock goes through a positive transition.
- The positive clock transition also increments the sequence counter SC from
0000 to 0001, meaning that the next clock cycle will have T1 active and T0
inactive.

In summary, understanding the timing and control signals within a computer

system is essential for ensuring that operations occur in the correct sequence
and at the right moments. Timing diagrams and clear definitions of register
transfer timing are crucial for programming and designing computer systems
effectively.
In the basic computer's instruction cycle, each instruction goes through several
phases, as outlined below:

1. **Fetch an Instruction from Memory:** This phase involves obtaining the

next instruction to be executed from the computer's memory. This instruction
is typically pointed to by the program counter (PC).

2. **Decode the Instruction:** Once fetched, the computer needs to

determine what operation the instruction represents. This is the decoding
phase where the operation code (opcode) of the instruction is interpreted.

3. **Read the Effective Address from Memory (if required):** In some cases,
instructions may have an indirect address. In such instances, the computer
needs to fetch additional data from memory to determine the effective
address for the instruction.

4. **Execute the Instruction:** Finally, the computer performs the actual

operation specified by the instruction. This phase could involve arithmetic
calculations, logical operations, data transfers, or control flow changes.
After the execution phase, the control loop returns to the first step (fetch) to
process the next instruction in the sequence. This cycle continues until a HALT
instruction is encountered, which typically indicates the end of the program.

Here's a more detailed explanation of the fetch and decode phases:

- **Fetch Phase (T0):**

- The program counter (PC) is loaded with the address of the next instruction
in memory.
- The sequence counter (SC) is cleared to 0, which generates timing signal T0.
- The address from PC is transferred to the address register (AR) to prepare
for memory access.
- The instruction at the address in AR is read from memory and placed into
the instruction register (IR).
- PC is incremented by 1 to point to the next instruction in memory.
- The operation code (opcode) and addressing mode bits from IR are decoded.
- The indirect addressing bit is transferred to a flip-flop designated as I.

The timing signals T0, T1, and T2 are used to synchronize these operations in
the fetch phase.

During the decode phase (T2), the computer interprets the opcode and sets up
the control signals for the execution phase. This ensures that the instruction is
correctly executed in the subsequent phases of the instruction cycle.

The control unit of the computer is responsible for generating these timing
signals and coordinating the various operations of the instruction cycle. The
details of how these phases are implemented in the control unit and bus
system are important for understanding the internal workings of the
computer.
In the basic computer's instruction cycle, once an instruction is decoded, it is
executed in the "Execute" phase. The execution phase includes various
microoperations depending on the type of instruction. Register-reference
instructions are a specific type of instruction where the operation is performed
on the registers of the computer. Here is an explanation of the execution of
register-reference instructions:

1. **Control Function Determination:** Register-reference instructions are

identified during the "Decode" phase by checking the values of D7 (decoder
output) and I (indirect bit) in the instruction. Specifically, the computer checks
if D7I and T3 (the current timing signal) are all true. This combination of
conditions is denoted as r, simplifying the control function determination.

2. **Microoperations:** Each register-reference instruction corresponds to a

specific microoperation on the registers. The control function for each
instruction is determined by the bit i (0-11) in the instruction register (IR).
These control functions are activated with the clock transition associated with
timing signal T3.

3. **Execution:** The actual execution of the instruction happens during the

clock transition associated with T3. The relevant microoperation is performed
on the registers as specified by the instruction.

4. **Sequence Counter (SC) Reset:** After the execution of a register-

reference instruction is completed at time T3, the sequence counter SC is
cleared to 0. This ensures that the next instruction in the sequence will be
fetched.

5. **Return to Fetch Phase:** The control unit then returns to the "Fetch"
phase to fetch the next instruction using timing signal T0.

Register-reference instructions include various operations like clearing

registers (CLA, CLE), complementing registers (CMA, CME), circular shifts (CIR,
CIL), incrementing (INC), and conditional skips (SPA, SNA, SZA, SZE).
Additionally, there's the HLT instruction that halts the computer's operation by
clearing a start-stop flip-flop (S).
These instructions allow the computer to manipulate data in its registers and
control the flow of the program based on certain conditions. The execution of
each instruction is synchronized with the clock signals and the sequence
counter SC to ensure proper operation and sequencing of instructions.
In the basic computer's instruction cycle, determining the type of instruction
occurs during the "Execute" phase, specifically at timing signal T3. Here's how
the control unit determines the instruction type and what actions are taken
based on that determination:

1. **Initial Configuration:** The process starts at the beginning of the

instruction cycle. Initially, the program counter (PC) is loaded with the address
of the first instruction in the program. The sequence counter (SC) is cleared to
0, indicating the start of the instruction cycle. The timing signal active after the
decoding phase is T3.

2. **Control Flow:** The control unit then proceeds to determine the type of
instruction by following a flowchart, as shown in Figure 5-9.

3. **Decoder Output D7:** The control unit checks the value of decoder
output D7. If D7 is equal to 1, this indicates that the instruction must be either
a register-reference or an input-output type.

4. **Memory-Reference or Not:** If D7 is equal to 0, this indicates that the

instruction's operation code falls into one of the seven values from 000
through 110. These values correspond to memory-reference instructions. In
this case, the control unit proceeds to determine if the instruction has an
indirect address.

5. **Inspecting Bit I:** The control unit inspects the value of the first bit of the
instruction, which is available in flip-flop I. If D7 is 0 and I is 1, this means that
the instruction is a memory-reference instruction with an indirect address.
6. **Handling Indirect Address:** If the instruction has an indirect address, the
control unit initiates a specific microoperation: AR (Address Register) is loaded
with the effective address from memory, symbolized by the register transfer
statement AR ← M[AR]. Initially, AR holds the address part of the instruction.
Reading the word from memory at the address in AR, and placing it on the
common bus, allows the indirect address (from the 12 least significant bits of
the memory word) to be loaded into AR. This process ensures that the
effective address is properly retrieved.

7. **Instruction Types and Execution:** Based on the determination of the

instruction type (register-reference or input-output), specific actions are taken
in the "Execute" phase:
- For memory-reference instructions, nothing additional needs to be done as
the effective address is already in AR.
- For register-reference instructions and input-output instructions, the actual
execution of the instruction is carried out in this phase.

8. **Sequence Counter (SC):** After the execution of the instruction is

completed at time T3, the sequence counter SC is cleared to 0. This ensures
that the computer is ready to fetch the next instruction.

9. **Return to Fetch Phase:** Control returns to the "Fetch" phase with timing
signal T0 activated, and the process continues to fetch, decode, and execute
the next instruction in the program.

This detailed process ensures that the control unit correctly identifies the type
of instruction and handles it accordingly during the instruction cycle. The
control unit's actions are synchronized with the timing signals and the
sequence counter SC to maintain the proper sequence of instructions.
Certainly! Here are detailed notes on the memory-reference instructions
discussed in the provided passage:

**Memory-Reference Instructions:**
Memory-reference instructions are a type of instructions in a computer
architecture that involve accessing memory. These instructions are specified in
terms of register transfer notation to define their precise function.

**Table 5-4: Memory-Reference Instructions**

1. **AND (D0):**
- Symbolic Description: `AC ← AC AND M[AR]`
- Microoperations:
- D0T4: Data read from memory to DR.
- D0T5: Perform AND operation between AC and DR, store result in AC, and
clear SC (Sequence Counter).

- Control Function:
- Uses operation decoder D0 when the instruction's AND operation has a
binary code value of 000.
- Execution:
- Timing signal T4: Operand is transferred from memory to DR.
- Timing signal T5: Result of AND logic operation between DR and AC is
transferred to AC, and SC is cleared.

2. **ADD (D1):**
- Symbolic Description: `AC ← AC + M[AR], E ← Cout`
- Microoperations:
- D1T4: Data read from memory to DR.
- D1T5: Perform addition between AC and DR, store the result in AC,
transfer the carry (Cout) to E, and clear SC.

- Control Function:
- Uses operation decoder D1.
- Execution:
- Timing signal T4: Operand is transferred from memory to DR.
- Timing signal T5: Result of addition between DR and AC is transferred to
AC, Cout is transferred to E, and SC is cleared.

3. **LDA (D2):**
- Symbolic Description: `AC ← M[AR]`
- Microoperations:
- D2T4: Data read from memory to DR.
- D2T5: Transfer the content of DR to AC and clear SC.

- Control Function:
- Uses operation decoder D2.
- Execution:
- Timing signal T4: Operand is transferred from memory to DR.
- Timing signal T5: Content of DR is transferred to AC, and SC is cleared.

4. **STA (D3):**
- Symbolic Description: `M[AR] ← AC`
- Microoperations:
- D3T4: Transfer the content of AC to memory at the effective address (AR)
and clear SC.

- Control Function:
- Uses operation decoder D3.
- Execution:
- Timing signal T4: Content of AC is written to memory at the effective
address (AR), and SC is cleared.
These instructions involve precise sequences of microoperations to execute
and manipulate data between the memory and registers in the computer
architecture. The control functions and microoperations are determined by the
specific operation decoder output associated with each instruction.
Certainly! The passage you provided describes the organization and execution
of memory-reference instructions in a computer architecture. Let's break down
the key points step by step:

**Table 5-4: Memory-Reference Instructions:**

- The table lists seven memory-reference instructions.
- Each instruction corresponds to a specific operation and is identified by a
decoded output signal, represented as Di for i = 0, 1, 2, 3, 4, 5, and 6. These
signals are generated by an operation decoder.
- The effective address of each instruction is stored in the address register AR.
This effective address is essential for determining which memory location to
access during the execution of the instruction.
- The placement of the effective address into the AR occurs at specific timing
signals:
- When I = 0, it happens during timing signal T2.
- When I = 1, it occurs during timing signal T3.
- The actual execution of memory-reference instructions begins with timing
signal T4.

**Symbolic Descriptions of Instructions:**

- Each instruction is described symbolically using register transfer notation.
These descriptions specify what each instruction does in terms of data
manipulation.

**Sequence of Microoperations:**
- To execute these memory-reference instructions, a sequence of
microoperations is required. Microoperations are fundamental operations that
manipulate data within the computer's registers.
- The reason for using a sequence of microoperations is that data stored in
memory cannot be directly processed. Instead, it must be read from memory
and transferred to a register where it can be manipulated using logic circuits.
- The passage provides detailed explanations for each instruction, including the
microoperations involved in their execution. These microoperations are
performed during specific timing signals.
- For example, for the "AND" instruction (D0), it specifies two microoperations
during timing signals T4 and T5 to read data from memory, perform the AND
operation, and update the accumulator (AC) register.
- The control functions that determine which microoperations to execute are
based on the decoded output signal (Di) associated with each instruction. For
instance, the control function for the "AND" instruction uses operation
decoder D0.
- Each instruction follows a specific sequence of microoperations, which are
coordinated by the control logic based on the instruction's decoded output.

**Flowchart:**
- The passage mentions the existence of a flowchart that summarizes all the
microoperations. Unfortunately, the flowchart is not provided in the text, but it
would likely illustrate the sequence of microoperations and how they are
controlled and coordinated during the execution of memory-reference
instructions.

In summary, the passage explains the organization and execution of memory-

reference instructions in a computer architecture, emphasizing the need for a
sequence of microoperations to manipulate data between memory and
registers and how control functions determine the microoperation sequence
based on decoded instruction outputs.
Certainly! Here are detailed notes on the "BUN" (Branch Unconditionally) and
"BSA" (Branch and Save Return Address) instructions described in the passage:

**BUN: Branch Unconditionally**

- **Purpose:** This instruction transfers control to the instruction specified by
the effective address without any condition or comparison. It allows for non-
sequential program execution, effectively implementing an unconditional
branch or jump.
- **Execution:** The instruction is executed with one microoperation:
- D4T4: PC (Program Counter) is updated with the value from AR (Address
Register), and SC (Sequence Counter) is cleared.
- **Explanation:**
- The PC holds the address of the next instruction to be fetched from memory
in the next instruction cycle.
- At the beginning of each instruction cycle, the PC is incremented at time T1
to prepare it for the next sequential instruction.
- The BUN instruction transfers control to the instruction at the address
specified by the effective address in AR.
- By resetting SC to 0, control is transferred back to the beginning (T0) of the
instruction cycle.
- **Result:** The next instruction is fetched and executed from the memory
address given by the new value in PC.

**BSA: Branch and Save Return Address**

- **Purpose:** This instruction is used for branching to a subroutine or
procedure within a program. It allows for the organization of code into
reusable and callable subroutines. The BSA instruction also saves the return
address.
- **Execution:** The instruction is executed with two microoperations:
- M[AR] ← PC: The address of the next sequential instruction (available in PC)
is stored in memory at the location specified by the effective address.
- PC ← AR * 1: The effective address plus one is transferred to PC, serving as
the address of the first instruction in the subroutine.
- **Explanation:**
- When the BSA instruction is executed, it saves the address of the next
sequential instruction (return address) in a memory location specified by the
effective address.
- It then updates the PC with the effective address plus one to point to the
first instruction in the subroutine.
- This operation effectively "jumps" to the subroutine.
- **Result:** The subroutine is executed starting from the address specified by
the effective address plus one.
- **Return to the Original Program:**
- To return to the original program after executing the subroutine, an indirect
BUN instruction is typically placed at the end of the subroutine.
- The indirect BUN instruction reads the effective address stored at the
specified location, which contains the previously saved return address.
- When executed, the effective address is transferred to PC, allowing control
to continue executing the instruction at the return address.

**Subroutine Call and Return:**

- The BSA instruction serves as a subroutine call, and the indirect BUN
instruction at the end of the subroutine serves as a subroutine return.
- In commercial computers, return addresses associated with subroutines are
often stored in processor registers or in a memory region known as a stack.
Certainly! Here are detailed notes on the provided text about combinational
circuits and the design of a half-adder circuit:

**Combinational Circuits Overview:**

- Combinational circuits are a type of digital logic circuit characterized by the
absence of feedback paths from outputs to inputs, and they do not possess any
form of memory.
- They are distinguished from sequential circuits, which do have feedback paths
and memory elements.
- Combinational circuits consist of interconnected logic gates with inputs and
outputs, and the outputs are solely determined by the current binary values of
the inputs.
- These circuits play a crucial role in digital computers, enabling them to make
binary control decisions and perform data processing tasks.
**Representation of Combinational Circuits:**
- Combinational circuits can be represented by a truth table, which shows the
binary relationship between input and output variables.
- Alternatively, they can be represented by Boolean functions, with one
function for each output variable. These functions express output values in
terms of input variables.

**Designing Combinational Circuits:**

The design process of a combinational circuit involves the following steps:
1. Problem Statement: Define the problem to be solved.
2. Variable Assignment: Assign letter symbols to input and output variables.
3. Truth Table Derivation: Create a truth table that defines the relationship
between inputs and outputs.
4. Boolean Function Simplification: Obtain simplified Boolean functions for
each output.
5. Logic Diagram: Draw the logic diagram of the circuit.

**Example: Designing a Half-Adder Circuit:**

- A half-adder is a basic digital arithmetic circuit used for binary addition of two
bits.
- It has two input variables (augend and addend) and two output variables
(sum and carry).

**Half-Adder Truth Table:**

- The truth table for a half-adder is provided, showing the relationship between
input bits (x and y) and output bits (S and C).
- The carry bit (C) is 0 unless both input bits are 1, while the sum bit (S)
represents the least significant bit of the sum.
**Boolean Functions for Half-Adder:**
- The Boolean functions for the outputs of the half-adder are derived from the
truth table:
- S = x⨁y (Exclusive OR operation between x and y)
- C = xy (AND operation between x and y)

**Logic Diagram for Half-Adder:**

- A logic diagram for the half-adder is presented, consisting of an Exclusive-OR
(XOR) gate for the sum and an AND gate for the carry.
- This simple logic module can also be used to implement universal logic gates
like NAND and NOR.

In summary, this passage introduces combinational circuits, explains their

representation using truth tables and Boolean functions, and provides a step-
by-step guide to designing such circuits with a practical example of a half-
adder circuit.
Certainly! Here are detailed notes on the provided text about control memory
and microprogrammed control:

**Control Unit in a Digital Computer:**

- The Central Processing Unit (CPU) of a digital computer consists of various
functional units, including the control unit.
- The primary function of the control unit is to initiate sequences of
microoperations, which are fundamental operations performed by the CPU.
- The number of available microoperations is finite, and the complexity of the
digital system is determined by the number of microoperation sequences it can
perform.

**Two Methods of Implementing Control Unit:**

1. **Hardwired Control:**
- In hardwired control, control signals are generated using fixed instructions,
fixed logic blocks (e.g., AND/OR arrays), encoders, decoders, and other fixed
hardware elements.
- Characteristics of hardwired control include high-speed operation,
costliness, relative complexity, and a lack of flexibility in adding new
instructions.
- Example CPUs with hardwired control include Intel 8085, Motorola 6802,
and some RISC (Reduced Instruction Set Computer) CPUs.

2. **Microprogrammed Control:**
- Microprogramming is an alternative method for designing the control unit
of a digital computer.
- It involves using microinstructions to systematically control sequences of
microoperations.
- CPUs with microprogrammed control include Intel 8080, Motorola 68000,
and many CISC (Complex Instruction Set Computer) CPUs.

**Control Variables and Control Words:**

- Control functions that specify microoperations are binary variables, where
one binary state (0 or 1) corresponds to executing a particular microoperation.
- These control variables are used to select paths in multiplexers, decoders,
and arithmetic logic units in a bus-organized system.

**Microprogrammed Control Unit:**

- A control unit with binary control variables stored in memory is called a
microprogrammed control unit.
- Control memory contains microinstructions, where each microinstruction
specifies one or more microoperations for the system.
- A sequence of microinstructions constitutes a microprogram.
- Control memory is often implemented as a read-only memory (ROM) because
the microprogram is fixed during hardware production.
- Microprograms can be used for controlling operations within the CPU.
**Dynamic Microprogramming and Writable Control Memory:**
- Dynamic microprogramming allows loading microprograms from auxiliary
memory sources (e.g., magnetic disks).
- Control units using dynamic microprogramming may employ writable control
memory, which allows changing the microprogram.
- This type of memory can be both read and written, but it is primarily used for
reading.
- A computer with a microprogrammed control unit typically has two separate
memories: main memory (for user programs and data) and control memory
(for microprograms).

**General Configuration of a Microprogrammed Control Unit:**

- A block diagram demonstrates the organization of a microprogrammed
control unit, including control memory (usually ROM), control address register,
control data register (pipeline register), and a next-address generator
(sequencer).
- The control memory stores microinstructions, and the control address
register specifies the address of the microinstruction to be read.
- The control data register holds the present microinstruction while the next
address is computed.
- The next address generator (sequencer) determines the address sequence for
reading from control memory, and it can perform functions like incrementing
the control address register, loading an address from control memory,
transferring an external address, or initializing control operations.

**Advantages of Microprogrammed Control:**

- Microprogrammed control offers the advantage of flexibility. Once the
hardware configuration is established, changes in control sequences can be
achieved by specifying a different set of microinstructions without altering the
hardware.
**Note on RISC Architecture:**
- It's worth noting that most computers following the Reduced Instruction Set
Computer (RISC) architecture tend to use hardwired control instead of
microprogrammed control.

In summary, this passage explains the concepts of control memory and

microprogrammed control, including the advantages of microprogramming,
the components of a microprogrammed control unit, and the difference
between hardwired control and microprogrammed control in digital
computers.
INPUT OUTPUT OPERATIONS LEFT