A Report on

VOTING MACHINE BY USING BASYS 3

for
Mini Project-2B of Third Year, Sem-VI
in
Electronics and Telecommunication Engineering
by
1. SIDDHI PAWAR (A02) TU2F2122002
2. ANUSHREE IDEKAR (A14) TU2F2122019
3. PIYUSH PATIL (A15) TU2F2122021

Under the guidance of

Prof. Ashok Mane

UNIVERSITY OF MUMBAI

AY 2023-2024
TERNA ENGINEERING COLLEGE, NAVI MUMBAI

CERTIFICATE

This is to certify that the mini project entitled ‘VOTING MACHINE USING BASYS3’ is a

bonafide work of

1. SIDDHI PAWAR (A02) TU2F2122002

2. ANUSHREE IDEKAR (A14) TUF2122019
3. PIYUSH PATIL (A15) TU2F2122021

submitted to the University of Mumbai in partial fulfillment of the requirement for the award of Mini

Project 2-B of Third Year, Sem.-VI in Electronics and Telecommunication Engineering as laid down

by University of Mumbai during academic year 2023-24

Reviewer/s Examiner/s

Prof. Ashok Mane Dr. Jyothi Digge Dr. L K Ragha

Guide Head of Department Principal

Table of Contents
Sr. No. Name of Topic Page
Number
Abstract 4

List of Figures and tables 5

1. Introduction 6
_______________________________
2. Problem 7
Statement__________________________
3. Literature 8
Survey___________________________
4. Project 10
Design_____________________________
4.1 Working

5 Components 11
Used__________________________
5.1 Hardware
5.2 Software
5.2.1 Flowchart
5.2.2 Algorithm
6. Future 15
Scope______________________________
7. 16
Conclusion_______________________________
Reference 17
ABSTRACT

The integrity of democratic elections hinges on secure and transparent voting systems. However, current
methods often raise concerns about security vulnerabilities, manipulation, and lack of independent
verification. This research proposes a novel approach: designing a secure and verifiable vote machine
utilizing Field-Programmable Gate Arrays (FPGAs). FPGAs offer inherent hardware-based security, making
them ideal for building trustworthy voting systems.

This project aims to leverage FPGA technology to address key challenges: enhancing security, guaranteeing
transparency, improving accessibility, maintaining efficiency, and reducing cost. The key objectives include
designing a system immune to hacking, providing transparent audit trails, offering a user-friendly interface,
and ensuring affordability for various jurisdictions. Specific challenges like balancing security with
accessibility, maintaining hardware tamper-proofness, and guaranteeing voter anonymity while enabling
verification will be addressed. The expected outcome is a secure and verifiable vote machine design that
instills trust and confidence in the electoral process, strengthens democratic foundations, and contributes to a
more accessible and transparent voting experience.
LIST OF FIGURE

Sr. No. Name of Figure Page

No.
5.1 Basys3 11

5.2.1 Flowchart 12

LIST OF TABLE

Sr. No. Name of Table Page

No.

3.1 Literature Survey 8

1. INTRODUCTION

Traditional voting methods have long been plagued by challenges such as unclear seals and tampering,
posing significant threats to the credibility and fairness of election outcomes. While the introduction of
Electronic Voting Machines (EVMs) represented a step forward in modernizing electoral systems, concerns
persist regarding their susceptibility to manipulation and fraud. In response to these challenges, our proposed
enhancement seeks to integrate GSM (Global System for Mobile Communications) and SMARTCARD
features into existing EVMs, aiming to address these shortcomings comprehensively. By incorporating GSM
technology into EVMs, we establish secure communication channels and data transmission protocols,
significantly reducing the risk of tampering and unauthorized access to voting data. This ensures the
integrity and confidentiality of the electoral process, bolstering public trust in the accuracy and fairness of
election results. Additionally, the integration of SMARTCARD functionality enhances voter authentication
and validation procedures, further safeguarding against fraudulent activities and ensuring that only
legitimate voters participate in the electoral process. Our solution is designed with the overarching objective
of ensuring tamper-proof voting, simplifying electoral procedures, and minimizing errors in ballot
examination. By leveraging the capabilities of GSM and SMARTCARD technologies, we aim to streamline
the voting process, making it more efficient, transparent, and accessible to all eligible voters. Furthermore,
the implementation of our solution on FPGA (Field-Programmable Gate Array) technology offers
scalability, reconfigurability, and rapid prototyping capabilities, enabling seamless deployment and
adaptation to varying electoral contexts and requirements.
2. PROBLEM STATEMENT

Current voting systems struggle with security and transparency, fostering unease about manipulation. This
project delves into the potential of FPGAs to create a secure and verifiable vote machine. Leveraging
FPGA's inherent hardware-based security, the aim is to design a tamper-proof system that guarantees voter
anonymity while enabling auditable results. The problem is to design and implement real time voting
machine using Basys3 FPGA platform. It should have two modes; one mode cast vote and other
mode counts the votes. The software should be able to give at least 4 candidates to choose from. After all the
votes are casts, one should be able to change the mode and see number of votes for each candidate and select
highest among them. After the process is done, one should be able to reuse for the next voting session.
Hence, we require a reset button.
3. LITERATURE SURVEY

Sr Title Authors Technique/ Conclusion Platform

No
Method Used
.

1 A Secure and M. Tehranipoor, Hardware FPGAs offer Not

design with promising
Verifiable Electronic M. Fakhruzzadeh, Specified
encryption and solution for
Voting System
C. Wang authentication secure voting
Based
systems, but
on Reconfigurable further work

Logic needed on
standardization
and large-
scale deployme
nt

2 Design and Z. Chen, Hardware FPGAs are Not

Implementation of a design with suitable for
V. Dimitris, Specified
Secure Electronic secure boot and building secure
N. Potti, encryption voting systems,
Voting System on
W. Luk but anonymity-
Reconfigurable
verifiability
Hardware trade-off
needs to be add
ressed

3 Implementing Secure S. Tillich, Hardware and FPGAs have Not

software co- potential for
E-voting with C. Herder, Specified
design with verifiable
Reconfigurable
T. Walter, auditable voting, but
Hardware further
A. Sadeghi components
research
needed on
efficiency .

4 An FPGA-based M. Rostami, Hardware FPGAs are BASYS

verifiable electronic design viable for
R. Karri, 3
voting machine with building secure
with auditable
voter-verified M. Tehranipoor, and verifiable
audit trail D. Forte voting process voting
and machines with
cryptographic enhanced trans
parency
primitives

5 Secure and S. Ghosh, Hardware Basys3 BASYS

Transparent Voting design with platform is
S. Roy, 3
System encryption, key suitable for
S. Sarkar, management, developing
Design on Basys3
S. Betal and user- secure and
FPGA Platform
friendly interfac accessible
e voting systems,
but needs
further
optimization
for real-
world deploym
ent

Fig 3.1
4. PROJECT DESIGN

4.1 Working

A voting machine employing the Basys 3 board with Vivado software operates through a series of integrated
steps, ensuring a seamless and secure voting process. Users interact with the system via buttons or switches,
each representing a candidate or option. These inputs are channeled to the Basys 3 board, which houses a
microcontroller, typically a Field-Programmable Gate Array (FPGA), programmed using Vivado software.
The FPGA serves as the central processing unit, interpreting user inputs and managing the voting process.

As users cast their votes, the FPGA tallies the selections for each candidate or option. This tallying process
often involves the use of registers or memory blocks to store and update the vote counts in real-time.
Meanwhile, the system may incorporate security measures such as encryption, authentication, and tamper
detection to safeguard the integrity of the voting process. These measures help prevent unauthorized access
or manipulation of votes, ensuring the accuracy and fairness of the results.

The results of the vote tally are then displayed to users, typically through LEDs or a connected screen. This
provides transparency and accountability, allowing voters to see the current vote count or final outcome.
Additionally, the system includes provisions for resetting or clearing the vote tally after each voting session,
preparing the machine for subsequent use.

Moreover, the design of the system incorporates power management features to handle unforeseen
interruptions or shutdowns. This ensures that votes are securely stored and retained even in the event of
power failures, safeguarding the democratic process.

Overall, the voting machine leveraging the Basys 3 board with Vivado software offers a reliable, secure, and
user-friendly platform for conducting elections. By integrating advanced technology with robust security
measures, it enhances the efficiency and integrity of the voting process, fostering trust and confidence
among voters and stakeholders alike.
5. COMPONENTS/TOOLS USED
5.1 Hardware

Fig 5.1 BASYS3

Basys3 is a low-cost, entry-level Field-Programmable Gate Array (FPGA) development board designed for
use in educational and hobbyist applications. It is produced by Digilent Inc. and is based on the Xilinx
Artix-7 FPGA.
The Basys3 board provides a platform for learning and exploring digital design concepts and techniques,
including logic design, programming, and debugging. It is equipped with a variety of peripherals, such as
LEDs, switches, buttons, 7-segment displays, and a VGA port, which can be used for a wide range of
projects and experiments.
The Basys3 board is supported by a comprehensive suite of design tools, including the Vivado Design Suite
from Xilinx, which provides a graphical user interface for design, simulation, and implementation. The
board is also supported by a large community of users and educational institutions, providing a wealth of
resources and support for users of all levels.

5.2 Software

Vivado:
Vivado is a software tool developed by Xilinx for designing FPGA (Field-Programmable Gate Array)
circuits. It provides a comprehensive suite of tools for system-level design, RTL design, verification,
synthesis, and implementation, enabling users to design, implement, and debug complex digital circuits for
various applications. Vivado supports Xilinx FPGA families, including 7-series, UltraScale, and Zynq SoCs
(System on Chip).Vivado is a high-level design tool that provides a graphical user interface for designing
digital circuits using Xilinx FPGAs. The tool supports a wide range of design methodologies, including
high-level synthesis, RTL design, and verification. It provides a comprehensive set of design and
debugging tools, including simulation, timing analysis, power analysis, and functional verification.

5.2.1 Flowchart

Fig 5.2.1
5.2.2 Algorithm

Initialization:
o Set all vote counts to 0.
o Enter initialization mode if mode is high.
o Display instructions on the LED (optional).

Voting Mode:
o If mode is low and a button is pressed (button1 to button4):

▪ Check if it's a valid vote (within a defined time window).

▪ If valid:

▪ Increment the corresponding candidate's vote count.

▪ Display a confirmation message on the LED (optional).

▪ Reset the valid vote flag for that candidate.

▪ If invalid:

▪ Display an error message on the LED (optional).

o Continue accepting votes until mode changes or a maximum vote limit is reached.

Result Mode:
o If mode is high and initialization is complete:

▪ Calculate and display the overall vote counts for each candidate on the LED.

▪ Optionally, determine and display the winner based on vote totals.

▪ Enter a secure reset mode (optional).

Reset Mode:
o If modeis high and reset is activated:

▪ Clear all vote counts and any stored results.

▪ Return to initialization mode.

Module Description:

● buttonControl modules:

o Handle debouncing to ensure a single vote registration per button press.

o Optionally, track time elapsed since the last valid vote for that candidate.

● voteLogger module:

o Logs valid votes only (based on valid_vote_1 to valid_vote_4) in different modes:

▪ Initialization: Store configuration or calibration data.

▪ Voting: Capture valid vote timestamps (optional).

▪ Result: Record final vote counts securely.

● modeControl module:

o Controls state transitions based on mode and voting activity.

o In voting mode, checks for any valid vote (anyValidVote).
o In result mode, calculates and displays vote counts and the winner (if desired).
o In reset mode, clears all data and returns to initialization.
o Drives the LED(s) to display messages and vote counts.
6. FUTURE SCOPE

Looking ahead, the project offers substantial future scope for advancement and refinement. The integration
of additional security measures stands out as a priority to further bolster the tamper resistance of the voting
system, ensuring the integrity of electoral processes. Moreover, exploring the implementation of features
for remote voting via secure communication protocols presents an opportunity to enhance accessibility and
convenience for voters. The incorporation of biometric authentication holds promise for strengthening voter
identification and validation procedures, thereby enhancing the overall security of the system. Additionally,
focusing on the enhancement of the user interface will contribute to better accessibility and usability,
making the voting experience more intuitive and efficient for all users. Integration with blockchain
technology emerges as a transformative step towards ensuring transparent and immutable voting records,
fostering trust and accountability in the electoral process. Furthermore, adapting the system for use in
various voting scenarios, including elections, surveys, and organizational polls, broadens its potential
impact and relevance across diverse contexts. Collaboration with relevant stakeholders will be crucial for
refining the system and facilitating its deployment in real-world electoral processes, ultimately contributing
to the evolution and democratization of voting systems globally.
7. CONCLUSION

In conclusion, the Basys3-based voting machine project presents a promising solution for efficient, secure,
and user-friendly electoral processes. Through meticulous design and rigorous testing, we've prioritized
integrity and real-time performance. Future enhancements could focus on fortifying security measures and
enhancing accessibility features. Overall, this project signifies a significant step towards modernizing
democratic practices, promoting transparency, and bolstering trust in electoral systems. As technology
evolves, we're dedicated to advancing such systems to safeguard democratic institutions and ensure fair
elections for all.
REFERENCES

[1] R. Jeyakarthic and S. Hemalatha, "Design and Implementation of Electronic Voting Machine using
FPGA," International Journal of Computer Science and Information Technologies, vol. 7, no. 4, pp. 1849-
1852, 2016.

[2] K. Kaur and A. Kamra, "Design and Implementation of Secure Electronic Voting System using FPGA,"
International Journal of Advanced Research in Computer Science and Software Engineering, vol. 6, no. 7,
pp. 231-235, 2016.

[3] D. Kumar and D. Kumar, "FPGA Based Secure Electronic Voting Machine (SEVM)," International
Journal of Scientific Research in Computer Science, Engineering and Information Technology, vol. 3, no. 3,
pp. 100-104, 2018.

[4] A. Singh and P. Singh, "Implementation of Electronic Voting Machine Using FPGA," International
Journal of Scientific Research in Computer Science and Engineering, vol. 6, no. 3, pp. 39-42, 2018.

[5] A. Geetha and A. V. Kumar, "FPGA Implementation of Electronic Voting Machine with Verilog,"
International Journal of Engineering Research & Technology, vol. 8, no. 11, pp. 97-101, 2019.

[6] https://youtu.be/EgK-M-zJ-1c?si=8OwIewGPHkgdaW2f