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sscpu

The document presents a series of registers and their values during different cycles of a computing process, including instruction fetch and execution phases. It outlines the status of various registers such as IR, DR, AC, IX, PC, and MAR, along with their corresponding operation codes. Additionally, it details the operation class instructions and their effects on the accumulator and index registers.

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Tommaso Parodo
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0% found this document useful (0 votes)
4 views

sscpu

The document presents a series of registers and their values during different cycles of a computing process, including instruction fetch and execution phases. It outlines the status of various registers such as IR, DR, AC, IX, PC, and MAR, along with their corresponding operation codes. Additionally, it details the operation class instructions and their effects on the accumulator and index registers.

Uploaded by

Tommaso Parodo
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as XLS, PDF, TXT or read online on Scribd
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6

2
4110 Saved Next Fetch Cycle Execute Cycle
7 Cycle Execute Fetch Execute Fetch
5 IR 0 0 0 0
3003 DR 1 1 0 1
1 AC -5 -5 -5 -5
IX 6 6 6 6
PC 8 7 9 7
10 MAR 9 8 9
-1 Write En 0 0 0
-2 MDWrite 0 0
-3 MDRead 0
-4
-5 Opcode 0
-6 Mode 0

MaxOpcode 6
MaxOperate 7
MaxCycle 2
Phase
Register Result
Cycle Execute
IR 0
DR 0
AC -5
IX 6
PC 9
MAR 8
Write En 0
Execute Operate Load Store Jump Add Sub LoadIX
Cycle Opcode Opcode Opcode Opcode Opcode Opcode Opcode
Register Result 0 1 2 3 4 5 6
Cycle Fetch
IR 0
DR 1
AC -5 -5 0 -5 -5 -5 -5 -5
IX 6 6 6 6 6 6 6 1
PC 7 7 8 8 1 8 8 8
MAR 9 9 1 1 1 1 1 1
Write En 0 0 0 1 0 0 0 0
MDWrite 0 -5

Operate Class Instruction Decoding


Operation No Op Stop Clear AC Negate Skip if zeroSkip if negati Clear IX Increment IX
Code 0 1 2 3 4 5 6 7
AC -5 -5 0 5 -5 -5 -5 -5
IX 6 6 6 6 6 6 0 7
PC 8 7 8 8 8 9 8 8

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