Name Client Project Status

Elavarasan Chokkalingam TI AEP PFI

1.added v refine files(with the help of
script) and verified the modules(five
modules).
2. Review was done and designer gave
green flag to close the modules.
3. Supporting Chaithra(Lead) to review
and verify all other modules and reports
for closure(ongoing).
Amee Darphan Rathod going through axi protocol
Anburaja Shanmugam Rambus CMRT 1)Added new testcases for coverage of HC
block.(Done)
2)Added refine files for HC and KTC
blocks.(Done)
3)Working on creating new test cases for
coverage of KTC block.(In progress)

Ansia Liji Nil Training 1)Learning I3C protocol and working on

developing verification env
Rohit Samuel Ronald Rambus EIP125 1) Added Monitor updates related to
Chacha20 algorithm core.
2) Added sequence(slave) and Testcases
for Chacha20 core.
3)Working on adding sequence and new
testcases for POLY1305 algorithm core.

Sheril Kiruba Richard sigmasense Training 1. Created verification env 2.

Debbugged the testcases for spi in azurite
soc 3.
Debbugged testcase for qspi in calcite soc
4.
worked on c testcases for spi in soc
verficiation with Azurite and cacite
processor
5.Working on developing PCIe verification
environment
Anirban Guha
Janakiraman Balraj ST Pinnacles Learing SPEC for Improving ADC TB.
Sindhu Guddampally Rambus DRBG 1) Continued analysing code coverage for
AES_4 .
2)Exclusion and uncovered signals report
preparation for AES_4.
3) Tried new scenarios to cover
uncovered signals in AES_4.
4)Started analysing code coverage for
AES_16.
5)Exclusion and uncovered signals report
preparation for AES_16.
Name Client Project
Elavarasan Chokkalingam
TI AEP PFI

Amee Darphan Rathod

Anburaja Shanmugam Rambus CMRT

Ansia Liji Nil Training

Rohit Samuel Ronald Rambus EIP125

Sheril Kiruba Richard sigmasense Training

Anirban Guha ST Ukulele

Janakiraman Balraj ST Pinnacles

Sindhu Guddampally Rambus AES

Status
1.working on document preparation for each module for closure
2.Supported Chaithra(Lead) to review and verify all other modules 3.
supporting another project on debugging McASP module PARTL runs which
i was worked previously
working on spi environment
1)Added assertion and covergroups updates for KTC coverage. 2)Added
testcases to cover the uncovered bins. 3)Updated refine file
for KTC 4)Working on SIC coverage
1)Created verification environment for I3C 2)Working
on testcases for I3C
1. Created Dma and Slave sequence for Poly1305 algorithm.
2. Created and verified testcases for Poly1305 algoritm for Non-AEAD
operations.
3. Working on sequnce modification and testcase creation for AEAD
operations.

1. Created verification env 2.

Debbugged the testcases for spi in azurite soc
3. Debbugged testcase for qspi in calcite soc
4. worked on c testcases for spi in soc verficiation with Azurite and
cacite processor
5.Working on developing PCIe verification environment

Understanding of LSADC.
1. Worked on ADC scoreboard improvement.
2. Adding missing ADC SVA.
3. Working with missing checkers in NVM Avalon bridge.
1. completed the code coverage analysis on AES_4 and AES_16.
2. Exclusion and uncovered signals report was shared to designer for
review.
3. Started on reading specification for AES_DPA_4 project.
4.Running regressions and merging for code coverage analysis.
4. started on analysing the code coverage for AES_DPA_4 project.
Name Client Project
Elavarasan Chokkalingam

TI TDA54

Anburaja Shanmugam Rambus CMRT v2

Ansia Liji COE AI

Prompting
and
Vlidation

Rohit Samuel Ronald Rambus EIP161

Sheril Kiruba Richard ST Avedon

Anirban Guha ST Barolo

Janakiraman Balraj ST 1.
Pinnacles
2. Farosh

Sindhu Guddampally Rambus AES TB- SV

Rajanna to UVM
conversion
Status
1.Working on new project TDA54(Total 12 modules has been assigned
with 3 engineers(buffer))
2.Started reading Specs and understanding the features to be test in SoC
level
3. Supporting buffers for creating the test plan and helping them to
understand about the requirements.
4.Created testplan for the assigned modules and prepared PPT for the
testplan review which has been scheduled with designers in the
upcoming weeks.
5.I have given 3 overview Sessions to the whole team to make them
understand about the TI SOC flow and the corresponding Environment
which can help new joiners to ramp up rapidly on the TI Flow.

1.Created Testplan and completed the TP review for PUF core.

2.Working on creating Test cases, Predictor, Assertions and Coverage for
PUF core as per testplan.
3.Working on TB updates for integration of PUF core to CMRT v2.
1. Generate feature list for various clients including Infineon, Metanoia,
OpenHW, STM, Renesas etc.. along with test case descripption,
pass,fail,criteria,assertion and coverage. 2.Validation of
generated features and code for assertion and coverage

1. Added and tested Latency checker for EIP62

2. Completed testing Statistics counter checkers for SA
counters,Interface counters and working on testing Secy counters.
3. Worked on debugging EIP62 Ingress regression failures
1.Worked on developing AFC uvc and dither counter for bubo controller
2. Developed testcases , checkers for AFC
3. completed attribute planning and feature list extraction
4. Worked on debugging the chip top pins and filed the bug
Regression and coverage closure
Pinnacles:
1. Working in A2D connectivity checks.
2. Working in RCCU, PGND and SOC top CC closure
3.worked on Regression clean up
Farosh:
1. Worked on Attribute and DV stratergy developement.

In AES,there are 3 modes -ECB,FBC,AE modes .Faultinjector in addition to

it.In SV,we have separate SV files for all these modes.
1.Converted the separate files in SV to UVM merging files of different
modes into single file.
2.updated uvm_driver,uvm_monitor,uvm_scoreboard and all other files
to support different modes of operation.
3.Sequence files and configuration files are updated to support different
modes.
4. AES_ECB_4_STD,AES_ECB_16_STD modes are clean .
5.Debugging failures on other configurations.
Name Client Project
Elavarasan
Chokkalingam

TI TDA54

Anburaja Shanmugam Rambus CMRT v2

Ansia Liji COE AI Prompting and

Vlidation

Rohith Samuel Ronald Rambus EIP161

Sheril Kiruba Richard ST Avedon

Anirban Guha ST Barolo

Janakiraman Balraj ST 1. Pinnacles
2. Farosh

Sindhu Guddampally Rambus AES TB- SV to UVM

Rajanna conversion
Status
1.DMPAC Module Testplan review was successfully done and
working on Action items.
2.Supporting McASP and ATL module Testplan development
and had a internal review.
3.Reading specs for VPAC and NPAC module for Testplan
development.
4.Ramping up the new folks on TI Flow and having query
sessions everyday which gives good interacting session with
team

1) Creating assertions and coverage for PUF core.

2) Working on new testcases for PUF core,
- 10/15 Tests are created but not validated because of design
bug. Bug is reported and Jira ticket is raised. Waiting for
designer to fix.
- 5 Tests are in progress.

1. Generate feature list for OpenHW and AXI4.

2.Validation of generated features and code for assertion and
coverage
1. Worked on Statistics counter checker testing.
2. Worked on Backdoor access for statistics counter register for
comparison.
3. Worked on EIP62 regression failure.
1.Worked on AFC testcases for corner cases, error scenario
implementation
2. Worked on Dither controller sample test case
implementation
3. Worked on AFC assertion for INTL pin and uvc development
(implementation)

Regression and coverage closure

Pinnacles:
1. Working on CC closure.
2. Working on A2D failure fix.
3. Regression failure fix.
Farosh:
1. Worked on DV stratergy developement.
2. Started TB developement by writing clock UVC.

1.Regression failures cleanup on AES_ECB_DPA.

2.Regession failures cleanup for AES_AE_DPA.
3.Working on debug of failures on fault injection.
Name Client Project
Elavarasan
Chokkalingam
TI TDA54

Anburaja Rambus
Shanmugam

Ansia Liji COE AI Validation

Rohith Samuel Rambus EIP161

Ronald
Sheril Kiruba ST Avedon
Richard

Anirban Guha ST Barolo

Janakiraman 1. Pinnacles
ST
Balraj 2. Farosh

Sindhu Rambus AES TB- SV to

Guddampally UVM conversion
Rajanna
Status
1.DMPAC Module Testplan review action items are done.
2.McASP module testplan review was done and working on AI's .
3.Reading specs for VPAC and NPAC module for Testplan development.
4.Supporting ATL and DCC module understanding and flow for Testplan
review(Scheduled on next Monday)

1) Working on TB updates, assertions and coverage

2) Testcases for PUF core,
15/15 Tests are created but not validated because of design bug. Bug is
reported and Jira ticket is raised. Waiting for designer to fix.

1.working on python script to generate Excel sheet with features from Spec
for AI automation.
2.Worked on RISCv testcases with assertion for openHW riscv debug support.
3.Validation of assertify tool to generate assertions with signal
mapping
1. Worked on Statistics counter monitor

1.Worked on AFC testcases for corner cases, error scenario implementation

2. Worked on Dither controller sample test case implementation
3. Worked on AFC assertion for INTL pin and uvc development
(implementation)
Closure of TO checklist items.
Pinnacles:
1. Worked on Fixing failures in A1 ECO fix RTL.
2. Worked on CC closure.
Farosh:
1. Working on SVA creation.
2. Working on clk uvc developement

1.Failures have been fixed on all STD,DPA,FIA versions of AES.

Name Client Project
Elavarasan
Chokkalingam
TI TDA54

Anburaja Rambus CMRT PUF

Shanmugam
Ansia Liji COE AI Validation

Rohith Samuel Rambus EIP161

Ronald

Sheril Kiruba ST Avedon

Richard

Anirban Guha ST Barolo

Janakiraman 1. Pinnacles
ST
Balraj 2. Farosh

Sindhu Rambus AES TB- SV to

Guddampally UVM conversion
Rajanna
Status
1.McASP and ATL modules testplan review was done and working on AI's .
2.Supporting NPAC(new module) module for Review(wednesday).
3.Reading specs for VPAC module for Testplan development.
4.Supporting DCC module for closing Action items
1. Implemented PUF predictor, assertions, coverage & Testcases. Waiting for
input from designer to fix design bugs and final RTL files.
1. worked on generating ASM testcases using AI for openHW riscv debug
support. 2.worked on
manual validation of the generated testcases
1. Worked on implementing Backdoor peek for Statistics counter register.
2. Worked on adding checker for Statistics counter.
3. Working on Latency checker implementation.
1.Worked on AFC testcases for corner cases, error scenario implementation
2. Worked on Dither controller sample test case implementation
3. Worked on AFC assertion for INTL pin and uvc development
(implementation)
On leave
Pinnacles
1. Worked on A1 failure fixes.
Farosh:
1. Working on SVA creation.
2. Developing TB to generate clock for RTL.

Implementation and verification of feedback of designer on AES UVM TB.

1. Implementing separate performance monitor.
2. Implementing separate FIA scoreboard and FIA monitor.
Name Client Project
Elavarasan Chokkalingam
TI TDA54

Anburaja Shanmugam Rambus CMRT & Fuji

Ansia Liji COE AI Validation

Rohith Samuel Ronald Rambus EIP161

Sheril Kiruba Richard ST Avedon

Anirban Guha ST Barolo

1. Pinnacles
Janakiraman Balraj ST
2. Farosh

Sindhu Guddampally Rambus AES TB- SV to

Rajanna UVM conversion
Status
1.NPAC testplan review was successfully done .
2.Working on McASP,DCC2, ATL,DMPAC and NPAC modules Action Item closure for Testplan.
3.Reading specs for VPAC module for Testplan development.
4.Going through the 7 more Analog modules specs for testplan review
CMRT:
- TB updates for the PUF integration to CMRT,
• Validated the fix by designer for RTL bug.
• Waiting for new RTL files from designer.
Fuji:
- Ramping up on Fuji spec.
- Ramped up on KIC block and drafted a testplan for KIC.

1. Worked on generating and validating RISCV testcases for openHW (CV32E40S core) 2.
Worked on debugging RISCV testcases.
1. Worked on Verifying Statistics Monitor updates.
2. Worked on Latency checker Monitor support.
3. Modified and updated files for Natural DOCs for upcoming release.
4. Gave KT on EIP338.
1.Worked on AFC testcases for corner cases, error scenario implementation
2. Worked on Dither controller sample test case implementation
3. debugged afc testcase
4. worked on mdr presentation
On leave
Pinnacles
1. Worked on A1 failure fixes.
2. Worked on RFI#8 checker creation and FC updation.
3. Identified and worked on cousin Bug of ECO#35.
Farosh:
1. Working on SVA creation.
2. Updating Attribute sheet as per latest DOS.
3. Worked on PLL prediction

1. Running regressions for coverage closure.

2.Working on clean up of uvm database - indentation,scripts .
Name Client Project
Elavarasan Chokkalingam

TI TDA54

Anburaja Shanmugam Rambus FUJI

Ansia Liji COE AI Validation

Rohith Samuel Ronald Rambus EIP161

Sheril Kiruba Richard ST Avedon

Anirban Guha ST Barolo

1. Pinnacles
Janakiraman Balraj ST
2. Farosh

Sindhu Guddampally Rambus AES -FUJI

Rajanna
Status
1.Supported IP team to hack RTL for temporary fix.
2.Working on McASP,DCC2, ATL,DMPAC and NPAC modules Action Item closure for Testplan.
3.Reading specs for VPAC module for Testplan development.
4.Ramping up new joineers for analog modules and going through the 6 Analog modules specs for
testplan review

1. Ramped up on Fuji spec.

2. Ramped up on BCU block and Testplan.
3. Working on creating testcases based on Testplan.
1.Generated 39 RISCV ASM testcases for riscv debug support(CV32E40S core) in openHW .
2.Simulating and debugging ASM testcases using Questasim.
3.Working on validation of AIautomation tool for feature list extraction
1. Debugged the failures due to Statistics counter monitor updates in both UVM and Python
environment.
2. Worked on Latency checker update for Pre-empt frames for fixed latency.
3. Helped team to complete the final phase of beta release.
1.Worked on AFC testcases for corner cases, error scenario implementation
2. Worked on Dither controller sample test case implementation
3. Worked on verifying the afc and dither block
4. started coverage implementation
5.started regression work on these blocks

Discussions on TB improvement.
Pinnacles:
1. Worked on testcase failures.
2. Worked on uncovered CC and FC.
Farosh:
1. Worked on clk generation with jitter.
2. Worked on SVA and Monitor developement.

1.Going through the Spec of AES -FUJI project.

2.Working on integration of AES Interface .
Name Client Project

Elavarasan Chokkalingam TI TDA54

Anburaja Shanmugam Rambus Fuji

Ansia Liji COE AI validation

Rohith Samuel Ronald Rambus EIP161

Sheril Kiruba Richard ST Avedon

Anirban Guha ST Barolo

1. Pinnacles
Janakiraman Balraj ST
2. Farosh

Sindhu Guddampally
Rambus AES -FUJI
Rajanna
Status

1.Working on McASP,DCC2 and ATL modules Action Item closure for Testplan.
2.Reading specs for VPAC module for Testplan development.
3.Ramping up new joineers for analog modules and going through the 6 Analog modules specs for testplan
review
4.checked in completed Action item testplan of DMPAC and NPAC

Working on creating testcases as per testplan,

- Boot status check test created. Bug in boot status, Jira ticket created. Update pending from designer to
validate the check.
- Working on SRAM health check testcase.

1.Worked on validation of AI DV flow tool for feature extraction.

2.Tested AI DV flow tool to generate test name to verify particular features.
3.Worked on simulation and debugging of CV32E40S core Helloworld testcase.
4.working on simulation and debugging of RISCV debug testcases for CV32E40P core

1. Worked on Fixed Latency mode checker

2. Analysed the Python environment test and sent clarification mail regarding latency being varied at each
packet.
3. Working on Dynamic Latency mode checker.
4. Working on Static bypass and no classification latency checks.

1.Worked on AFC testcases for corner cases, error scenario implementation

2. Worked on Dither controller sample test case implementation
3. Worked on verifying the afc and dither block
4. started coverage implementation
5.started regression work on these blocks

Discussions on TB improvement

Pinnacles:
1. Worked on failures in A1 chip's new tag release.
2. Worked on implementation of checker for A1 chip.
3. Worked on CC and FC closure.
Farosh:
1. Worked on predictor implementation on PLL
2. Worked on SVA and Monitor developement.
3. Worked on TB top for new released tagged.

working on Driver updates for AES-FUJI interface.

Name Client Project

Elavarasan Chokkalingam TI TDA54

Anburaja Shanmugam
Ansia Liji
Rohith Samuel Ronald
Sheril Kiruba Richard
Anirban Guha
Janakiraman Balraj

Sindhu Guddampally Rajanna

Status

1.McASP,DCC2 and ATL modules Action Item are done for Testplan.
2.Reading specs for VPAC module for Testplan development.
3.Ramping up new joineers for analog modules and going through the 6 Analog modules specs for testplan review
4.checked in completed Action item testplan of DMPAC and NPAC
Name Client Project

Elavarasan Chokkalingam TI TDA54

Anburaja Shanmugam
Ansia Liji
Rohith Samuel Ronald
Sheril Kiruba Richard
Anirban Guha
Janakiraman Balraj
Sindhu Guddampally Rajanna
Status

1.McASP,DCC2,DMPAC,NPAC and ATL modules testplan are checked in .

2.Reading specs for VPAC module for Testplan development.
3.Ramping up new joineers for analog modules and going through the 6 Analog
modules specs for testplan review