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Ashwini Patil ASIC Verification Engr 4plus

Ashwini Patil seeks a senior verification engineer position. She has over 4 years of experience in ASIC verification. She has worked with SystemVerilog and UVM based verification environments for IP and SoC level verification. Some of her project experiences include NoC verification for an NXP chip, enhancing a digital motion processor, and verifying RISC cores including RISC-V and SPARC architectures. Her skills include Verilog, SystemVerilog, UVM methodologies, protocols like AXI and verification tools from major EDA vendors. She holds an MTech in VLSI and Embedded Systems and a BTech in Electronics and Communications.

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82 views

Ashwini Patil ASIC Verification Engr 4plus

Ashwini Patil seeks a senior verification engineer position. She has over 4 years of experience in ASIC verification. She has worked with SystemVerilog and UVM based verification environments for IP and SoC level verification. Some of her project experiences include NoC verification for an NXP chip, enhancing a digital motion processor, and verifying RISC cores including RISC-V and SPARC architectures. Her skills include Verilog, SystemVerilog, UVM methodologies, protocols like AXI and verification tools from major EDA vendors. She holds an MTech in VLSI and Embedded Systems and a BTech in Electronics and Communications.

Uploaded by

Ashwini Patil
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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ASHWINI PATIL

[email protected]
Mobile: +91-9886432273

Education
Date Educational Institution Degree
201 Sri Sidhartha University, Tumkur (SSIT College) MTech in VLSI and Embedded Systems
2
201 VTU University, Karnataka (REC, Bhalki) Engineering in Electronics and Communications
0

Skills
 HDL / HDVL : Verilog, System Verilog
 EDA tools : VCS, Cadence NCSim, Mentor Graphics QuestaSim
 Methodology : UVM
 Protocols : AXI3, AXI4, AHB, ACE

Work Experience Summary


● 4+ years of experience in ASIC Verification
● Worked in SV-UVM based verification environment
● IP and SoC-level Verification
● NoC Verification

Professional Summary
Date Company Position
March 2020 – Till Date Einfochips Pvt Ltd Senior Verification Engineer
March 2017 – March 2020 Sankalp Semiconductor Senior Verification Engineer
April 2016 – March 2017 Emupro Consulting Pvt Ltd Verification Engineer
July 2015 – April 2016 CVC Pvt Ltd ASIC Verification Trainee Engineer
Jan 2013 – Feb 2015 AIET college Gulbarga Assistant Professor

Work Experience

Einfochips Pvt Ltd


Enhanced Digital Motion Processor Verification
Enhanced digital motion processor (eDMP) is based on a Load-Store ISA, This IP focuses on motion
processing for sensor products with limited memory for code and data. It is designed for applications requiring
much higher bandwidth and target to support all the motion functions of future product .

Roles and Responsibility:


 Developed verification and test plan for eDMP
 Developed direct and random test cases for eDMP IP
 Developed performance monitor check the instruction clock cycles for the instructions.
 Working on functional coverage and code coverage
S ankalp Semiconductor

LS1028 NoC verification (Client- NXP)


There are several NoC blocks used in LS1028 chip. This project involves verification of all NoC blocks.
Few NoC blocks are AXI masters and few are AHB and ACE. AXI master blocks are memory blocks (MM,
MEM), ACE masters are A72.

Roles and Responsibilities:


 Created Verification Environment for all the NoC’s.
 Test-cases using interconnect test bench to run the test sequences
 Test bench and test case development
 Worked to replace NoC masters to AXI and AHB VIP’s from Synopsys
 Prepared Test plan for all NoC blocks to enhance coverage
 Developed Test Cases and Corner test Scenarios for all NoC blocks
 Verified all the NoC blocks in LS1028
 Developed scenario for all AXI, ACE and AHB features improving functional coverage
 Generated functional and code coverage for the RTL verification sign-off
 Sync-up with team, multiple development sites and client

Detection of weak checkers and incorrect design tie-off’s signal using certitude

Certitude is a synopsys functional qualification tool and helps in identifying weak and missing
checkers in the test- bench environment. It can also be deployed to detect wrong design tie-offs, which can
lead to undetected bugs in the design much earlier in the design cycle. The tool accomplishes this by
injecting faults at ports of modules, assignments, registers and any chosen signals of design and expects
for failures in the instrumented test cases.

Roles and Responsibilities:


 Developed Test Cases and Corner test Scenarios for design tie-off’s
 Developed Test Cases to detect weak checkers

EE muPro Consulting Pvt Ltd

Verification of high performance PHNXR5 RISC core


PHNXR5 core is ASIC based RISC-V 3 stage core. Core has Harvard memory style to speed the core
operations. Depending on the instruction, the controller can generate the control signals to drive the data to
ALU and resultant data can write back to destination register file. Work on the reference model (SPIKE) to
compare the core values. Work on the functional and core coverage of PHNXR5 core.

Roles and Responsibilities:


 In-order 32-bit RISC-V based ISA RISC core
 Single thread execution
 Supports for custom instructions
 Verified Load and store memory operations
 Test bench and test case development
 ELF file generations and loading to test bench

Verification of ER5C RISC core and EMIC 32-bit CPU

ER5C and EMIC module can fetch PC can read value from the program memory and decoder can
decode the instructions and generate the control signal to execute the ISA specified operations. ALU
resultant data can write into destination register file. We have illegal data and address exception address
generation logic. For every test case, we can generate configurable the trace report. We can handle the 8
interrupts for external operations. Work on the core block and top-level verification model in UVM. Work on
the reference model (SPIKE) to compare the core values. Work on the functional and core coverage of ER5C
and EMIC.

Roles and Responsibilities:


 Support program to run in User and Machine mode
 Verified Load and Store operations
 Test bench and test case development
 ELF file generations and loading to test bench
 Wrote the separate UVC for each sub-module
 Wrote the direct and random test-cases
 Written self-checking assembly level test

Academic Project
Development of 32-bit SPARC-V8 processor block in verilog
Organization: ISRO Bangalore
Language: Verilog

Description:
SPARC-V8 is a 32-bit RISC instruction set architecture (ISA) developed by Sun Microsystems. A reusable
verification component for SPARC-V8 IU is developed in Verilog. Instructions of SPARC-V8 are verified with the
reference model written in high level language which implements, SPARC instruction which includes read/write
status register, push/pop a register window and ALU instructions.

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