Chapter-4

Instruction sets Architecture

• Instruction types
• Instruction formats
• Addressing modes
• Instruction cycle
Instruction Set Architecture
• An instruction is an order given to a computer processor by
a computer program.
• Instruction set is the complete collection of instructions
that are understood by a CPU.
• Instruction set architecture is the structure of a computer
that a machine language programmer must understand to
write a correct program for that machine.
• It is also the machine description that a hardware designer
must understand to design a correct implementation of the
computer.
• It is the set of the instructions that the
Microprocessor/CPU can execute.
• It has its own structure/formats and elements

Instruction Set Architecture
• Refers to the part of a computer architecture related to programming, which includes
the native commands and operations a processor can execute.

• It serves as the interface between software (compilers, operating systems,

applications) and hardware (the processor).

• The ISA def in es how software controls the processor's behavior and utilizes its
features.

• A t t h e l o w e s t l e v e l , e a c h i n s t r u c t i o n i s a s e q u e n c e o f
0s and 1s that describes a physical operation the computer is to perform (such as "
Add").

• Depending on the particular instruction type, the specif ication of special storage areas
called registers that may contain data to be used in carrying out the instruction, or the
location in computer memory of data.

Instruction Set Architecture (ISA)
Instruction set is the boundary where the computer designer and
computer programmer see the same computer from different
viewpoints.
From the designer, point of view, the computer instruction set
provides a functional description of a processor, that is :
(i) detailed list of the instructions that a processor is capable of
processing.
(ii) describes of the types/locations/access methods for
operands.
The common goal of computer designer is to build the hardware
for implementing the machine's instructions for CPU.
Cont….
From the programmer's point of view, the user must
understand machine or assembly language for low-level
programming.
Moreover, the user must be aware of the register set,
instruction types and the function that each instruction
performs.
However, our main focus is the programmer's viewpoint
with the design of instruction set.

Instruction Types
Refers to the categories of instructions in an Instruction Set Architecture (ISA),
which determine the kinds of operations a processor can perform.
These are generally classif ie d based on the function they serve within the
computer's operations.
Data transfer: These instructions transfer data from one location in the computer
to another location without changing the data contents.
These instructions are used to move data between memory, registers, and I/O
devices.
Examples:
LOAD: Transfer data from memory to a register.
STORE: Transfer data from a register to memory.
MOV: Move data between registers.
PUSH / POP: Push data to or pop data from a stack.
IN / OUT: Transfer data between I/O devices and registers.
The most common transfer are between:
Resister to register.
Memory to register.
Register to memory.
Register to I/O part and vice versa.






Instruction Types
Arithmetic Instructions
Perform mathematical operations on numerical data and Carry out computations such
as addition, subtraction, multiplication, and division.
Examples:
ADD: Add two values.
SUB: Subtract one value from another.
MUL: Multiply two values.
DIV: Divide one value by another.
INC / DEC: Increment or decrement a value by 1.
Logical Instructions
• Perform bitwise operations on data and Manipulate individual bits or test conditions.
Examples:
AND: Perform a bitwise AND operation.
OR: Perform a bitwise OR operation.
XOR: Perform a bitwise XOR operation.
NOT: Perform a bitwise NOT operation (complement).
TEST: Test specific bits for conditions.
Instruction Types
Control Flow Instructions
Change the sequence of program execution and alter
the normal f lo w of execution based on conditions or
explicit jumps.
Examples:
Unconditional Jumps:
• JMP: Jump to a specified address.
Conditional Branches:
• BEQ: Branch if equal.
• BNE: Branch if not equal.
• BLT: Branch if less than.
• BGT: Branch if greater than.
Function/Procedure Control:
• CALL: Call a subroutine.
• RET: Return from a subroutine.
Instruction format
Describe the structure and layout of an instruction in a
computer's Instruction Set Architecture (ISA).
They def in e how information such as operation codes
(opcodes), operands, addressing modes, and other control
d at a is org anized in t he b inar y rep resent at ion of an
instruction.
Some operation codes deal with more than one operand; the
locations of these operands may be specif ie d using any of
the many addressing schemes.
The bits of the instruction are divided into groups called
fields.
1. An operation code f ield that specif ies the operation to be
performed.
2. An address f ield that designates a memory address or a
processor registers.
3. A mode f ie ld that specif ie s the way the operand or the
effective address is determined.
Instruction format
In order to execute the instruction CPU needs to know three
things.
Operation code (opcode): specif ies the type of action to be
performed
Example: add, sub, mul, div
Opera nds a re the da ta on which the opera tion is to be
performed.
MOV B, A Here MOV is operation and (B & A) are operands.
ADD B Here ADD is operation and (B) is operand.
Operand can be place either in one of the processor register or
in memory.
Operands residing in memory are specif ied with their memory
address
Addressing mode: The way in which the operand is taken from
register or memory.

Instruction format
Mode Operation code Address/data
Addressing mode opcode operands

|-----------------------------Machine instruction format----------------------|

Indicate the data or memory locations to operate

on.

Identifies the instruction type.

Indicates the addressing mode for operands.

Instruction classification
Evaluate X=(A+B) * (C+D)
Assume the instruction C= Three address instructions
A+B 1. ADD A, B, R1;R1 ← M[A] + M[B]

Three address instructions 2. ADD C, D, R2 ; R2 ← M[C] + M[D]

Syntax: opcode, source1, 3. MUL R1, R2, X; M[X] ← R1 * R2
source2,destination Two address instructions
Eg: ADD A,B, C
1. MOV A, R1; R1 ← M[A]
C ->[A]+[B]
2. ADD B, R1 ; R1 ← R1 +M[B]
Two address instructions 3. MOV C, R2; R2 ← M[C]
Syntax: opcode, source, destination 4. ADD D, R2 ; R2 ← R2 +M[D]
Eg: ADD A, B 5. MUL R2, R1;R1 ← R1 * R2
B = [A]+[B] 6. MOV R1, X; M[X] ← R1
MOVB,C
C -> [B]
Instruction classification
One-Address
1. LOAD A ; AC← M[A]
2. ADD B ; AC← AC + M[B]
One address instructions
3. STORE T; M[T]← AC
Syntax: opcode, source
4. LOAD C ; AC← M[C]
LOAD A (copies content of memory
location A to accumulator) 5. ADD D ; AC← AC + M[D]

STORE C (copies content of accumulator 6. MUL T ; AC← AC *M[T]

to memory location C) 7. STORE X ; M[X] ← AC
Zero-address instructions stack operation Zero-Address
Syntax: opcode 1. PUSH A ; Top Of Stack← A
Eg: PUSH A 2. PUSH B ; TOS← B
PUSH B, POP C 3. ADD ; TOS← (A + B)
4. PUSH C ; TOS← C
5. PUSH D ; TOS← D
6. ADD ; TOS← (C + D)
7. MUL ; TOS← (C+D)*(A+B)
8. POP X ; M[X] ← TOS
Addressing mode
Describe how an instruction specif ies the location of its operands
(data or memory).
They are a crucial aspect of the Instruction Set Architecture (ISA)
as they def ine how the processor accesses data required for
operations.
The operation f ield of an instruction specif ies the operation to be
performed.
This operation must be executed on some data stored in
computer registers or memory.
The way the operands are chosen during program execution in
dependent on the addressing mode of the instruction.
Addressing Mode Classification
Addressing modes can be grouped by where the operand is stored:
• Register-Based Addressing: Operands are in CPU registers.
• Memory-Based Addressing: Operands are in memory, specified
by direct, indirect, indexed, or base-relative modes.
Cont…..
The addressing mode specif ies a rule for interpreting or
modifying the address f ield of the instruction before the
operand is actually referenced.
1. Immediate Addressing Mode
2. Register Addressing Mode
3. Register Indirect Addressing Mode
4. Direct Addressing Mode
5. Indirect Addressing Mode
6. Implied Addressing Mode
7. Relative Addressing Mode
8. Indexed Addressing Mode
9. Base Register Addressing Mode
10. Autoincrement or Autodecrement Addressing Mode
Addressing mode
Immediate Addressing Mode

The operand is specified with in the instruction and operand itself is provided in
the instruction rather than its address.

ADD R1, R2, #10, Adds the immediate value 10 to the contents of register R2
and stores the result in R1.

Move Immediate

• MOVI A , 15h, A ← 15h Here 15h is the immediate operand

Add Immediate

• ADDI A, 3Eh, A ← A + 3Eh Here 3Eh is the immediate operand

Direct Addressing Mode
The memory address of the operand is directly specif ied in
the instruction.
LOAD R1, 1000, Loads the value from memory address 1000 into
Indirect Addressing Mode
The instruction specif ie s a register or memory location
containing the address of the operand.

LOAD R1, (R2), Loads the value from the memory

address stored in R2 into R1.
Addressing mode
Register Addressing Mode
The operand is specified with in one of the processor register.
Instruction specifies the register in which the operand is stored.
ADD R1, R2, R3, Adds the contents of R2 and R3, and stores the result in R1.
MOV C , A C ← A Here A is the operand specified in register
ADD B, A ← A + B Here B is the operand specified in register

Register Indirect Addressing Mode

The instruction specif ie s the register in which the memory address of
operand is placed.
It do not specify the operand itself but its location with in the memory where
operand is placed.
MOV A , M A ← [[H][L]]
Example: Find out the effective address of operand and operand value by
considering different addressing modes.
Memory
Address
Load to Mod
PC 200 200 AC e
• Memory having first instruction to
201 500
load AC
R1 400 • Mode will specify the addressing
202 Next
mode to get operand.
Instruction • Address field of instruction is 500.
AC
399
PC = Program Counter 450
400
R1 = Register 700
AC = Accumulator
500
800

600
900

702
325

800
300
1. Immediate Addressing Mode
Address Memory
Instruction
200 Load to Mod
AC e opcode 500
PC 200
201 500

R1 400 202 Next

Instruction • As instruction contains immediate number
500.
AC 399
450
400 Effective Address = Nil
700 Operand = 500
500
800 AC 500
600
900

702
325

800
300
2. Direct Addressing Mode

Address Memory
200 Load to Mod Instruction
AC e
201 opcode Address = 500
PC 200
Next • Instruction contains the address 500.
202 Instruction
R1 400 • So effective address of operand is 500.
• The data stored at 500 is 800.
AC 450
399
700
Effective Address = 500
400
Operand = 800
500 800
AC 800

600 900

702 325

800 300
3. Indirect Addressing Mode
Address Memory

200 Load to Mod

AC e Instruction
201
500
opcode Address = 500
PC 200 Next
202 Instruction • Instruction contains the address 500.
R1 400 • Address at 500 is 800.
399 450 • So effective address of operand is 800.
AC • The data stored at 800 is 300.
400 700
Effective Address = 800
500 800 Operand = 300

600 900 AC 300

702 325

800 300
4. Register Addressing Mode

Memory
Address
Load to Mod
200
AC e
PC 200 Address =
201 500
R1 400 202 Next
Instruction • Register R1 contains 400.
• A s ope ra n d is in re gist e r so n o a n y
AC memory location.
399 450
400 700 Effective Address = Nil
Operand = 400
500 800
AC 400

600 900

702 325

800 300
5. Register Indirect Addressing Mode

Address Memory
Load to Mod
200
AC e
201
500
PC 200
Next
202 Instruction
R1 400 • Register R1 contains 400.
• So effective address of operand is 400.
AC 399 450 • The data stored at 400 is 700.
400 700 Effective Address = 400
Operand = 700
500 800
AC 700

600 900

702 325

800 300
Instruction cycle
• The instruction cycle (fetch–decode–execute cycle, or simply
the fetc h- exec ute c yc le) is the c yc le that the c entral
processing unit (CPU) follows from boot-up until the computer
has shut down in order to process instructions.
• A program consisting of sequence of instructions is executed
in the computer by going through a cycle for each instruction.

1. Fetch: The CPU fetches the next instruction from memory (usually
from RAM) based on the Program Counter (PC).
The Program Counter keeps track of the address of the next instruction
to be executed. The instruction is fetched from the memory location
and placed into the instruction register (IR).
2. Decode: The fetched instruction is decoded to understand what
operation needs to be performed.
The control unit (CU) decodes the instruction to determine which
operation (such as addition, subtraction, move data, etc.) is required,
and which operands (data values) are involved. It also identif ie s the
address of operands if required.
3. Execute: The CPU performs the operation defined by the instruction.
The actual execution happens during this phase. This could involve
arithmetic/logic operations (using the Arithmetic Logic Unit or ALU).The
operands are processed, and the result is stored in a register or memory.
4. Store : The result of the execution is written back to memory or a
register.
If the instruction requires storing the result, the value is written back to a
specific memory location or a CPU register.