1

CHAPTER 3
THE CENTRAL PROCESSING
UNIT (CPU)
Outline
2

 What is an Instruction Set ?

 Elements of Machine Instruction
 Operand Locations
 Instruction Representation
 Instruction Types
 Addresses in Instructions
 Instruction Set Design
 Types of Operands

 Types of Operations

 Addressing Mode

 Instruction Format

 Processor Structure and Organization

What is an instruction set?
3

 The collection of different instructions that are

understood by a CPU

 Machine Code
 encoded in binary – for machines to work with

 For people: represent by assembly codes

 text – for people to work with
Elements of an Instruction
4

 Each instruction must contain all the information required

by CPU for execution
 These elements are :
 Operation code (Op code)
◼ Do this operation
 Source Operand(s) reference(s)
◼ With this/these operands
 Result Operand reference
◼ Put the answer here
 Next Instruction Reference (control flow!)
◼ When you have done that, do this...
◼ Implicitly the next instruction, in most cases
Operand Locations
5

 Where Can Operands Be?

 Main memory or virtual memory

◼ address must be supplied
 CPU register
◼ Implicit
◼ Explicitly using its unique number
 Immediate
◼ The value of the operand is contained in a field of instraction
 I/O device
◼ Specific I/O device
Instruction Representation
6

 Each instruction represented by sequence of bits

 Each instruction has a unique bit pattern
 Divided into fields

 For human consumption a symbolic representation is

used
 e.g. ADD, SUB, LOAD
 Operands can also be represented symbolically
 e.g. ADD A,B
Simple Instruction Format
7
Instruction Types
8

 An instruction set must be functionally complete

 Sufficient enough to express HLL programs
 Categories of instruction types
 Data processing
 Data storage (main memory)

 Data movement (I/O)

 Program flow /control

Number of Addresses
9

 One way of describing processor architectures

 What is the max number of addresses needed in an
instruction ?
 Most operations are:
◼ Unary
◼ Binary
 Typical are binary
◼2 addresses to reference operands
◼ 1 address to store the result of operations
◼ Implies max no addresses in an instruction to be three
address
Number of Addresses …
10

 Based on the no of addresses we have

 Three address instructions
 Two address instructions

 One address instructions

 Zero address instructions

Number of Addresses …
11

 Three address instructions

 The instruction contains both operands and the
destination of the result
◼ Operand 1, Operand 2, Result
◼ SUB Y,A,B
◼ a = b + c;

 Rarely used due to the length of

◼ addresses
◼ the resulting instruction word
Three address instructions
12

𝐴−𝐵
𝑌=
𝐶+𝐷×𝐸

Instruction Comment

SUB Y, A, B Y  A-B

MPY T, D, E T  DxE

ADD T, T, C T  T+C

DIV Y, Y, T Y  Y/T

(a) Three-address instructions

Number of Addresses …
13

 Two address instructions

 One address used to specify both
◼ Operand location
◼ Result location
◼ Example
◼ SUB Y, B
◼ a=a+b
 Very common in instruction sets
 Reduces length of instruction
 Requires some extra work
◼ Temporary storage to avoid altering the value of operand
Two address instructions
14

𝐴−𝐵
𝑌=
𝐶+𝐷×𝐸

Instruction Comment
MOVE Y, A YA
SUB Y, B Y  Y-B
MOVE T, D TD
MPY T, E T  TxE
ADD T, C T  T+C
DIV Y, T Y  Y/T
(b) Two-address instructions
Number of Addresses …
15

 One address instructions

 Twoaddresses are implied in the instruction
 Common in earlier machines
◼ The implied address being a CPU register called
accumulator
◼ Example
◼ ADD Y
◼ Acc = Acc + Y
One Address Instruction
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Instruction Comment
LOAD D AC  D
MPY E AC  ACxE
ADD C AC  AC+C
𝐴−𝐵 STOR Y Y  AC
𝑌=
𝐶+𝐷×𝐸 LOAD A AC  A
SUB B AC  AC-B
DIV Y AC  AC/Y
STOR Y Y  AC

(c) One-address instructions

Number of Addresses …
17

 Zero addresses instruction

 All addresses are implied
 Requires a special memory organization
◼ Stack
◼ Last in first out memory locations
◼ Stack based operations are
◼ Push
◼ Pop

◼ Operations use implicit stack

◼ Example:
◼ push a
◼ push b
◼ add (c=a+b)
◼ pop c
How Many Addresses ?
18

 More addresses
 More complex instructions
 More registers
 Inter-register operations are quicker
 Fewer instructions per program

 Few addresses in the instruction results in:

 More primitive instructions
 Less complex CPU
 Instructions with shorter length
 More total instructions in a program
Instruction Set Design
19

 A very complex task

 Because it affects so many aspects of the computer
design
 Instruction set
 boundarywhere computer designer and computer
programmer can view the same machine
 Programmer’s means of controlling the CPU
Instruction Set Design …
20

 Most important issues related to the design of

instruction set includes:

 Operation repertoire
 How many ops?
 What can they do?
 How complex are they?
 Built-In Data types supported
 Instruction formats – how to encode as binary values
 Length of op code field
 Number of addresses
Instruction Set Design …
21

 Registers
 Number of CPU registers available
 Which operations can be performed on which
registers?
 Addressing modes
Types of Operand
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 Machine instructions operate on data

 Categories of data
◼ Numbers
◼ Signed Integer / Unsigned Integer / Floating Point
◼ Characters
◼ ASCII etc.
◼ Logical Data
◼ Bits or flags
◼ Addresses
Types of Operations
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 Data Transfer
 I/O
 Arithmetic
 Logical
 Conversion
 System Control
 Transfer of Control
Data Transfer
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 Most fundamental type of instructions

 Must specify the following things
 Location of source and destination operands
◼ memory, register …
 Length of data to be transferred
◼ Full word, half word …
 Addressing mode of each operand
◼ E.g. move, store, Load, Push, Pop
 In terms of CPU action
 data transfer operations are the simplest type
Arithmetic
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 Performed by ALU
 Basic arithmetic operations provided by most machines
are:
 Add, Subtract, Multiply, Divide
◼ Signed Integer
◼ Floating point

 May include
 Increment
 Decrement
 Negate
 Absolute
Logical
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 Operations that manipulate individual bits of a word

 Bitwise operations
◼ AND, OR, exclusive-OR (XOR)
◼ NOT (one’s complement)

 In addition a variety of shifting and rotating functions

 Logical shift
◼ Shifts bits of word either to the left or right
◼ On one end the bit shifted out is lost
 Arithmetic shift
◼ Treats the data as a signed integer and does not shift the sign bit
 Rotate/Cyclic shift
◼ Preserves all of the bits being operated on
Shift and Rotate Operations
0
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logical
shift
shift in 0

arithmetic
shift
keep sign !

rotate
Conversion
28

 Change the format of data

 E.g.
◼ Binary to BCD
 binary 00001111 (1510) to
 packed BCD 0001 0101
BCD BCD
1 5
Input/Output
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 Transfer data
 From the computer to peripheral devices
 From peripheral devices to the computer system

 To be seen in detail in another chapter

Systems Control
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 Reserved for use by the operating system

 Instructions executed while the processor is in certain
privileged mode (kernel mode)
 Privileged
instructions
 CPU needs to be in specific state
Transfer of Control
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 Alter the flow of program

 Update the PC to a specific address
 Most common such type of operations are:
 Branch, Skip, Procedure call

 Branch
 Also called jump instruction
 Its operand is the address of the next instruction to be fetched and
executed
 Two types of branches
◼ Conditional and unconditional

 Unconditional branch
 e.g. branch to instruction at location xxxx
 Conditional Branch
 e.g. branch to instruction at location xxxx if result of
last operation was zero
Transfer of Control …
32

Branch Instruction ...

Transfer of Control …
33

Skip
 Implies that the next instruction be skipped

 Contains an implied address

 Can be of two types:

 Unconditional
◼ Skip (i.e unconditionally increment PC to skip the next instruction)
 Conditional
◼ Test some condition and skip if met/satisfied
◼ e.g. increment and skip next instruction if result is zero

ISZ Register1  increment & skip if zero

Branch xxxx  skip this if result was zero
ADD A
Transfer of Control …
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Procedure call
 Procedure
A self contained block of code
 It can be called/invoked from any point in the program

 Executing a procedure needs two basic instructions

A call instruction
 A return instruction
Transfer of Control …
35

 Three common places for storing the return address

◼ E.g call x

 Register
◼ RN  PC +1 ; PC  X
 Start of called procedure
◼X  PC + 1; PC  X + 1
 Top of stack
Nested Procedure Calls
36

start
address how does
of Proc1 machine
know
where
to go
back
start to?
address
of Proc2 STACK!
Addressing Modes
37

 The manner in which each address field specify

operand location

 Notations:
 A = Contents of an address field in the instruction
 R = Contents of an address field in the instruction that refers to a register
 (X) = Contents of memory location X or register X
 EA =Effective address of the location containing the referenced operand
Addressing Modes…
38

 Types of addressing modes

 Immediate

 Direct

 Indirect

 Register

 RegisterIndirect
 Displacement
Immediate Addressing
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 The instruction itself contains the operand

 Operand is part of instruction
 Operand = A
 E.g. ADD 5
◼ Add 5 to contents of accumulator
◼ 5 is operand

 No additional memory reference required after the

fetch of the instruction itself
 Fast
 Limited range
Immediate Addressing Diagram
40

Instruction

Opcode Operand
Direct Addressing
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 Address field contains address of operand

 Effective address EA = A
 Operand = (A)
 E.g. ADD A
◼ Add contents of memory location A to accumulator
 Single memory reference to access data
 No additional calculations to work out effective
address
 Limited address space
Direct Addressing Diagram
42

Instruction

Opcode A

Memory

Operand
Indirect Addressing
43

 A (the address field) refers to a memory location

which contains the address of operand

 EA = (A)
 Operand = ((A))
 E.g. ADD (A)
◼ Look in A, find address (A) and look there for operand
Indirect Addressing …
44

 Large address space

 2n ,where n = word length
 Multiple memory accesses to find operand
 Access the memory twice
 Hence slower
Indirect Addressing Diagram
45

Instruction

Opcode Address A
Memory

Pointer to operand

Operand
Register Addressing
46

 Similar to direct addressing

 Theaddress field refers to a register than a main
memory address
 EA = R
 Operand = (R )
 Limited number of registers
 Very small address field needed
 Shorter instructions
 Faster instruction fetch
Register Addressing…
47

 No memory access
 Very fast execution
 Very limited address space
Register Addressing Diagram
48

Instruction

Opcode Register Address R

Registers

Operand
Register Indirect Addressing
49

 Similar to indirect addressing mode

 Operand is in memory pointed to by contents of
register R
 EA = (R)
 Operand =((R ))
 Large address space (2n)
 Where n is the width of the register
 One fewer memory access than indirect addressing
Register Indirect Addressing Diagram
50

Opcode R
Memory

Registers

Operand
Displacement Addressing
51

 Very powerful addressing mode

 Combines
 Direct addressing and
 Register indirect addressing
 Instruction needs to have two address fields
 At least one of which is explicit
 EA = A + (R)
 Address field hold two values
 A = base value
 R = a register whose contents are added to A to produce
the effective address
Displacement Addressing Diagram
52

Instruction
Opcode R A
Memory
Registers

+ Operand
Relative Addressing
53

 A version of displacement addressing mode

 Implicitly references the PC register
R = Program counter, PC
 EA = A + (PC)

 Saves bits
Base-Register Addressing
54

 Referenced register contains memory address

R holds pointer to base address

 Address field contains the displacement from that

address
A holds displacement
Indexed Addressing
55

 Address field contains memory address

A = base
 The referenced register contains a displacement
from that address
R = displacement
 EA = A + ( R )
 Good for accessing arrays and performing iterative
operations
 EA =A+(R)
Indexed Addressing…
56

 Combinations
 Indirect addressing with indexing

 Post indexing
 The indexing performed after the indirection
 EA = (A) + (R)
 Good to access a block of data of a fixed format
 Pre indexing
 The indexing performed before the indirection
 EA = (A+(R))
 Used to construct a multiway branch table
Instruction Format
57

 It defines the layout of the bits of an instruction

 The two most basic design issue
 Instruction Length is affected by and affects:
◼ Memory size
◼ Memory organization
◼ Bus structure
◼ CPU complexity
◼ CPU speed
❖ Trade off between powerful instruction repertoire and saving space
 Allocation of Bits
◼ Trade-off between the number of opcodes and the power of the addressing

 What are the factors affecting the instruction format ?

 READING ASSIGNMENT!!!
Outline
58

 Processor Organization
 Register Organization
◼ User-visibleregister
◼ Control and status registers

 Instruction Cycle
 Data Flow
Processor Organization
59

 Requirements placed on the CPU:

 Fetch instructions
 Interpret instructions
 Fetch data
 Process data
 Write data

 To do all these things

 Processor needs to store data temporarily
◼ Registers are needed
Processor Organization…
60

 Simplified view of a CPU

61
Processor Organization…
62

 Detailed view of a CPU

Register Organization
63

 Registers
 CPU must have some working space
◼ Temporary storage
 Toplevel of memory hierarchy
 Number and function vary between processor designs

 One of the major design decisions

Register Organization
64

 Registers classified into two groups:

 User visible registers:
◼ referenced by assembly language instructions

 Control and status registers:

◼ Used by control unit
◼ To control the operation of the CPU
User Visible Registers
65

 Can be categorized as follows:

 General purpose registers
 Data registers

 Address registers

 Condition codes
User Visible Registers
66

 General Purpose Registers

 Canbe assigned variety of function
 May be true general purpose

 May be restricted

 May be used for data or addressing

 Data Registers
 Used only to hold data
◼ Accumulator
User Visible Registers…
67

 Address registers
 Can be
◼ General purpose
◼ Devoted to particular addressing mode
◼ Index registers, stack pointer, segment register
Design Consideration
68

 General or Specialized ?

 Make them general purpose

 Increase flexibility and programmer options
 Increase instruction size & complexity

 Make them specialized

 Smaller (faster) instructions
 Less flexibility
Design Consideration
69

 How Many GP Registers?

 Affects the instruction set design
 Between 8 – 32 --- optimum no of registers

 Fewer registers
 Results in more memory references
 More registers
 Does not noticeably reduce memory references

 There is, however, a new approach which finds advantage

of the use of hundreds of registers exhibited in some RISC
systems.
Design Consideration…
70

 How big?

 Address registers
 Large enough to hold full address
 Data Registers
 Large enough to hold full word
 Often possible to combine two data registers
Condition Codes
71

 Sets of individual bits

 Each bit set by CPU hardware:
 E.g. Arithmetic operation results could be
◼ Positive, negative, zero, overflow
 Can be read (implicitly) by programs
 e.g. Jump if zero
 Can not (usually) be set by programs
Control & Status Registers
72

 Employed to control the operation of the CPU

 Register essential during instruction cycle are
 Program Counter (PC)
◼ Contains the address of an instruction to be fetched
 Instruction Register (IR)
◼ Contains the instruction most recently fetched
 Memory Address Register (MAR)
◼ Contains the address of a location in memory
 Memory Buffer Register (MBR)
◼ Contains a word of data to be written to memory or the word
most recently read
Control & Status Registers…
73

 Program status word (PSW)

 A register that contain status information
◼ Sign of last result
◼ Zero
◼ Carry
◼ Equal
◼ Overflow
◼ Interrupt enable/disable
◼ Supervisor/kernel mode
 Usually contains
◼ Condition codes
◼ Status information
Example of Register Organization
74
Computer Function Reviewed

 Basic Function
 Execution of a program --- a set of instructions

 Processing of Instruction consists of two steps

◼ Fetch
◼ Execute
◼ Together called an Instruction cycle
Instruction Cycle
 Two steps:
 Fetch

 Execute
Fetch Cycle
 Program Counter (PC) holds address of next
instruction to be fetched
 Processor fetches instruction from memory location
pointed by PC
 Increment PC
 Unless told otherwise
 Instruction loaded into Instruction Register (IR)
78
Execute Cycle
 Processor interprets instruction and performs required
actions
 Processor-memory
◼ data transfer between CPU and main memory
 Processor -I/O
◼ Data transfer between CPU and I/O module
 Data processing
◼ Some arithmetic or logical operation on data
 Control
◼ Alteration of sequence of operations
◼ e.g. jump
 Combination of above
Example of Program Execution
80

 Internal CPU Registers

 Program counter (PC) Address of instruction
 Instruction register (IR) Instruction being executed

 Accumulator (AC) Temporary storage

 Partial list of opcodes

 0001 1 Load AC from memory
 0010 2 Store AC to memory

 0101 5 Add to AC from memory

Example of Program Execution
Instruction Cycle State Diagram
Interrupts
 Interruption of the normal sequence of execution
 Mechanism by which other modules (e.g. I/O) may interrupt normal
sequence of processing
 Provided to improve processing efficiency

 Common classes of interrupts

 Program
◼ e.g. overflow, division by zero
 Timer
◼ Generated by internal processor timer
◼ Used in pre-emptive multi-tasking
 I/O
◼ from I/O controller
 Hardware failure
◼ e.g. memory parity error
Interrupt Cycle
 Added to instruction cycle
 Processor checks for interrupt
 Indicated by an interrupt signal
 If no interrupt, fetch next instruction
 If interrupt pending:
 Suspend execution of current program
 Save context
 Set PC to starting address of interrupt handler routine
 Process interrupt
 Restore context and continue interrupted program
Transfer of Control via Interrupts
Instruction Cycle with Interrupts
Instruction Cycle (with Interrupts) -
State Diagram
Multiple Interrupts
 Two approaches to deal with multiple interrupts
 Disable interrupts
 Processor will ignore further interrupts whilst processing one
interrupt
 Interrupts remain pending and are checked after first
interrupt has been processed
 Interrupts handled in sequence as they occur
 Define priorities
 Low priority interrupts can be interrupted by higher priority
interrupts
 When higher priority interrupt has been processed,
processor returns to previous interrupt
Multiple Interrupts – Sequential
Disable interrupts
Multiple Interrupts – Nested
Prioritized interrupts
Time Sequence of Multiple Interrupts
Instruction Cycle
92

 Instruction cycle consists of

 Fetch

 Execute

 Interrupt

 Additional sub cycle to be added:

 Indirect cycle
Instruction Cycle ,Revised …
93

 Indirect addressing
 May require memory access to fetch operands
 Indirect addressing requires more memory accesses

 Can be thought of as additional instruction subcycle

Instruction Cycle ,Revised …
94

 Instruction cycle state diagram

Data Flow (Instruction Fetch)
95

 Depends on CPU design

 In general:

 Fetch
 PC contains address of next instruction
 Address moved to MAR
 Address placed on address bus
 Control unit requests memory read
 Result placed on data bus, copied to MBR, then to IR
 Meanwhile PC incremented by 1
Data Flow (Data Fetch)
96

 IR is examined
 If indirect addressing, indirect cycle is performed
 Right most N bits of MBR transferred to MAR
 Control unit requests memory read

 Result (address of operand) moved to MBR

Data Flow (Fetch Diagram)
97
Data Flow (Indirect Diagram)
98
Data Flow (Execute)
99

 May take many forms

 Depends on instruction being executed
 May include
 Memory read/write
 Input/Output

 Register transfers

 ALU operations
Data Flow (Interrupt)
100

 Simple
 Predictable
 Current PC saved to allow resumption after interrupt
 Contents of PC copied to MBR
 Special memory location (e.g. stack pointer) loaded to
MAR
 MBR written to memory
 PC loaded with address of interrupt handling routine
 Next instruction (first of interrupt handler) can be
fetched
Data Flow (Interrupt Diagram)
101
Prefetch
 Fetch accessing main memory
 Execution usually does not access main memory
 Can fetch next instruction during execution of
current instruction
 Called instruction prefetch
103
The ALU
 The ALU is the part of the microprocessor that
actually performs the arithmetic and logical
operations on data.
 The rest of the circuitry simply
 brings the data into the ALU,
 tells the ALU what to do with it, and

 takes the results out of the ALU.

Control Flags
Unit ALU
Registers Registers
The ALU
 Registers are used to:
 Bring data into the ALU
 Store the results of the ALU’s operations

 The control unit provides the signals that control the

operation of the ALU and the movement of data
into and out of the ALU

 Most of the operations in the ALU set the flags to

signify some condition.
The Control Unit
 Control unit needs to:
 Generate signals for each register transfer action and
other operations specified, and
 Be able to sequence through the steps for
fetching/executing the instructions in the program

Registers
Control
Unit
ALU
Control Unit Design
 Hardwired Control
 The control logic is implemented using flip flops, gates, etc
 The unit is designed specifically for the digital system being
designed
 Modifying it is very tedious

 Microprogrammed Control
 The control information is stored in a Micro-memory inside
the CPU
 The Microprogram memory is loaded with the sequence of
control signals needed to implement the different instructions
The Control Unit
 The system clock produces a continuous sequence of pulses in a specified
duration and frequency. A sequence of steps t0 , t1 , t2 , . . . , (t0< t1 < t2 . . .)
are used to execute a certain instruction.
 The op-code field of a fetched instruction is decoded to provide the control
signal generator with information about the instruction to be executed.