Unit 1

CPU Organization
Mrs. J. D. Pakhare
• Objectives:
• Upon completion of this unit you will be able to --

– Understand Fundamentals of CPU organization and operation

with selection and formats of instruction and data types.

– Understand overall design of instruction set processor as

illustrated by the CPU of a computer.
Processor Basics:
• Function of CPU- execute set of instructions stored in
external main memory(RAM).
– Transfer
– Execute
– Outputs data to main memory

• Program execution is carried out as-

– Transfer instructions and data (operands)from main
memory to registers.
– Execute instructions by stored sequence except branch
instructions.
– Transfer output from CPU registers to main memory.
• External communication
– Processor memory communication
– I/O mapped I/O, Memory mapped I/O
– User and supervisor mode
• External communication
– Processor memory communication without cache
– Processor memory communication with cache

Fig. Processor memory communication without cache

• In without cache , CPU communicates directly with main

memory.
• CPU is more faster than main memory
• Read/ write operations with CPU register are 5 to 10 times
faster than Read/ write operations with main memory.
External communication
• Processor memory communication with cache

Fig. Processor memory communication with cache

• Many computers have cache memory positioned between CPU and main
memory.
• CM is smaller and faster than main memory and may reside on the same
chip as the CPU.
• CM allows the CPU to perform memory load(read) or store(write)
operation in a single clock cycle.
• Cache Memory
• Cache Memory is a special very high-speed memory.
• It is used to speed up and synchronizing with high-speed CPU.
• Cache memory is used to reduce the average time to access
data from the Main memory.
• It is a smaller and faster than main memory and reside on the
same chip.
CPU communication with I/O devices:
• CPU communicates with I/O devices in the
same way as it communicates with
memory.
• I/O devices are associated with
addressable resisters called I/O ports.

• Memory mapped I/O

 In some computers there’re are no I/O
instructions.
 All I/O data transfers are implemented by I/O mapped I/O Memory mapped I/O

memory referencing instruction, is called I/O treated as IO and Both memory and IO treated
memory mapped I/O. memory treated as as memory.
memory
• i.e. memory locations and I/O ports
Control signals for IO Control signals for memory -
share the same set of addresses.
- ~IOR, ~IOW ~MEMR, ~MEMW

• I/O mapped I/O (Isolated)

 Computers that employ I/O instructions that are
distinct from memory referencing instructions is
called I/O mapped I/O.
 These instructions produces control signals to
respond to I/O ports not to memory.
User and Supervisor mode:
• Program executed by computer fall into two groups:
– User Mode
– Supervisor Mode

• User Mode:
– Handles a specific application.
– e.g. word processing, paint etc.
• Supervisor Mode (privileged mode)
– In normal operation CPU switches back and forth between user and supervisor
program.
• e.g. while executing user program there is need for information that is available only on
hard disk
• This causes supervisor to temporarily suspend the execution of user program and execute
the routine that initiate the required data transfer operation and the resume execution of
user program.
– It manages various routines of the computer system
– It is part of the computers OS.
– e.g. controlling graphics interface, transferring data between secondary and main
• Interrupt:
– Interrupt is a signal emitted by hardware or software when a
process or an event needs immediate attention.
• An interrupt is a signal sent to the processor that interrupts the current
process.
• An interrupt is a condition that causes the microprocessor to
temporarily work on a different task, and then later return to its
previous task.

– In the event of an interrupt, CPU suspend the execution of

current program and transfer to ISR(Interrupt Service Routine)

– As interrupt is particularly from IO devices , it require a rapid

response from the CPU.

– CPU checks frequently for the presence of interrupt requests.

CPU operation:
• Instruction Cycle:
– The sequence of operations performed by the CPU in processing an
instruction constitutes an instruction cycle.
– Time required to fetch and execute an entire instruction
is called instruction cycle.

– All instructions require two major steps:

• Fetch step- A new instruction is read form the external memory
• Execution step- Operations specified by instruction are executed.

• A check for pending interrupt request is included in the

instruction cycle.

• Clock Period (CPU Cycle time/ Tclock):

– Is the time required for the CPU micro-operation .
T =1/f
CPU Operation:

Fig. Flowchart summarizes the

main functions of CPU.
Accumulator based CPU:

Figure shows structure of a small accumulator

based CPU.
•Program control Unit:
•Instructions are fetched by PCU.
•Its main register is PC (program counter)
•PC stores instruction address only.
X1:=fi (X1,X2)
• Where X1 and X2 denotes CPU register
(AC,DR or PC) or memory location .
•Some instructions have an operand in an external
memory.
IR.AR:=M(PC)
• Transfers word from memory to CPU
• IR –opcode (op) is loaded in IR register
• AR-address is loaded in to the AR register.
• (e.g memory addressing instructions are load
and store)
• Memory addresses are stored in two address
registers in the PCU: PC and AR

•Data Processing Unit:

•Instructions are executed in the DPU.
•Instruction and data have some fixed word size n
bits .
•Instructions can be expressed by means of register
transfer operations. Fig. A small accumulator based CPU
• To perform data processing operation addition
as-
Z=X+Y

• Accumulator based CPU supports only single

address instruction, i.e. instruction with one
explicit memory address.
• AC and DR serves implicit operand location.
Programming considerations: load/store architecture
HDL Format Assembly language format Explanation
AC:=M(X) LD X Load X from M into acc AC
DR:=AC MOV DR, AC Move contents of AC to DR
AC:=M(Y) LD Y Load Y into acc AC
AC:=AC+DR ADD Add DR to AC
M(Z):=AC ST Z Store contents of AC in M.
• Instruction Format:
Operation code (opcode) operand1 operand2

• Addressing Modes:
– Different ways to specify operands is termed as addressing modes.
• Immediate address:
– Operation and its operands within the instruction. MVI A,99
• Direct address:
– Address of the operand is specified in the instruction.
• Indirect Address:
– Operands address is specified by register or memory pointer.
Types of instructions:
Zero, one, two and three address machine
• Zero address add instruction:
ADD (add top two operands X and Y from stack)

• One address add instruction:

ADD X (AC:=AC+X)

• Two address add instruction:

ADD X,Y (AC:=X+Y)

• Three address add instruction:

ADD Z,X,Y (Z:=X+Y)
Zero Address machine –

Stack is a memory area used to store data temporarily.

•The stack is a LIFO (last in, first out) data structure implemented in the RAM area .
Namely the first data element pushed on the stack, is the last to be retrieved.

•There is a special CPU register, called the stack pointer(SP) which is used to access the stack
area of memory.
•The Stack Pointer register will hold the address of the top
location of the stack.
Instruction contain no explicit address called zero
address machine
Implement X:=A*B+C*C
Program to execute operation
X:=A*B+C*C in one address , two
address and three address
processors
T- temporary register
RISC CISC
RISC stands for Reduced Instruction CISC stands for Complex
Set Computer. Instruction Set Computer.
RISC processors have simple CSIC processor has complex
instructions taking about one clock instructions that take up multiple
cycle. clocks for execution.
It has a hard-wired unit of It has a microprogramming unit.
programming.
The instruction set is reduced i.e. it The instruction set has a variety
has only a few instructions in the of different instructions that can
instruction set. Many of these be used for complex operations.
instructions are very primitive.

Instructions have simple , fixed Instructions have variable format

format with few addressing modes. with several addressing modes.
RISC CISC
Has simple instructions so program Has complex instructions so
length is long. program length is short.

Execution time is very less. Execution time is very high.

Code expansion can be a problem Code expansion is not a problem

Decoding of instructions is simple. Decoding of instructions is complex

The most common RISC Examples of CISC processors are

microprocessors are Alpha, ARM, the System/360,Motorola 68000
AVR, MIPS etc. family, AMD and Intel x86 CPUs.
RISC architecture is used in CISC architecture is used in
applications such as video applications such as security
processing, telecommunications, systems, home automation, etc.
and image processing.