8086 INTERRUPTS

Interrupt: The meaning of word interrupt is to break the sequence of operation. While processor is executing a
program, an interrupt stops the normal sequence of execution of instructions, diverts its control to execute some
other program called Interrupt Service Routine (ISR). After executing an ISR the control is transferred back
again to the main program i.e to the instruction which was being executed at the time interruption.

An 8086 interrupt can come from any one of the following four sources:

a) An external signal applied to the non-maskable interrupt (NMI) pin or to the interrupt (INTR) pin. An
interrupt caused by a signal applied to one of these inputs is called hardware interrupt.
b) The execution of the instruction INT n, where n is the interrupt type that can take any value between 00H
and FFH. This is called software interrupt.
c) An error condition such as divide-by-0, which is produced in the 8086 by the execution of the DIV/IDIV
instruction or the trap interrupt.
d) A trap interrupt

If an interrupt has been requested, the 8086 processes it by performing the following series of steps:

a) Pushes the content of the flag register onto the stack to preserve the status of the interrupt (IF) and trap flags
(TF), by decrementing the stack pointer (SP) by 2
b) Disables the INTR interrupt by clearing IF in the flag register
c) Resets TF in the flag register, to disable the single step or trap interrupt
d) Pushes the content of the code segment (CS) register onto the stack by decrementing SP by 2
e) Pushes the content of the instruction pointer (IP) onto the stack by decrementing SP by 2
f) Performs an indirect far jump to the start of the interrupt service routine (ISR) corresponding to the received
interrupt

Process of Interrupts

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INTERRUPT VECTOR TABLE:

Interrupt Vector Table of 8086

 When 8086 responds to an interrupt it refers to four memory locations present in the Interrupt Vector Table
(IVT) to get the new values of CS and IP.
 These memory locations are used to find the starting address of the ISR of the received interrupt in the
memory.
 In an 8086, the first 1 KB of memory from the addresses 00000H – 003FFH is set aside as table called
Interrupt Vector Table (IVT) for storing the interrupt vectors (IVs).
 Each interrupt vector indicates the starting address of the ISR of a particular interrupt in the memory.
 It contains four bytes, in which the lower two bytes are called offset and is loaded in the IP register and upper
two bytes are called segment and is loaded in the CS register.
 The following figure shows the 256 interrupt vectors arranged in the IVT in the memory. The IP value is
inserted as the lower order word of the interrupt vector and the CS value is inserted as higher order word of
the interrupt vector.
 Each interrupt vector is identified by a number called its type, which is an 8 bit number.
 The lowest five types are dedicated to specific interrupts such as the divide-by-0 interrupt, the single step
(Trap), the NMI interrupt, the one byte INT instruction interrupt and the overflow interrupt.
 Interrupt types 5-31 are reserved by the Intel for future use.
 The upper 224 interrupt types are available for the programmer to use for hardware/software interrupts.
 When the 8086 responds to a particular type of interrupt. It is automatically multiplies by 4 to find the desired
address in the vector table, from where it takes the interrupt vector and loads it in the IP and CS registers.
 For example, if the interrupt type 03h is currently received by the 8086, it goes to the memory address given
by 03h X 04h = 000Ch, to get the interrupt vector for type 03H.
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Dedicated Interrupt Types in 8086

The lowest five interrupt types in the 8086 (i.e., types 00H–04H) are dedicated to

1. Type 00H or divide-by-0 interrupt

Whenever the quotient from a DIV or IDIV operation is too large to fit in the result register, which occurs
while dividing a number by 0, or if the divisor is very small compared to the dividend, the 8086 automatically
generates a type 0 interrupt.

2. Type 01H or the single step (trap) interrupt

 The type1 interrupt is used for single step operation, in which the 8086 executes one instruction in the
program and then executer the ISR of the trap interrupt.
 In this ISR, we write the instructions to verify the contents of certain registers and memory locations and
display them in the output device such as monitor or seven segment display.
 If the expected data are present in the registers and/or memory locations the 8086 can be made to proceed to
the next instruction.
 If the trap flag in the 8086 is set, the 8086 automatically generates a type1 interrupt after each instruction in
the main program is executed.
 After executing the IRET instruction in the ISR, the 8086 goes to execute the next instruction in the main
program.

3. Type 02H or the NMI interrupt

 The 8086 generates a type 2 interrupt automatically when it receives a low to high transition on its NMI pin.
 The NMI interrupt cannot be disables by the software and hence it is used to inform the processor that it has
execute the corresponding ISR what for it was interrupted.
 This interrupt is used to save an important data when there is a power failure. It can be stored in a RAM
with battery backed up power.
 It can also be used to find hazards like smoke, fire or any abnormal temperature using sensors. The sensor
output is given to NMI pin which executes ISR of NMI, which is used to issue an alarm signal or shut off
the processor.

4. Type 03H or the one-byte INT instruction interrupt

 The type 03 interrupt is produced by the execution of the INT 03H instruction.
 It is a single byte instruction (CCH is the opcode of INT 03H) which is mainly used to implement a break
point function in the 8086 system for debugging a program.
 The break point technique allows us to execute all the instructions up to the inserted breakpoint in the main
program.
 the processor then goes on to execute the ISR of the break point interrupt.

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5. Type 04H or the overflow interrupt:

 The 8086 overflow flag (OF) is set if the result of an arithmetic operation on signed numbers is too large to
be stored in the destination register 0r memory location.
 There are two ways to detect and respond to an overflow error in a program:
1. Place the jump on overflow (JO) instruction immediately after the arithmetic instruction. If OF is set,
execution is transferred to the address specified in the JO instruction. At this address an error that responds to
the overflow in the required manner can be placed.
2. Place the interrupt overflow (INTO) instruction immediately after the arithmetic instruction. If OF is not
set, then INTO is treated as a NOP. If it is set 8086 generates type 4 interrupt after executing INTO.

Software Interrupts: (Types 00H-FFH)

 The INT instruction of the 8086 can be used to generate any one of the 256 possible interrupt types, which
are called software interrupts. The desired type of interrupt is specified as part of the INT instruction.
Ex: INT 03H ; it causes the 8086 to generate break point interrupt.
 When the 8086 executes the INT n instruction where n is the interrupt type, the 8086 pushes the content
of the flag register, CS and IP contents on to the stack and clear IF and TF.
 Then the 8086 goes to the memory address to obtain the interrupt vector for the type n from the IVT and
loads it in the IP and CS registers.
 This makes the 8086 executes the ISR for the interrupt type n.
 The IRET instruction at the end of the ISR makes the 8086 return to the main program to the instruction
next to the INT n instruction, to continue the execution of the main program.

Hardware Interrupts:

 Hardware interrupts are those interrupts which are caused by any peripheral device by sending a signal through a
specified pin to the microprocessor.
There are two hardware interrupts in 8086 microprocessor. They are:
 (A) NMI (Non Maskable Interrupt) – It is a single pin non maskable hardware interrupt which cannot be disabled.
It is the highest priority interrupt in 8086 microprocessor. After its execution, this interrupt generates a TYPE 2 interrupt.
 (B) INTR (Interrupt Request) – It provides a single interrupt request and is activated by I/O port. This interrupt
can be masked or delayed. It is a level triggered interrupt.

Priority among interrupts:

As far as the 8086 Interrupt Priority are concerned, software have the highest priority, followed by NMI followed
by INTR. Single step has the least priority.

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