MICROPROCESSORS AND

MICROCONTROLLERS(EECE3041)
Syllabus
L T P C
3 0 2
4
UNIT II
Instruction Set and Interrupts Addressing modes of 8086, instruction set of 8086,
assembly language programs (example programs), interrupts and interrupt service
routines, interrupt cycle of 8086, non-maskable interrupt, maskable interrupt (INTR).

2
Interrupts and Interrupt Service Routines
While CPU is executing a program, an interrupt breaks the
normal sequence of execution of instructions and divert its
execution to some other program called Interrupt Service
Routine (ISR)

Main Program Main Program Main Program Main Program

Printer Interrupt Modem Interrupt Modem Interrupt

Types of interrupts

Interrupts

Hardware Software
Interrupts Interrupts

Maskable Non-Maskable INT 0 –

Interrupts Interrupts INT 255
Hardware interrupts
• Hardware interrupts are those interrupts which are caused by any
peripheral device by sending a signal through a specified pin
to the microprocessor.

1. NMI (Non Maskable Interrupt) – It is a single pin non

maskable hardware interrupt which cannot be disabled. It is
the highest priority interrupt in 8086 microprocessor.

2. MI(Maskable Interrupt)- INTR(Interrupt Request) It provides

a single interrupt request and is activated by I/O port. This
interrupt can be masked or delayed.
Hardware interrupts
1. NMI (Non-Maskable Interrupt) : Ex: power
supply fail, over pressure in a steam boiler

Interrupts

Hardware
Interrupts

Maskable Non-Maskable
Interrupts Interrupts
1.NMI (Non maskable interrupt)

• This is a non-mask-able, edge triggered, high priority

interrupt.

• On receiving an interrupt on NMI line, the microprocessor

executes INT

• Microprocessor obtains the ISR(Interrupt Service Routine)

address from 0008H from the IVT (Interrupt Vector Table).

• It reads 4 locations starting from this address to get the values

for IP and CS to execute the ISR.

Hardware interrupts
2. Maskable Interrupt : Ex Key board, Printer etc..

Interrupts

Hardware
Interrupts

Non-
Maskable
Maskable
Interrupts
Interrupts
2. INTR- Maskable Interrupts
• INTR pin(Pin number 18) in Intel 8086 microprocessor is
for Interrupt. This is a mask-able, level triggered, low
priority interrupt. It is an interrupt request signal, which
is sampled during the last clock cycle of each
instruction to determine if the processor considered this as
an interrupt or not.

• When INTR=1 is then it looks for Interrupt Flag.

• If IF=1 , Maskable Hardware interrupts will be handled.

• If IF=0, such interrupts will be ignored.

• If INTR is enabled and NMI is disabled, then the
microprocessor first completes the current execution then
the microprocessor executes 2 INTA pulses.

• 1st INTA pulse – The interrupting device calculates

(prepares to send) the vector number.

• 2nd INTA pulse – The interrupting device sends the vector

number ‘N’ to the microprocessor.

• Now microprocessor multiplies N x 4 and goes to the

corresponding location in the IVT to obtain the ISR

address. INTR is a mask-able interrupt.

Software Interrupts
• These are instructions that are inserted within the program to

generate interrupts.

• There are 256 software interrupts in 8086 microprocessor.

• The instructions are of the format INT type where type ranges

from 00 to FF.

• The starting address ranges from 0000 H to 03FF H.

Interrupt vector
Size = 4 Bytes

Segment address (HIGH)

0003H
CS
0002H
Segment address (LOW)

00001H
Offset address (HIGH)

Offset address (LOW) IP

0000H

CS:IP ISR
Interrupt vector
• As for each type, four bytes (2 for NEW CS and 2 for NEW

IP) are required; therefore interrupt pointer table occupies

up to the first 1k bytes (i.e. 256 x 4 = 1024 bytes) of low

memory.

• The total interrupt vector table is divided into three groups

namely,

A. Dedicated interrupts (INT 0…..INT 4)

B. Reserved interrupts (INT 5…..INT 31)

C. Available interrupts (INT 32…..INT 225)

Interrupt vector table
03FFH
03FCH
INT 255
224 reserved for users -----
0080H
INT 32
007CH
INT 31
27 reserved for system use -----
0014H
INT 5
0010H
INT 4 (OVER FLOW)
000CH
INT 3 (BREAK POINT)
5 Dedicated interrupts 0008H
INT 2 (NMI)
0004H
INT 1 (SINGLE STEP)
0000H INT 0 (DIVIDE ERROR)
A. Dedicated interrupts (INT 0…..INT 4):
INT 0 (Divide Error)
• This interrupt occurs whenever there is division error i.e.
when the result of a division is too large to be stored. This
condition normally occurs when the divisor is very small as
compared to the dividend or the divisor is zero.
INT 1 (Single Step)
• The microprocessor executes this interrupt after every
instruction
• It puts microprocessor in single stepping mode i.e. the
microprocessor pauses after executing every instruction.
This is very useful during debugging.
INT 2 (Non mask-able Interrupt)
• The microprocessor executes this ISR in response to an
interrupt on the NMI (Non mask-able Interrupt) line.

INT 3 (Breakpoint Interrupt)

• This interrupt is used to cause breakpoints in the program.
It is caused by writing the instruction INT 03H or simply
INT.

INT 4 (Overflow Interrupt)

• This interrupt occurs if the overflow flag is set. It is used to

detect overflow error in signed arithmetic operations.
B. Reserved interrupts (INT 5…..INT 31):
• These levels are reserved by Intel to be used in higher
processors like 80386, Pentium etc. They are not available to
the user.

C. Available interrupts (INT 32…..INT 225):

• These are user defined, software interrupts.

• ISRs for these interrupts are written by the users to service
various user defined conditions.
• These interrupts are invoked by writing the instruction INT
n.
Example
• Using the Interrupt Vector Table shown below, determine the address of
the ISR of a device with interrupt vector 27H.
Answer: Address in table = 4 X 27H = 108H
(Multiply by 4 since each entry is 4 bytes)
Offset Low = [108] = 2A, Offset High = [109] = 33
Segment Low = [10A] = 3C, Segment High = [10B] = 4A
Address = 4A3C:332A = 4A3C0 + 332A = 4D6EAH
0 1 2 3 4 5 6 7 8 9 A B C D E F
00000 3C 22 10 38 6F 13 2C 2A 33 22 21 67 EE F1 32 25
00010 11 3C 32 88 90 16 44 32 14 30 42 58 30 36 34 66
......... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ...
00100 4A 33 3C 4A AA 1A 1B A2 2A 33 3C 4A AA 1A 3E 77
00110 C1 58 4E C1 4F 11 66 F4 C5 58 4E 20 4F 11 F0 F4
......... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ...
00250 00 10 10 20 3F 26 33 3C 20 26 20 C1 3F 10 28 32
00260 20 4E 00 10 50 88 22 38 10 5A 38 10 4C 55 14 54
......... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ...
003E0 3A 10 45 2F 4E 33 6F 90 3A 44 37 43 3A 54 54 7F
003F0 22 3C 80 01 3C 4F 4E 88 22 3C 50 21 49 3F F4 65
Web Reference

https://www.youtube.com/watch?v=8VSTGxm92T8
Thank you!

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