MICROPROCESSORS AND INTERFACING (5131)

MODULE – III
Interrupt mechanism of x86 & Interfacing of
chips
Interrupts

The meaning of ‘interrupts’ is to break the sequence of operation. While the CPU is executing a
program, on ‘interrupt’ breaks the normal sequence of execution of instructions, diverts its execution to some
other program called Interrupt Service Routine (ISR) or Interrupt Service Procedure (ISP).After executing
ISR , the control is transferred back again to the main program. Interrupt processing is an alternative to polling.
ISR is a program that tells the processor what to do when the interrupt occurs. At the end of the ISR the
last instruction should be IRET. After the execution of ISR, control returns back to the main routine where it
was interrupted.

Need for Interrupt: Interrupts are particularly useful when interfacing I/O devices that provide or require data
at relatively low data transfer rate.
Whenever a number of devices interrupt a CPU at a time, and if the processor is able to handle them
properly, it is said to have multiple interrupt processing capability. There are two interrupt pins in 8086. NMI
and INTR

Interrupts of 8086
Types of Interrupts:

There are two types of Interrupts in 8086. They are:

(i)Hardware Interrupts and
(ii)Software Interrupts

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Hardware Interrupts (External Interrupts).

Hardware interrupt is caused by any peripheral device by sending a signal through a specified pin to the
microprocessor. The 8086 has two hardware interrupt pins, i.e. NMI and INTR.
NMI is a non-maskable interrupt and INTR is a maskable interrupt having lower priority. One more
interrupt pin associated is INTA called interrupt acknowledge.

INTR
INTR is a maskable hardware interrupt. The interrupt can be enabled/disabled using STI/CLI
instructions or using more complicated method of updating the FLAG register with the help of the POPF
instruction.
When an interrupt occurs, the processor stores FLAGS register into stack, disables further interrupts,
fetches from the bus one byte representing interrupt type, and jumps to interrupt processing routine address of
which is stored in location 4 * <interrupt type>. Interrupt processing routine should return with the IRET
instruction.
The INTR interrupt is activated by an I/O port. If the interrupt is enabled and NMI is disabled, then the
microprocessor first completes the current execution and sends ‘0’ on INTA pin twice. The first ‘0’ means
INTA informs the external device to get ready and during the second ‘0’ the microprocessor receives the 8 bit,
say X, from the programmable interrupt controller.

NMI

NMI is a non-maskable interrupt. Interrupt is processed in the same way as the INTR interrupt. Interrupt
type of the NMI is 2, i.e. the address of the NMI processing routine is stored in location 0008h. This interrupt
has higher priority than the maskable interrupt.

SOFTWARE INTERRUPTS

Interrupts are generated by a software instruction and operate similarly to a jump or branch instruction.
 256 interrupts are there.
INT n is invoked as software interrupts - n is the type Number in the range 0 to 255(00 to FF).
They are divided into three groups
1. Type 0 to Type4 (Dedicated Interrupts)
TYPE 0 interrupt represents division by zero
TYPE 1 interrupt represents single-step execution during the debugging of a program. –
TYPE 2 interrupt represents non-maskable NMI interrupt. –
TYPE 3 interrupt represents break-point interrupt. –
TYPE 4 interrupt represents overflow interrupt.

2. Type 5 to 31(Not used by 8086, reserved for higher processor like 80286,80386….
3. Type 32-255(Available for user) - User defined interrupts
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Interrupt Vector Table (IVT)

For every interrupt, there is a fixed location in memory that holds the address of its ISR. The group of
memory locations set aside to hold the addresses of ISRs is called the interrupt vector table. An entry in the
Interrupt Vector is the address of the ISR.
The 1st 1Kbyte of memory of 8086 (00000 to 003FF) is set aside as s table for storing the starting
address of ISR. Since 4–bytes are required for storing starting addresses of ISRs, the table can hold 256 ISRs.
The starting address of an ISR is often called the Interrupt Vector or Interrupt Pointer. Therefore the table is
referred as Interrupt Vector Table. In this table, IP value is put in as lowword of the vector & CS is put in high
vector.
When an interrupt is occurred, the microprocessor stops execution of current instruction. It transfers the
content of program counter (CS and IP) into stack. After this, it jumps to the memory location specified by
Interrupt Vector Table (IVT). After that the code written on that memory area will execute.

The Operation of an Interrupt sequence (Interrupt Response) on the 8086

Microprocessor:
1. External interface sends an interrupt signal, to the Interrupt Request (INTR) pin, or an internal interrupt
occurs.
2. The CPU finishes the present instruction (for a hardware interrupt) and sends Interrupt Acknowledge (INTA)
to hardware interface.
3.The interrupt type N is sent to the Central Processor Unit (CPU) via the Data bus from the hardware interface.
4. The contents of the flag registers are pushed onto the stack.

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5. Both the interrupt (IF) and (TF) flags are cleared. This disables the INTR pin and the trap or single-step
feature.
6. The contents of the code segment register (CS) are pushed onto the Stack.
7. The contents of the instruction pointer (IP) are pushed onto the Stack.
8. The interrupt vector contents are fetched, from (4 x N) and then placed into the IP and from (4 x N +2) into
the CS so that the next instruction executes at the interrupt service procedure addressed by the interrupt vector.
9. While returning from the interrupt-service routine by the Interrupt Return (IRET) instruction, the IP, CS and
Flag registers are popped from the Stack and return to their state prior to the interrupt.

Dedicated Interrupt types

Intel has dedicated certain interrupt types for specific applications directly related to CPU operations. These are

1. Type 0: Divide by Zero Interrupt

o 8086 supports division (unsigned/signed) instruction. 8086 will automatically do a type 0 interrupt if
the result of DIV or IDIV operation is too large to fit in destination register.
o Type 0 is automatic and cannot be disabled i.e. non maskable.
o Users have to account it in the program where he/she uses DIV/IDIV instruction.
o Normally user will write an interrupt service procedure which takes desired action when an invalid
division occurs.
o To avoid this interrupt, user can check before division that divisor is not zero.

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2. Type 1: Single Step Interrupt (INT1)

o The microprocessor executes this interrupt after every instruction if the TF is set.
o It puts microprocessor in single stepping mode i.e. the microprocessor pauses after executing every
instruction. This is very useful during debugging.
o Its ISR generally displays contents of all registers. Its ISR address is stored at location 1 x 4 =
00004H in the IVT.

3. Type 2: NMI (Non Mask-able Interrupt) (INT2)

o This is the highest priority hardware interrupt and is non maskable. The input is edge triggered but is
synchronized with the CPU clock and must be active for two clock cycles to generate recognition.
o The interrupt signal may be removed prior to entry to the service routine.
o Since the input must make a LOW to HIGH transition to generate an interrupt, spurious transition on
the input should be suppressed.
o If the input is normally HIGH, the NMI low time to guarantee triggering is two CPU clock times.
o Its ISR address is stored at location 2 x 4 = 00008H in the Interrupt Vector Table (IVT).
o Basically NMI interrupt input is used for catastrophic failures for example power failure, time out of
system watchdog timer.

4. Type 3: One Byte Interrupt/Breakpoint Interrupt (INT3)

o This type is invoked by a special form of the software interrupt instruction which requires a single
byte of code space i.e. CCH (INT3).
o This interrupt is primarily used as a breakpoint interrupt for software debug.
o When we insert a breakpoint in program, the system executes instructions up to the breakpoint and
then goes to the breakpoint procedure.
o When user informs debugger program to insert breakpoint at some point in program, they actually do
it by temporarily replacing the instruction byte at that address with CCH i.e. code for INT3
instruction.
o Thus this single byte instruction can be mapped into the smallest instruction for absolute resolution
in setting breakpoints.
o Its ISR address is stored at location 3 x 4 = 0000CH in the IVT.
o A breakpoint ISR routine usually saves all the register contents on the stack.

5. Type 4: Interrupt on Overflow (INTO)

o This interrupt occurs if the overflow flag (OF) is set in the flag register.
o The OF flag is set if the signed result of an arithmetic operation on two signed number is too large to
be represented in destination register or memory location. Thus this interrupt is used to capture
overflow errors.
o Its ISR address is stored at location 4 x 4 = 00010H in the IVT.

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Iterrupt Priority

As far as the Interrupt Priority in 8086 are concerned, software interrupts (All interrupts except single step, NMI
and INTR interrupts) have the highest priority, followed by NMI followed by INTR. Single step has the least
priority.
The interrupt flag is automatically cleared as part of the response of an 8086 to an interrupt. This prevents a
signal on the INTR input from interrupting a higher priority interrupt service routine. The 8086 allows NMI
input to interrupt higher priority interrupt, for example suppose that a rising edge signal arrives at the NMI input
while the 8086 is executing a DIV instruction, and that the division operation produces a divide error. Since the
8086 checks for internal interrupts before it checks for an NMI interrupt, the 8086 will push the flags on the
stack, clear TF and IF, push the return address on the stack, and go to the start of the divide error service
routine.
The 8086 will then do an NMI interrupt response and execute non-maskable interrupt service routine. After
completion of NMI service routine an 8086 will return to the divide error routine. It will execute divide error
routine and then it will return to the main program (refer Fig. 9.4).

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DIFFERENT INTERFACING CHIPS

Interface is the path for communication between two components. Interfacing is of two types, memory
interfacing and I/O interfacing.
To communicate with the outside world microcomputers use peripherals (I/O devices). Commonly
used peripherals are: keyboard, mouse, printer, etc.
Peripherals are connected to the microcomputer through electronic circuits known as interfacing circuits.

8259 PIC
The 8259 is known as the Programmable Interrupt Controller (PIC) microprocessor.
Programmable interrupt controllers are used to enhance the number of interrupts of a microprocessor. 8259 is a
programmable interrupt controller which shows compatibility with 8085 microprocessor.
It is also known as a priority interrupt controller and was designed by Intel to increase the interrupt
handling ability of the microprocessor. An 8259 PIC never services an interrupt; it simply forwards the interrupt
to the processor for the execution of interrupt service routine.

Need of Programmable Interrupt Controller

In 8085 and 8086 there are five hardware interrupts and two hardware interrupts respectively. But there
are many devices connected to a processor. So, for such a case the processor must have more number of lines to
handle several interrupts.
But it is not practically possible to increase the number of lines each time with the increase in the
number of interrupts.
So, to overcome this problem 8259 PIC chip is used. 8259 allows the combining of multiple interrupts
and providing them to the processor based on priority through a common line.

Features of 8259 PIC:

 This chip is designed for 8085 and 8086.
 The 8259 programmable interrupt controller has 8 interrupt pins thus can handle 8 interrupt inputs.
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 By cascading 8259 chips, we can increase interrupts up to 64 interrupt lines.

 It reduces the software and real-time overhead generated due to handling multilevel priority interrupts.
 Clock cycle is not needed
 It can be programmed either in edge triggered, or in level triggered mode
 We can mask individual bits of Interrupt Request Register.
 It can be operated in various priority modes such as fixed priority and rotating priority.

Architecture of 8259

The figure below shows the architectural representation of 8259 programmable interrupt controller:

Data Bus Buffer:

It is used to transfer data between the microprocessor and internal bus.
8259 has tri-stated bidirectional 8-bit data bus buffer (i.e., D0 to D7) that interfaces with the internal bus of the
processor. The 8085 microprocessor sends/ receives control or status words to / from the 8259 using data bus
buffer.

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Read/ Write Logic:

This unit is responsible for controlling the internal read-write operations of the system. It sets the
direction of the data bus buffer. It contains initialization and operation command registers.
RD, WR, A0 and CS are the pins that are associated with this unit. These are active low pins for read and write.
Basically, these pins are used by the processor for read and write operations.
A low signal at CS i.e., chip select shows that now the communication has been set up between the processor
and 8259. This block works when the value of pin CS is 0.

Control Logic:
This unit is the heart of the architecture of 8259. It controls the overall operation of the system by
sending the INTR signal to the processor whenever an interrupt request is generated.
Also, it receives INTA signal by the processor when microprocessor demands for the address of the
interrupt service routine. The control logic is responsible for sending the address of the desired interrupt service
routine through the data bus.

Interrupt request register (IRR):

This unit stores the interrupt requests generated by the peripheral devices. We know that 8259 has 8
interrupt request pins (i.e., IR0 to IR7). So, the unit can store 8 interrupt requests that are requesting the service
from the processor.

Priority Resolver:
This logic unit decides that among the entire interrupt request present in the IRR which holds the highest
priority and needs to be executed first.
Suppose at the time of servicing an interrupt, another incoming interrupt request gets generated then that
request will be ignored as the one in-service is holding the highest priority.
But in case the incoming request has greater priority than the one which is being in current execution
then that respective bit will be set in ISR and INTR signal is sent to the microprocessor.
This simply means that only the interrupt holding the highest priority will be forwarded by the 8259 to
the processor.

In-service register:
Here the name of the unit is itself indicating the operation performed by it. This register unit stores the
interrupts which are currently being executed by the processor.
The priority resolver sets each bit of ISR and after getting interrupt word command by the processor, the
bits get reset. As the processor holds the ability to directly read the status of in-service register.

Interrupt mask register:

This register unit holds the masking bit of those interrupts which are to be masked. Through operation
command word (OCW) the processor sends the required information and programs the interrupt mask register.

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Cascade buffer/comparator:
As we have already discussed that by cascading multiple 8259, the number of interrupts handled by 8259
can be expanded up to 64. The unit allows the comparison of IDs of different 8259s cascaded together.
It permits the operation of the system in two modes: master mode and slave mode.
In the master mode of operation, it acts as a cascaded buffer. Whereas in slave mode, this unit acts as a
comparator.
Among the various cascaded 8259, one 8259 directly handles the interrupts by forming a connection
with the processor and it is known to be master 8259. While the other 8259s that interrupts the master 8259 are
known as slave 8259.
Each of the 8259s can be separately programmed as all of them holds a specific address. The cascading
pins of the master 8259, CAS0, CAS1 and CAS2 forms connection with the corresponding pins of slave 8259s.
For the slave devices, these pins act as input pins while for a master device these acts as output pins. An active-
low signal at SP/EN for a device shows that it is operating in slave mode.

BASIC CONNECTIONS BETWEEN 8086 AND 8259 PIC

COMMAND WORDS (CONTROL WORDS) OF 8259 PIC

The processor issues some words termed as command words to the ports so as to configure the 8259
better. There are several command words often classified as initialization command words and operation
command words.
8259 has four initialization command words namely ICW1, ICW2, ICW3, and ICW4 and three operation
command words namely as OCW1, OCW2, and OCW3.
Initialization command words(ICW) :
 ICW is given during the initialization of 8259 i.e. before its start functioning.
 ICW1 and ICW2 commands are compulsory for initialization.
 ICW3 command is given during a cascaded configuration.

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 If ICW4 is needed, then it is specified in ICW1.

 The sequence order of giving ICW commands is fixed i.e. ICW1 is given first and then ICW2 and then
ICW3.
 Any of the ICW commands cannot be repeated, but the entire initialization process can be repeated if
required.
Operating command words(OCW) :
 OCW is given during the operation of 8259 i.e. microprocessor starts using 8259.
 OCW commands are not compulsory for 8259.
 The sequence order of giving OCW commands is not fixed.
 The OCW commands can be repeated.

PRIORITY MODES OF 8259A PROGRAMMABLE INTERRUPT CONTROLLER

The various priority modes of 8259A are:
1. Fully nested mode
2. Special fully nested mode
3. Rotating Priority mode
o The rotating priority mode can be set as:
1. Automatic rotation
2. Specific rotation
4. Special masked Mode

OPERATING MODES OF 8259A PROGRAMMABLE INTERRUPT CONTROLLER

8259 has two operating modes:
1. Interrupt drive: In this mode, 8259 Interrupts the processor with the INT pin whenever it gets an
interrupt.
2. Polled Mode: In this mode, the INT output is not used. The microprocessor checks the status of the
interrupt request by issuing poll command.

8255A – PPI
8255A - Programmable Peripheral Interface(PPI)

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Intel 8255 is a peripheral interface (PPI) chip which is programmable. It is used for the connection of peripheral
devices and interfacing. We call Peripheral device also as Input Output device. We use Input Output ports for
the connection of Input Output devices. Hence 8255 is a programmable Input Output port chip.
It is a 40 pin chip available for dual line packaging. Power supply of +5 Volt DC is needed for its
working. It consists of two programmable Input Output ports having of size 8 bits and two programmable Input
Output ports of size 4 bits. We call them as Port A, Port B, Port C upper, and Port C lower, respectively. These
pins source 1 mA of current at 1.5V, when they are programmed to work as the Output pins.

Features of 8255A
The prominent features of 8255A are as follows −
 It consists of 3 8-bit IO ports i.e. PA, PB, and PC.
 Address/data bus must be externally demux'd.
 It is TTL compatible.
 It has improved DC driving capability.

Architecture (Block Diagram) of 8255 PPI

Data Bus Buffer

It is a tri-state 8-bit buffer, which is used to interface the microprocessor to the system data bus. Data is
transmitted or received by the buffer as per the instructions by the CPU. Control words and status information is
also transferred using this bus.
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Read/Write Control Logic

This block is responsible for controlling the internal/external transfer of data/control/status word. It accepts the
input from the CPU address and control buses, and in turn issues command to both the control groups.

CS
It stands for Chip Select. A LOW on this input selects the chip and enables the communication between the
8255A and the CPU. It is connected to the decoded address, and A0 & A1 are connected to the microprocessor
address lines.

Ports of 8255A
8255A has three ports, i.e., PORT A, PORT B, and PORT C.
 Port A contains one 8-bit output latch/buffer and one 8-bit input buffer.
 Port B is similar to PORT A.
 Port C can be split into two parts, i.e. PORT C lower (PC0-PC3) and PORT C upper (PC7-PC4) by the
control word.

These three ports are further divided into two groups, i.e. Group A includes PORT A and upper PORT
C. Group B includes PORT B and lower PORT C. These two groups can be programmed in three different
modes, i.e. the first mode is named as mode 0, the second mode is named as Mode 1 and the third mode is
named as Mode 2.

Operating Modes
8255A has three different operating modes −
 Mode 0 − In this mode, Port A and B is used as two 8-bit ports and Port C as two 4-bit ports. Each port
can be programmed in either input mode or output mode where outputs are latched and inputs are not
latched. Ports do not have interrupt capability.
 Mode 1 − In this mode, Port A and B is used as 8-bit I/O ports. They can be configured as either input or
output ports. Each port uses three lines from port C as handshake signals. Inputs and outputs are latched.
 Mode 2 − In this mode, Port A can be configured as the bidirectional port and Port B either in Mode 0 or
Mode 1. Port A uses five signals from Port C as handshake signals for data transfer. The remaining three
signals from Port C can be used either as simple I/O or as handshake for port B.

Programming the PPI

 Programming the chip involves only the writing of a particular word to the control register.
 The control register is an 8-bit register which can be written into.
 The bits of this word (called the control word) will decide the way the ports of the chip are to
configured.

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 The ports A, B and C are grouped into 2 groups – A and B

 Group A includes Port A and Port C upper
 Group B includes Port B and Port C lower
 Group a port can have 3 operational modes (0,1 and 2), but Group B ports have only 2 modes of
operation.

rogrammable Keyboard and Display Interface

8279 Programmable
Intel’s 8279 is a dedicated controller designed by Intel that offe rs simultaneous keyboard and display
offers
64 contact keys that are arranged in 8*8 matrix format. Also, through
operations. It provides interfacing for 64-contact
7 segment LEDs as well as other popular display devices.
8279 multiplexed interfacing can be obtained for 7-segment
It has a display RAM of 16*8 matrix, however; the arrangement can be organized in dual 16*4 RAM.
The RAM is loaded by the CPU however, once data loading is done, the 8279 performs data displaying and
refreshing functions.
It works in a way that the keyboard display interface keeps the keyboard under scanning in order to
check if any key is pressed. If a pressed key is detected, then the keycode of the pressed key is sent to the CPU.
Also, after the operation, the data which the CPU forwards it, is transmitte
transmittedd to the display device. These two
operations take place within the system in a synchronized manner without disturbing the other ongoing
operations of the CPU.

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Block Diagram (Architecture) of 8279

The functional block diagram of the Intel 8279 keyboard/display controller is shown below:

I/O Control and Data Buffer

This unit controls the flow of data through the microprocessor. It is enabled only when D is low. Its data buffer
interfaces the external bus of the system with the internal bus of the microprocessor. The pins A0, RD, and WR
are used for command, status or data read/write operations.

Control and Timing Register and Timing Control

This unit contains registers to store the keyboard, display modes, and other operations as programmed by the
CPU. The timing and control unit handles the timings for the operation of the circuit.

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Scan Counter
It has two modes i.e. Encoded mode and Decoded mode. In the encoded mode, the counter provides the binary
count that is to be externally decoded to provide the scan lines for the keyboard and display.
In the decoded scan mode, the counter internally decodes the least significant 2 bits and provides a
decoded 1 out of 4 scan on SL0-SL3.

Return Buffers, Keyboard Debounce, and Control

This unit first scans the key closure row-wise, if found then the keyboard debounce unit debounces the key
entry. In case, the same key is detected, then the code of that key is directly transferred to the sensor RAM along
with SHIFT & CONTROL key status.

FIFO/Sensor RAM and Status Logic

This unit acts as 8-byte first-in-first-out (FIFO) RAM where the key code of every pressed key is entered into
the RAM as per their sequence. The status logic generates an interrupt request after each FIFO read operation
till the FIFO gets empty.
In the scanned sensor matrix mode, this unit acts as sensor RAM where its each row is loaded with the
status of their corresponding row of sensors into the matrix. When the sensor changes its state, the IRQ line
changes to high and interrupts the CPU.

Display Address Registers and Display RAM

This unit consists of display address registers which holds the addresses of the word currently read/written by
the CPU to/from the display RAM.

Methods of Interfacing Keyboard with CPU

Mainly there are two ways by which the keyboard can be interfaced with the CPU, these are as follows:
 Interrupt Mode: In this mode of operation, the CPU continues to perform its original task until and
unless any request is generated to that a key is pressed and is required to be serviced.
 Polled Mode: In the polled mode of operation the CPU itself checks for any pressed key in a periodic
manner by reading the flags of 8279. So, in this case whenever the CPU gets a signal that shows the
pressed key then the requested service is served.

Operating Modes of 8279

Mainly, the operating modes of 8279 is classified as:

INPUT MODES
The input which is provided by the keyboard to the system specifies the input mode. This mode is classified into
the following categories:

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1. Scanned Keyboard Mode: In this operating mode, the key matrix is interfaced with either encoded or
decoded scan. In encoded scan, 8*8 keyboard is interfaced while in the decoded scan, 4*8 keyboard is
interfaced. The keycodes are stored in the FIFO RAM.
2. Scanned Sensor Matrix: This helps in interfacing the sensor array with 8279 by making use of an
encoder or decoder scan. Similar to scanner keyboard mode, 8*8 sensor matrix for encoder scan and 4*8
sensor matrix interfacing for decoder scan.
3. Strobed Input: This mode of operation, if control is not offered by the processor and the control line
shows low signal then the data present on the return lines is stored in FIFO RAM byte by byte.

OUTPUT MODES
This mode is also known as a display mode. It is further classified into two modes. This mode helps in selecting
the display options.
1. Display Scan: The 8279 generates 8 or 16 characters multiplexed displays that are organized in either
dual 4-bit or single 8-bit display units.
2. Display Entry: The data which gets displayed can be either displayed starting from either the right side
or left side.

DISPLAY MODES
This mode is associated with data display and has two further classifications.
1. Left Entry Mode: It is also known as typewriter mode. In this, the first type of character is present at
the left-most position while further incoming characters appear successively towards the right. This
means data begins to appear from the left side of the display unit. So, the bit value at address 0 in the
display RAM will appear at the left-most position whereas the bit value at address 15 will appear at the
right-most position.
2. Right entry Mode: This mode is also known as calculator mode. This is so because in the calculator the
first entered character appears at the rightmost position and then successively when a new character has
entered the position of the former one is shifted towards the left. Thus, in this mode, the first entry will
appear at the rightmost position but as soon as a new entry is made then the previous one will get shifted
towards the left by one and the present entry will take the rightmost position.

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